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CYM8301V33-12BGC

型号：

CYM8301V33-12BGC

品牌：

CYPRESS[ CYPRESS ]

页数：

9 页

PDF大小：

401 K

下载PDF手册
01  
PRELIMINARY  
CYM8301V33  
512K x 24 Static RAM Module  
Writing the data bytes into the SRAM is accomplished when  
the chip select controlling that byte is LOW and write enable  
(WE) input is LOW. Data on the respective input/output pins  
(I/O) is then written into the memory location specified on the  
address pins (A0 through A18). Asserting all the chip selects  
LOW and write enable LOW will write the entire da-  
ta(I/O0-I/O23) into the SRAM. Output enable (OE) is not looked  
into while in a WRITE mode.  
Features  
• High density 12- Mb SRAM Module  
• High Speed CMOS SRAMs  
• Access Times of 10 ns  
• Single 3.3V Power supply  
• Low active power(1620W at 10 ns)  
• TTL compatible inputs and outputs  
• Available in standard 119 ball BGA  
• Interface to Motorola DSP and Analog Devices  
Data bytes can also be individually read from the device.  
Reading a byte is accomplished when the chip select control-  
ling that byte is LOW and write enable (WE) HIGH while ouput  
enable (OE) remains LOW. Under these conditions, the con-  
tents of the memory location specified on the address pins will  
appear on the specified data input/output pins (I/O). Asserting  
all the chip selects LOW and write enable HIGH with output  
enable LOW will read the entire data (I/O0-I/O23) from the  
SRAM.  
Functional Description  
The CYM8301 is a 3.3V high performance 12 Megabit static  
RAM organized as a 512K words by 24 bits. This module is  
constructed from three 512K x8 SRAM dies mounted on a  
multi layer laminate substrate combined to form a 24 bit  
SRAM. CYM8301 is an ideal single chip solution for the Mo-  
torola’s DSP5630X or a two chip solution to Analog Devices  
ADSP2106XL.  
The data input/output (I/O0-I/O23) pins stay at high-imped-  
ance state when all the chip selects are HIGH or when the  
output enable (OE) is HIGH when in a READ mode. For further  
details, refer to the truth table in this datasheet.  
Each data byte is separately controlled by the individual chip  
selects(CE0/,CE1/CE2/). CE0/ controls I/O0-7. CE1/ controls  
I/O8-15. CE2/ controls I/O16-23.  
Functional Block Diagram  
A[18:0]  
I/O0-7  
8
I/O0-7  
CE0/  
WE/  
OE/  
CE0/  
A[18:0]  
A[18:0]  
I/O8-15  
8
I/O0-23  
I/O8-15  
24  
CE1/  
WE/  
OE/  
CE1/  
WE/  
OE/  
A[18:0]  
8 I/O16-23  
I/O16-23  
CE2/  
WE/  
CE2/  
OE/  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-05092 Rev. **  
Revised July 5, 2001  
PRELIMINARY  
CYM8301V33  
Selection Guide  
CYM8301-10  
CYM8301-12  
CYM8301-15  
Maximum Access Time (ns)  
10  
450  
90  
12  
420  
90  
15  
420  
90  
Maximum Operating Current (mA)  
Maximum Standby Current (mA)  
Shaded areas contain advance information.  
Pin Configurations  
119 BGA  
Top View  
1
2
3
4
5
6
7
A
B
NC  
NC  
A
A
A
A
A
NC  
A
A
CE0  
NC  
A
A
NC  
C
D
E
F
I/O12  
I/O13  
I/O14  
I/O15  
I/O16  
I/O17  
NC  
NC  
VDD  
VSS  
VDD  
VSS  
VDD  
VSS  
VDD  
VSS  
VDD  
VSS  
VDD  
A
CE1  
VSS  
VDD  
VSS  
VDD  
VSS  
VDD  
VSS  
VDD  
VSS  
VDD  
VSS  
NC  
A
CE2  
VSS  
VDD  
VSS  
VDD  
VSS  
VDD  
VSS  
VDD  
VSS  
VDD  
VSS  
NC  
A
NC  
VDD  
VSS  
VDD  
VSS  
VDD  
VSS  
VDD  
VSS  
VDD  
VSS  
I/00  
I/O1  
I/O2  
I/O3  
I/O4  
I/O5  
NC  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
NC  
G
H
J
K
L
1/O18  
I/O19  
I/O20  
I/O21  
I/O22  
I/O23  
NC  
I/O6  
I/O7  
I/O8  
I/O9  
M
N
P
R
T
VDD  
A
I/O10  
I/O11  
NC  
A
WE  
OE  
A
U
NC  
A
A
A
A
NC  
Current into Outputs (LOW) ........................................ 20 mA  
Maximum Ratings  
Static Discharge Voltage ........................................... >2001V  
(per MIL-STD-883, Method 3015)  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Latch-Up Current..................................................... >200 mA  
Storage Temperature .................................–65°C to +150°C  
Operating Range  
Ambient Temperature with  
Ambient  
Power Applied.............................................–55°C to +125°C  
Supply Voltage on VCC to Relative GND[1] ...... –0.5V to 4.6V  
Range  
Commercial  
Industrial  
Temperature[2]  
0°C to +70°C  
VCC  
3.3V ±5%  
3.3V ±5%  
DC Voltage Applied to Outputs  
in High Z State [1]...................................–0.5V to VCC + 0.5V  
–40°C to +85°C  
DC Input Voltage [1] ...............................–0.5V to VCC + 0.5V  
Shaded areas contain advance information.  
Notes:  
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.  
2. TA is the “Instant On” case temperature.  
Document #: 38-05092 Rev. **  
Page 2 of 9  
 
 
 
PRELIMINARY  
CYM8301V33  
Electrical Characteristics Over the Operating Range  
CYM8301-10  
CYM8301-12/15  
Parameter  
VOH  
Description  
Test Conditions[3]  
VCC = Min.,  
Min.  
Max.  
Min.  
Max.  
Unit  
Output HIGH Voltage  
2.4  
2.4  
V
IOH = –4.0 mA  
VOL  
VIH  
Output LOW Voltage  
Input HIGH Voltage  
VCC = Min.,  
IOL = 8.0 mA  
0.4  
0.4  
V
V
2.2  
VCC  
+ 0.3  
2.2  
VCC  
+ 0.3  
VIL  
IIX  
Input LOW Voltage[1]  
Input Load Current  
–0.5  
–10  
–10  
0.8  
+10  
+10  
–0.5  
–10  
–10  
0.8  
+10  
+10  
V
GND < VI < VCC  
µA  
µA  
IOZ  
Output Leakage  
Current  
GND < VI < VCC  
,
Output Disabled  
ICC  
VCC Operating  
Supply Current  
VCC = Max.,  
IOUT = 0 mA,  
f = fMAX = 1/tRC  
450  
150  
90  
420  
150  
90  
mA  
mA  
mA  
ISB1  
Automatic CE  
Power-Down Current  
—TTL Inputs  
Max. VCC, CE > VIH  
VIN > VIH or  
VIN < VIL, f = fMAX  
ISB2  
Automatic CE  
Max. VCC,  
Power-Down Current  
—CMOS Inputs  
CE > VCC – 0.3V,  
VIN > VCC – 0.3V,  
or VIN < 0.3V, f = 0  
Capacitance[4]  
Parameter  
Description  
Test Conditions  
Max.  
Unit  
CIN  
Input Capacitance  
Output Capacitance  
TA = 25°C, f = 1 MHz,  
VCC = 3.3V  
8
8
pF  
pF  
COUT  
AC Test Loads and Waveforms  
R1 317Ω  
ALL INPUT PULSES  
90%  
OUTPUT  
3.3V  
3.0V  
90%  
10%  
Z =50Ω  
0
OUTPUT  
R =50Ω  
10%  
L
R2  
351Ω  
GND  
5 pF  
≤ 3 ns  
≤ 3 ns  
= 1.5V  
VTH  
INCLUDING  
JIG AND  
SCOPE  
(b)  
1024V33–3  
(a)  
1024V33–4  
Notes:  
3. CE is a combination of CE1, CE2 and CE3  
4. Tested initially and after any design or process changes that may affect these parameters.  
Document #: 38-05092 Rev. **  
Page 3 of 9  
 
 
PRELIMINARY  
CYM8301V33  
Switching Characteristics [5] Over the Operating Range  
CYM8301-10  
CYM8301-12  
CYM8301-15  
Parameter  
Description[3]  
Min.  
10  
3
Max.  
Min.  
12  
3
Max.  
Min.  
15  
3
Max.  
Unit  
READ CYCLE  
tRC  
Read Cycle Time  
Address to Data Valid  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
10  
12  
15  
tOHA  
tACE  
tDOE  
tLZOE  
tHZOE  
tLZCE  
tHZCE  
tPU  
Data Hold from Address Change  
CE active to Data Valid  
OE LOW to Data Valid  
OE LOW to Low Z  
OE HIGH to High Z[6, 7]  
CE active to Low Z[7]  
CE inactive to High Z[6, 7]  
CE active to Power-Up  
CE inactive to Power-Down  
10  
6
12  
15  
7.2  
8.5  
0
3
0
0
3
0
0
3
0
5
5
6
6
7
7
tPD  
10  
12  
15  
WRITE CYCLE[8, 9]  
tWC  
tSCE  
tAW  
tHA  
Write Cycle Time  
10  
9
12  
9
15  
9
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CE active to Write End  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
9
9
10  
0
0
0
tSA  
0
0
0
tPWE  
tSD  
8
10  
6
11  
7
Data Set-Up to Write End  
Data Hold from Write End  
WE HIGH to Low Z[7]  
6
tHD  
0
0
0
tLZWE  
3
3
3
tHZWE  
WE LOW to High Z[6, 7]  
5
6
7
Notes:  
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of  
the specified IOL/IOH  
HZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.  
.
6.  
t
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.  
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of  
any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.  
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD  
.
Document #: 38-05092 Rev. **  
Page 4 of 9  
 
 
 
 
 
 
PRELIMINARY  
CYM8301V33  
Switching Waveforms  
Read Cycle No. 1[10, 11]  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
8301V33  
Read Cycle No. 2 (OE Controlled)[3, 11, 12]  
ADDRESS  
CE  
t
RC  
t
ACE  
OE  
t
HZOE  
t
DOE  
t
HZCE  
t
LZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA OUT  
DATA VALID  
t
LZCE  
t
PD  
I
t
PU  
CC  
V
CC  
50%  
50%  
SUPPLY  
CURRENT  
I
SB  
8301V33  
Write Cycle No. 1 (CE Controlled)[3, 13, 14]  
t
WC  
ADDRESS  
CE  
t
SCE  
t
SA  
t
SCE  
t
t
HA  
AW  
t
PWE  
WE  
t
t
HD  
SD  
DATA I/O  
DATA VALID  
8301V33  
Notes:  
10. Device is continuously selected. OE, CE = VIL.  
11. WE is HIGH for read cycle.  
12. Address valid prior to or coincident with CE transition LOW.  
13. Data I/O is high impedance if OE = VIH  
.
14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.  
Document #: 38-05092 Rev. **  
Page 5 of 9  
 
 
 
 
 
PRELIMINARY  
CYM8301V33  
Switching Waveforms (continued)  
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13, 14]  
t
WC  
ADDRESS  
CE  
t
SCE  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
OE  
t
t
SD  
HD  
DATA I/O  
DATA VALID  
IN  
NOTE 15  
t
HZOE  
8301V33  
Write Cycle No. 3 (WE Controlled, OE LOW)[3, 14]  
t
WC  
ADDRESS  
CE  
t
SCE  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
t
HD  
SD  
NOTE 15  
DATA I/O  
DATA VALID  
t
t
LZWE  
HZWE  
8301V33  
Note:  
15. During this period the I/Os are in the output state and input signals should not be applied.  
Document #: 38-05092 Rev. **  
Page 6 of 9  
 
PRELIMINARY  
CYM8301V33  
Truth Table  
CE1  
H
CE2  
H
CE3  
H
WE  
X
OE  
X
I/O0–I/O23  
High Z  
Mode  
DESELECT/POWER DOWN  
L
L
L
H
L
Data Out (I/O 0 - 23)  
I/O High Z  
Read  
L
L
L
H
H
L
Power Down  
Read  
L
H
H
H
Data Out (I/O 0 -7)  
I/O8-23 in High Z  
H
H
L
H
L
H
H
L
L
Data Out (I/O 8- 15)  
I/O 0 -7 in High Z  
I/O 16- 23 in High Z  
Read  
Read  
H
Data Out (I/O 16-23)  
I/O 0 -15 in High Z  
L
L
L
H
L
L
H
H
L
L
L
L
L
X
X
X
X
Data In (I/O 0 -23)  
Data In (I/O 0-7)  
Data In (I/O 8 - 15)  
Data In (I/O 16- 23)  
Write  
Write  
Write  
Write  
H
H
H
Ordering Information  
Speed  
Package  
Operating  
Range  
(ns)  
Ordering Code  
CYM8301V33 - 10 BGC  
CYM8301V33 - 12 BGC  
CYM8301V33 - 15 BGC  
CYM8301V33 - 15 BGI  
Name  
BG119  
BG119  
BG119  
BG119  
Package Type  
10  
119-Ball BGA  
Commercial  
Commercial  
Commercial  
Industrial  
12  
119-Ball BGA  
119-Ball BGA  
119-Ball BGA  
15  
15  
Document #: 38-05092 Rev. **  
Page 7 of 9  
PRELIMINARY  
CYM8301V33  
Package Diagram  
119-Ball BGA (14 x 22 x 2.4 mm) BG119  
51-85115  
Document #: 38-05092 Rev. **  
Page 8 of 9  
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
PRELIMINARY  
CYM8301V33  
Document Title: CYM8301V33 512 x 24 Static RAM Module  
Document Number: 38-05092  
REV.  
ECN NO.  
Issue Date  
Orig. of Change  
Description of Change  
New Data Sheet  
**  
107602  
07/17/01  
MEG  
Document #: 38-05092 Rev. **  
Page 9 of 9  
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