3
fax id: 2046
PRELIMINARY
CYM1836V33
128K x 32 3.3V Static RAM Module
lects (CS , CS , CS , CS ) are used to independently enable
Features
1
2
3
4
the four bytes. Reading or writing can be executed on individ-
ual bytes or any combination of multiple bytes through proper
use of selects.
• High-density 3.3V 4-megabit SRAM module
• 32-bit standard footprint supports densities from 16K
x 32 through 1M x 32
• High-speed CMOS SRAMs
• Access time of 25 ns
Writing to each byte is accomplished when the appropriate
chip select (CS) and write enable (WE) inputs are both LOW.
Data on the input/output pins (I/O) is written into the mem-
ory location specified on the address pins (A through A ).
0
16
— Low active power 1.6W (max.) at 20 ns
Reading the device is accomplished by taking the chip select
(CS) LOW while write enable (WE) remains HIGH. Under
these conditions, the contents of the memory location
specified on the address pins will appear on the data in-
put/output pins (I/O).
• 2.0V Data Retention (I
• SMD technology
• TTL-compatible inputs and outputs
• Available in 64-pin SIMM, 64-pin ZIP format or 72-pin
SIMM format.
= 0.8 mA, max.)
CCDRL
The data input/output pins stay at the high-impedance state
when write enable is LOW or the appropriate chip selects are
HIGH.
Functional Description
The CYM1836V33 is a 3.3V high-performance 4-megabit stat-
ic RAM module organized as 128K words by 32 bits. This mod-
ule is constructed from four 128K x 8 SRAMs in SOJ packages
mounted on an epoxy laminate board with pins. Four chip se-
Two pins (PD and PD ) are used to identify module mem-
ory density in applications where alternate versions of the
JEDEC-standard modules can be interchanged.
0
1
Pin Configurations
Logic Block Diagram
72-pin SIMM
Top View
64-pin ZIP/SIMM
NC
PD
1
3
5
Top View
NC
3
PD
0
2
4
2
PD
GND
GND
1
PD
6
8
0
2
3
7
9
PD
PD
1
1
PD -
OPEN
I/O
I/O
I/O
0
I/O
0
1
2
3
4
5
0
I/O
8
I/O
9
I/O
10
PD −OPEN
I/O
8
0
PD - OPEN
I/O
1
6
7
1
10
12
14
16
18
20
22
24
26
28
30
32
PD −OPEN
11
13
15
17
19
21
23
25
27
29
31
I/O
1
9
PD -
A −A
8
9
I/O
OPEN
GND
2
0
16
OE
WE
2
I/O
10
17
I/O
V
10
11
PD -
I/O
3
I/O
11
3
I/O
11
CC
A
12
13
A
0
A
1
V
A
CC
A
0
14
15
7
7
A
16
17
A
8
1
A
2
A
8
A
18
19
A
2
9
I/O
12
A
I/O
4
9
20
21
I/O
128K x 8
SRAM
I/O
13
I/O
14
12
I/O
I/O
I/O
I/O
I/O −I/O
I/O
5
I/O
6
I/O
7
4
5
6
7
22
23
0
7
I/O
13
4
4
4
4
24
25
I/O
15
I/O
14
26
27
GND
I/O
15
28
29
CS
1
WE
A
15
A
14
GND
30
31
WE
CS
2
CS
1
33
35
A
15
32
A
14
34
36
128K x 8
SRAM
CS
I/O −I/O
CS
2
CS
4
NC
33
8
15
1
CS
3
34
35
A
16
36
37
CS
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
4
OE
I/O
CS
A
GND
3
16
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
38
39
NC
OE
24
CS
2
I/O
16
17
18
19
40
41
I/O
25
I/O
26
I/O
I/O
I/O
GND
42
43
I/O
I/O
I/O
I/O
24
25
26
27
44
45
I/O
128K x 8
SRAM
16
I/O
27
I/O −I/O
16
23
46
47
I/O
17
A
3
A
A
48
49
10
11
I/O
A
4
18
50
51
A
I/O
19
5
A
12
A
13
52
53
A
CS
3
3
V
CC
A
10
54
55
A
4
A
5
A
6
A
I/O
20
I/O
21
I/O
22
I/O
23
56
57
11
I/O
28
128K x 8
SRAM
A
58
59
12
A
I/O −I/O
V
24
31
I/O
29
I/O
30
CC
60
61
13
A
6
62
63
I/O
20
I/O
31
I/O
I/O
I/O
I/O
GND
28
29
30
31
64
I/O
21
1836V33–1
CS
4
I/O
22
1836V33–2
I/O
23
GND
NC
NC
A
18
NC
1836V33–3
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
April 29, 1998