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CYM1836V33PM-15C

型号:

CYM1836V33PM-15C

品牌:

CYPRESS[ CYPRESS ]

页数:

7 页

PDF大小:

258 K

3
fax id: 2046  
PRELIMINARY  
CYM1836V33  
128K x 32 3.3V Static RAM Module  
lects (CS , CS , CS , CS ) are used to independently enable  
Features  
1
2
3
4
the four bytes. Reading or writing can be executed on individ-  
ual bytes or any combination of multiple bytes through proper  
use of selects.  
• High-density 3.3V 4-megabit SRAM module  
• 32-bit standard footprint supports densities from 16K  
x 32 through 1M x 32  
• High-speed CMOS SRAMs  
• Access time of 25 ns  
Writing to each byte is accomplished when the appropriate  
chip select (CS) and write enable (WE) inputs are both LOW.  
Data on the input/output pins (I/O) is written into the mem-  
ory location specified on the address pins (A through A ).  
0
16  
— Low active power 1.6W (max.) at 20 ns  
Reading the device is accomplished by taking the chip select  
(CS) LOW while write enable (WE) remains HIGH. Under  
these conditions, the contents of the memory location  
specified on the address pins will appear on the data in-  
put/output pins (I/O).  
• 2.0V Data Retention (I  
• SMD technology  
• TTL-compatible inputs and outputs  
• Available in 64-pin SIMM, 64-pin ZIP format or 72-pin  
SIMM format.  
= 0.8 mA, max.)  
CCDRL  
The data input/output pins stay at the high-impedance state  
when write enable is LOW or the appropriate chip selects are  
HIGH.  
Functional Description  
The CYM1836V33 is a 3.3V high-performance 4-megabit stat-  
ic RAM module organized as 128K words by 32 bits. This mod-  
ule is constructed from four 128K x 8 SRAMs in SOJ packages  
mounted on an epoxy laminate board with pins. Four chip se-  
Two pins (PD and PD ) are used to identify module mem-  
ory density in applications where alternate versions of the  
JEDEC-standard modules can be interchanged.  
0
1
Pin Configurations  
Logic Block Diagram  
72-pin SIMM  
Top View  
64-pin ZIP/SIMM  
NC  
PD  
1
3
5
Top View  
NC  
3
PD  
0
2
4
2
PD  
GND  
GND  
1
PD  
6
8
0
2
3
7
9
PD  
PD  
1
1
PD -  
OPEN  
I/O  
I/O  
I/O  
0
I/O  
0
1
2
3
4
5
0
I/O  
8
I/O  
9
I/O  
10  
PD OPEN  
I/O  
8
0
PD - OPEN  
I/O  
1
6
7
1
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
PD OPEN  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
I/O  
1
9
PD -  
A A  
8
9
I/O  
OPEN  
GND  
2
0
16  
OE  
WE  
2
I/O  
10  
17  
I/O  
V
10  
11  
PD -  
I/O  
3
I/O  
11  
3
I/O  
11  
CC  
A
12  
13  
A
0
A
1
V
A
CC  
A
0
14  
15  
7
7
A
16  
17  
A
8
1
A
2
A
8
A
18  
19  
A
2
9
I/O  
12  
A
I/O  
4
9
20  
21  
I/O  
128K x 8  
SRAM  
I/O  
13  
I/O  
14  
12  
I/O  
I/O  
I/O  
I/O  
I/O I/O  
I/O  
5
I/O  
6
I/O  
7
4
5
6
7
22  
23  
0
7
I/O  
13  
4
4
4
4
24  
25  
I/O  
15  
I/O  
14  
26  
27  
GND  
I/O  
15  
28  
29  
CS  
1
WE  
A
15  
A
14  
GND  
30  
31  
WE  
CS  
2
CS  
1
33  
35  
A
15  
32  
A
14  
34  
36  
128K x 8  
SRAM  
CS  
I/O I/O  
CS  
2
CS  
4
NC  
33  
8
15  
1
CS  
3
34  
35  
A
16  
36  
37  
CS  
37  
39  
41  
43  
45  
47  
49  
51  
53  
55  
57  
59  
61  
63  
65  
67  
69  
71  
4
OE  
I/O  
CS  
A
GND  
3
16  
38  
40  
42  
44  
46  
48  
50  
52  
54  
56  
58  
60  
62  
64  
66  
68  
70  
72  
38  
39  
NC  
OE  
24  
CS  
2
I/O  
16  
17  
18  
19  
40  
41  
I/O  
25  
I/O  
26  
I/O  
I/O  
I/O  
GND  
42  
43  
I/O  
I/O  
I/O  
I/O  
24  
25  
26  
27  
44  
45  
I/O  
128K x 8  
SRAM  
16  
I/O  
27  
I/O I/O  
16  
23  
46  
47  
I/O  
17  
A
3
A
A
48  
49  
10  
11  
I/O  
A
4
18  
50  
51  
A
I/O  
19  
5
A
12  
A
13  
52  
53  
A
CS  
3
3
V
CC  
A
10  
54  
55  
A
4
A
5
A
6
A
I/O  
20  
I/O  
21  
I/O  
22  
I/O  
23  
56  
57  
11  
I/O  
28  
128K x 8  
SRAM  
A
58  
59  
12  
A
I/O I/O  
V
24  
31  
I/O  
29  
I/O  
30  
CC  
60  
61  
13  
A
6
62  
63  
I/O  
20  
I/O  
31  
I/O  
I/O  
I/O  
I/O  
GND  
28  
29  
30  
31  
64  
I/O  
21  
1836V33–1  
CS  
4
I/O  
22  
1836V33–2  
I/O  
23  
GND  
NC  
NC  
A
18  
NC  
1836V33–3  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
April 29, 1998  
PRELIMINARY  
CYM1836V33  
Selection Guide  
1836V33–15 1836V33–20 1836V33–25 1836V33–30 1836V33–35 1836V33–45  
Maximum Access Time (ns)  
15  
520  
20  
20  
480  
20  
25  
440  
20  
30  
440  
20  
35  
440  
20  
45  
440  
20  
Maximum Operating Current (mA)  
Maximum Standby Current (mA)  
Shaded area contains advance information.  
Maximum Ratings  
Operating Range  
Ambient  
Temperature  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Range  
V
CC  
Commercial  
0°C to +70°C  
3.3V ± 300mV  
Storage Temperature ................................. –55°C to +125°C  
Ambient Temperature with  
Power Applied............................................... –10°C to +85°C  
Supply Voltage to Ground Potential ............... –0.5V to +7.0V  
DC Voltage Applied to Outputs  
in High Z State .....................................–0.5V to +V + 0.5V  
CC  
DC Input Voltage..................................–0.5V to +V + 0.5V  
CC  
Electrical Characteristics Over the Operating Range  
1836V33–20, 25,  
30, 35, 45  
1836V33–15  
Parameter  
Description  
Output HIGH Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
Input Load Current  
Output Leakage Current  
Test Conditions  
= Min., I = 4.0 mA  
Min.  
Max.  
Min.  
2.4  
Max.  
Unit  
V
V
V
V
V
V
V
2.4  
OH  
OL  
IH  
CC  
CC  
OH  
= Min., I = 8.0 mA  
0.4  
0.4  
V
OL  
2.2  
–0.3  
–4  
V
+0.3 2.2  
V
+0.3  
CC  
V
CC  
0.8  
+4  
–0.3  
–4  
0.8  
V
IL  
I
I
I
GND < V < V  
CC  
+4  
+5  
µA  
µA  
IX  
I
GND < V < V , Output Disabled –5  
+5  
–5  
OZ  
CC  
O
CC  
V
Operating Supply Current  
V
= Max., I  
= 0 mA, CS < V  
IL  
520  
480 (20ns) mA  
440  
CC  
CC  
OUT  
I
I
Automatic CS Power-Down  
Current  
V
= Max., CS > V ,  
100  
20  
80  
mA  
SB1  
SB2  
CC  
IH  
[1]  
Min. Duty Cycle = 100%  
Automatic CS Power-Down  
V
V
= Max., CS > V – 0.2V,  
CC CC  
20  
mA  
[1]  
Current  
> V – 0.2V or V < 0.2V  
IN  
CC IN  
Shaded area contains advance information.  
Capacitance[2]  
Parameter  
Description  
Test Conditions  
T = 25°C, f = 1 MHz,  
Max.  
Unit  
pF  
[3]  
C
C
Input Capacitance  
Output Capacitance  
24  
8
IN  
A
V
= 5.0V  
CC  
pF  
OUT  
Notes:  
1. A pull-up resistor to VCC on the CS input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given.  
2. Tested on a sample basis.  
3. 20 pF on CS, 40 pF all others.  
2
PRELIMINARY  
CYM1836V33  
AC Test Loads and Waveforms  
R1 481  
R1 481  
ALL INPUT PULSES  
90%  
10%  
5V  
5V  
3.0V  
GND  
90%  
10%  
OUTPUT  
OUTPUT  
R2  
255  
R2  
255  
30 pF  
5 pF  
< 5 ns  
< 5 ns  
INCLUDING  
JIG AND  
SCOPE  
INCLUDING  
JIG AND  
SCOPE  
1836V33–4  
1836V33–5  
(a)  
(b)  
Equivalent to:  
THÉVENIN EQUIVALENT  
167Ω  
1.73V  
OUTPUT  
[4]  
Switching Characteristics Over the Operating Range  
1836V33–15 1836V33–20 1836V33–25 1836V33–30 1836V33–35 1836V33–45  
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit  
Parameter  
Description  
READ CYCLE  
t
t
t
Read Cycle  
Time  
15  
20  
25  
30  
35  
45  
ns  
ns  
ns  
RC  
Address to Data  
Valid  
15  
20  
25  
30  
35  
45  
AA  
Output Hold  
from Address  
Change  
3
3
3
3
3
3
OHA  
t
t
t
t
t
t
CS LOW to Data  
Valid  
15  
7
20  
8
25  
8
30  
10  
35  
12  
45  
15  
ns  
ns  
ns  
ns  
ns  
ns  
ACS  
OE LOW to Data  
Valid  
DOE  
OE LOW to  
Low Z  
0
3
0
3
0
3
0
3
0
3
0
3
LZOE  
HZOE  
LZCS  
HZCS  
OE HIGH to  
High Z  
7
7
8
10  
10  
11  
13  
12  
15  
15  
18  
CS LOW to  
[5]  
Low Z  
CS HIGH toHigh  
10  
[5, 6]  
Z
Shaded area contains advance information.  
Notes:  
4. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified  
IOL/IOH and 30-pF load capacitance.  
5. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device. These parameters are guaranteed by design and not 100% tested.  
6. tHZCS and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage.  
3
PRELIMINARY  
CYM1836V33  
[4]  
Switching Characteristics Over the Operating Range (continued)  
1836V33–15 1836V33–20 1836V33–25 1836V33–30 1836V33–35 1836V33–45  
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit  
Parameter  
Description  
[7]  
WRITE CYCLE  
t
t
t
t
t
Write Cycle  
Time  
15  
12  
12  
0
20  
15  
15  
0
25  
15  
15  
0
30  
18  
18  
0
35  
20  
20  
0
45  
25  
25  
0
ns  
ns  
ns  
ns  
ns  
WC  
SCS  
AW  
HA  
CSLOWtoWrite  
End  
Address Set-Up  
to Write End  
Address Hold  
from Write End  
Address Set-Up  
to Write Start  
0
0
0
0
0
0
SA  
t
t
WE Pulse Width  
12  
7
15  
10  
15  
10  
18  
13  
20  
15  
25  
20  
ns  
ns  
PWE  
SD  
Data Set-Up to  
Write End  
t
t
t
Data Hold from  
Write End  
0
3
0
0
3
0
0
3
0
0
3
0
0
3
0
0
3
0
ns  
ns  
ns  
HD  
WEHIGHtoLow  
Z
LZWE  
HZWE  
WELOWtoHigh  
7
8
10  
15  
15  
18  
[6]  
Z
Shaded area contains advance information.  
Switching Waveforms  
[8, 9]  
Read Cycle No.1  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
1836V33–6  
[8, 10]  
Read Cycle No. 2  
t
CS  
RC  
t
ACS  
OE  
t
HZOE  
t
DOE  
t
HZCS  
t
LZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA VALID  
DATA OUT  
t
LZCS  
1836V33–7  
Notes:  
7. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can  
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.  
8. WE is HIGH for read cycle.  
9. Device is continuously selected, CS = VIL and OE= VIL  
.
10. Address valid prior to or coincident with CS transition LOW.  
4
PRELIMINARY  
CYM1836V33  
Switching Waveforms (continued)  
[7]  
Write Cycle No.1 (WE Controlled)  
t
WC  
ADDRESS  
CS  
t
SCS  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
t
HD  
SD  
DATA IN  
DATA VALID  
t
t
LZWE  
HZWE  
HIGH IMPEDANCE  
DATA OUT  
DATA UNDEFINED  
1836V33–8  
[7, 11]  
Write Cycle No. 2 (CS Controlled)  
t
WC  
ADDRESS  
CS  
t
SA  
t
SCS  
t
t
HA  
AW  
t
PWE  
WE  
t
t
HD  
SD  
DATA IN  
DATA VALID  
t
HZWE  
HIGH IMPEDANCE  
DATA OUT  
DATA UNDEFINED  
1836V33–9  
Note:  
11. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.  
Truth Table  
CS  
H
L
WE OE Input/Outputs  
Mode  
Deselect/Power-Down  
Read  
N
X
H
L
X
L
High Z  
Data Out  
Data In  
High Z  
L
X
H
Write  
L
H
Deselect  
5
PRELIMINARY  
CYM1836V33  
Ordering Information[12]  
Speed  
Package  
Operating  
Range  
(ns)  
Ordering Code  
Name  
PM03  
PZ08  
PM03  
PZ08  
PM03  
PZ08  
PM04  
PM03  
PZ08  
PM04  
PM03  
PZ08  
PM04  
PM03  
PZ08  
PM04  
Package Type  
64-Pin SIMM Module  
15  
CYM1836V33PM–15C  
CYM1836V33PZ–15C  
CYM1836V33PM–20C  
CYM1836V33PZ–20C  
CYM1836V33PM–25C  
CYM1836V33PZ–25C  
CYM1836V33P8–25C  
CYM1836V33PM–30C  
CYM1836V33PZ–30C  
CYM1836V33P8–25C  
CYM1836V33PM–35C  
CYM1836V33PZ–35C  
CYM1836V33P8–25C  
CYM1836V33PM–45C  
CYM1836V33PZ–45C  
CYM1836V33P8–25C  
Commercial  
Commercial  
Commercial  
72-Pin SIMM Module (Gold Contacts)  
64-Pin SIMM Module  
20  
25  
72-Pin SIMM Module (Gold Contacts)  
64-Pin SIMM Module  
72-Pin SIMM Module (Gold Contacts)  
72-Pin ZIP Module (Gold Contacts)  
64-Pin SIMM Module  
30  
35  
45  
Commercial  
Commercial  
Commercial  
72-Pin SIMM Module (Gold Contacts)  
72-Pin ZIP Module (Gold Contacts)  
64-Pin SIMM Module  
72-Pin SIMM Module (Gold Contacts)  
72-Pin ZIP Module (Gold Contacts)  
64-Pin SIMM Module  
72-Pin SIMM Module (Gold Contacts)  
72-Pin ZIP Module (Gold Contacts)  
Shaded area contains advance information.  
Note:  
12. 64-pin SIMM suitable for use in angled SIMM applications.  
Document #: 38-M-00085  
Package Diagrams  
64-Pin SIMM Module PM03  
3.855 MAX.  
3.580/3.588  
. 200 MAX.  
124/.126 DIA.  
2 PLCS  
128KX8  
128KX8  
128KX8  
128KX8  
.595 MAX.  
.135 REF.  
.397/.403  
.245/.255  
.061/.063 R  
.249/.251  
PIN1  
.075/.085  
6
PRELIMINARY  
CYM1836V33  
Package Diagrams (continued)  
64-Pin ZIP Module PZ08  
72-Pin Plastic SIMM Module PM04  
© Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
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