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JZY7010L

型号：

JZY7010L

品牌：

MURATA[ muRata ]

页数：

33 页

PDF大小：

920 K

下载PDF手册
JZY7010L 10A DC-DC Intelligent POL  
o 13.2V Input • 0.5V to 5.5V Output  
OBSOLETE PRODUCT  
Contact Factory for Replacement Modeltures  
Wide input voltage range: 3V – 13.2V  
•
•
High continuous output current: 10A  
Active digital current share  
Single-wire serial communication bus for frequency  
synchronization, programming, and monitoring  
•
•
•
Wide programmable output voltage range: 0.5V to  
5.5V  
Optimal voltage positioning with programmable slope  
of the VI line  
Overcurrent, overvoltage, undervoltage, and  
overtemperature protections with programmable  
thresholds and types  
Applications  
•
•
•
Programmable fixed switching frequency 0.5-1.0MHz  
Programmable turn-on and turn-off delays  
•
Low voltage, high density systems with  
Intermediate Bus Architectures (IBA)  
Programmable turn-on and turn-off voltage slew rates  
with tracking protection  
•
Point-of-load regulators for high performance DSP,  
FPGA, ASIC, and microprocessor applications  
•
•
•
•
•
•
Programmable feedback loop compensation  
Power Good signal with programmable limits  
Programmable fault management  
•
•
Desktops, servers, and portable computing  
Broadband, networking, optical, and  
communications systems  
Start up into the load pre-biased up to 100%  
Full rated current sink  
•
Active memory bus terminators  
Real time voltage, current, and temperature  
measurements, monitoring, and reporting  
Benefits  
•
•
•
Integrates digital power conversion with intelligent  
power management  
•
•
•
Small footprint SMT package: 16x32mm  
Low profile of 7mm  
Eliminates the need for external power  
management components  
Compatible with conventional pick-and-place  
equipment  
Completely programmable via industry standard  
serial communication bus  
•
•
Wide operating temperature range  
UL60950 recognized, CSA C22.2 No. 60950-00  
certified, and TUV EN60950-1:2001 certified  
•
•
One part that covers all applications  
Reduces board space, system cost and  
complexity, and time to market  
Description  
The JZY7010L is an intelligent, fully programmable step-down point-of-load DC-DC module integrating digital  
power conversion and intelligent power management. When used with JZM7100 Series Digital Power Managers,  
the JZY7010L completely eliminates the need for external components for sequencing, tracking, protection,  
monitoring, and reporting. All parameters of the JZY7010L are programmable via the serial communication bus  
and can be changed by a user at any time during product development and service.  
Selection Chart  
Model  
Input Voltage  
Range (VDC)  
Output Voltage Range  
(VDC)  
Output Voltage Setpoint Accuracy  
(%VOUT or mV, whichever is greater)  
Output Current  
(ADC)  
JZY7010L  
3.0 – 13.2  
0.5 – 5.5  
1% or 20mV  
10  
www.cd4power.com  
Page 1 of 33  
JZY7010L 10A DC-DC Intelligent POL  
3V to 13.2V Input • 0.5V to 5.5V Output  
1. Reference Documents:  
•
•
•
JZM7100 Digital Power Manager. Data Sheet  
Digital Power Manager. Programming Manual  
ZIOSTM Graphical User Interface  
2. Ordering Information  
JZY7117L  
3. Absolute Maximum Ratings  
•
Stresses in excess of the absolute maximum ratings may cause performance degradation, adversely affect long-  
term reliability, and cause permanent damage to the converter.  
Parameter  
Operating Temperature  
Input Voltage  
Conditions/Description  
Controller case temperature  
250ms Transient  
Min  
Max  
105  
15  
Units  
°C  
-40  
VDC  
ADC  
Output Current  
(See Output Current Derating Curves)  
-10  
10  
4. Environmental and Mechanical Specifications  
Parameter  
Ambient Temperature Range  
Storage Temperature (Ts)  
Weight  
Conditions/Description  
Min  
Nom  
Max  
85  
Units  
-40  
-55  
°C  
°C  
125  
15  
grams  
MHrs  
MTBF  
Calculated Per Telcordia Technologies SR-332  
3.11  
1) DC-DC Front End suffix: HBC for HBC25ZH-NT; QBC for QBC11ZH-NT; HDS for HDS48T30120-NCAR; QHS for QHS25ZG-NT  
www.cd4power.com  
Page 2 of 33  
JZY7010L 10A DC-DC Intelligent POL  
3V to 13.2V Input • 0.5V to 5.5V Output  
5. Electrical Specifications  
Specifications apply at the input voltage from 3V to 13.2V, output load from 0 to 10A, ambient temperature from -40°C to 85°C,  
100μF output capacitance, and default performance parameters settings unless otherwise noted.  
5.1 Input Specifications  
Parameter  
Conditions/Description  
Min  
Nom  
Max  
Units  
VDC  
At VIN<4.75V, VLDO pin needs to be  
connected to an external voltage source  
higher than 4.75V  
Input voltage (VIN)  
3
13.2  
Input Current (at no load)  
50  
mADC  
VIN≥4.75V, VLDO pin connected to VIN  
Undervoltage Lockout (VLDO  
connected to VIN)  
Ramping Up  
Ramping Down  
4.2  
3.75  
VDC  
VDC  
Undervoltage Lockout (VLDO  
connected to VAUX=5V)  
Ramping Up  
Ramping Down  
3.0  
2.5  
VDC  
VDC  
External Low Voltage Supply  
VLDO Input Current  
Connect to VLDO pin when VIN<4.75V  
4.75  
13.2  
VDC  
Current drawn from the external low  
voltage supply at VLDO=5V  
50  
mADC  
5.2 Output Specifications  
Parameter  
Conditions/Description  
Min  
Nom  
Max  
Units  
Programmable1  
0.5  
5.5  
VDC  
VDC  
Output Voltage Range (VOUT  
)
Default (no programming)  
0.5  
IOUT=0.5*IOUT MAX, FSW=500kHz,  
room temperature  
Output Voltage Setpoint Accuracy  
(See Selection Chart)  
Output Current (IOUT  
Line Regulation  
)
VIN MIN to VIN MAX  
VIN MIN to VIN MAX  
0 to IOUT MAX  
-102  
10  
ADC  
±0.4  
±0.3  
%VOUT  
%VOUT  
Load Regulation  
Dynamic Regulation  
Peak Deviation  
Settling Time  
Slew rate 2.5A/μs, 50 -100% load step  
COUT=220μF, FSW=1MHz  
mV  
μs  
mV  
mV  
mV  
mV  
mV  
50  
200  
10  
15  
15  
to 10% of peak deviation  
VIN=5.0V, VOUT=0.5V, FSW=500kHz  
VIN=5.0V, VOUT=2.5V, FSW=500kHz  
VIN=12V, VOUT=0.5V, FSW=500kHz  
VIN=12V, VOUT=2.5V, FSW=500kHz  
VIN=12V, VOUT=5.0V, FSW=500kHz  
Output Voltage Peak-to-Peak  
Ripple and Noise  
BW=20MHz  
25  
45  
Full Load  
Temperature Coefficient  
Switching Frequency  
VIN=12V, IOUT=0.5*IOUT MAX  
20  
ppm/°C  
Default  
500  
kHz  
kHz  
%
Programmable, 250kHz steps  
Default  
Programmable, 1.56% steps  
500  
0
1,000  
95  
90.5  
Duty Cycle Limit  
%
1
JZY7010L is a step-down converter, thus the output voltage is always lower than the input voltage as show in  
Figure 1.  
2 At the negative output current (bus terminator mode) efficiency of the JZY7010L degrades resulting in increased  
internal power dissipation. Therefore maximum allowable negative current under specific conditions is 20% lower  
than the current determined from the derating curves shown in paragraph 6.5.  
www.cd4power.com  
Page 3 of 33  
JZY7010L 10A DC-DC Intelligent POL  
3V to 13.2V Input • 0.5V to 5.5V Output  
VOUT  
[V]  
5.5  
5.0  
4.5  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
Min Load 0.2A  
VIN [V]  
2.0  
4.0  
3.0 3.15  
6.0  
8.0  
10.0  
12.0  
14.0  
5.5  
13.2  
6.25  
Figure 1. Output Voltage as a Function of Input Voltage and Output Current  
5.3 Protection Specifications  
Parameter  
Conditions/Description  
Output Overcurrent Protection  
Min  
Nom  
Max  
Units  
Default  
Programmable  
Non-Latching, 130ms period  
Latching/Non-Latching  
Type  
Default  
Programmable in 11 steps  
135  
135  
%IOUT  
%IOUT  
Threshold  
45  
Threshold Accuracy  
-20  
20  
%IOCP.SET  
Output Overvoltage Protection  
Default  
Programmable  
Non-Latching, 130ms period  
Latching/Non-Latching  
Type  
Default  
Programmable in 10% steps  
130  
%VO.SET  
%VO.SET  
Threshold  
1101  
-2  
130  
2
Threshold Accuracy  
%VOVP.SET  
From instant when threshold is exceeded until  
the turn-off command is generated  
Delay  
6
μs  
www.cd4power.com  
Page 4 of 33  
JZY7010L 10A DC-DC Intelligent POL  
3V to 13.2V Input • 0.5V to 5.5V Output  
Output Undervoltage Protection  
Default  
Programmable  
Non-Latching, 130ms period  
Latching/Non-Latching  
Type  
Default  
Programmable in 5% steps  
75  
%VO.SET  
%VO.SET  
Threshold  
Threshold Accuracy  
Delay  
75  
-2  
85  
2
%VUVP.SET  
From instant when threshold is exceeded until  
the turn-off command is generated  
6
μs  
Overtemperature Protection  
Default  
Programmable  
Non-Latching, 130ms period  
Latching/Non-Latching  
Type  
Turn Off Threshold  
Turn On Threshold  
Threshold Accuracy  
Delay  
Temperature is increasing  
130  
120  
5
°C  
°C  
°C  
μs  
Temperature is decreasing after module was  
shut down by OTP  
-5  
From instant when threshold is exceeded until  
the turn-off command is generated  
6
Tracking Protection (when Enabled)  
Default  
Programmable  
Disabled  
Type  
Latching/Non-Latching, 130ms period  
Threshold  
Enabled during output voltage ramping up  
mVDC  
±250  
Threshold Accuracy  
-50  
50  
mVDC  
From instant when threshold is exceeded until  
the turn-off command is generated  
Delay  
6
μs  
Overtemperature Warning  
Threshold  
Threshold Accuracy  
Hysteresis  
Always enabled, reported in Status register  
120  
°C  
°C  
°C  
-5  
5
3
6
From instant when threshold is exceeded until  
the warning signal is generated  
Delay  
μs  
Power Good Signal  
VOUT is inside the PG window  
VOUT is outside the PG window  
High  
Low  
Logic  
N/A  
Default  
Programmable in 5% steps  
90  
%VO.SET  
%VO.SET  
Lower Threshold  
Upper Threshold  
Delay  
90  
-2  
95  
2
110  
12  
%VO.SET  
μs  
From instant when threshold is exceeded until  
status of PG signal changes  
Threshold Accuracy  
%VO.SET  
___________________  
1 Minimum OVP threshold is 1.0V  
www.cd4power.com  
Page 5 of 33  
JZY7010L 10A DC-DC Intelligent POL  
3V to 13.2V Input • 0.5V to 5.5V Output  
5.4 Feature Specifications  
Parameter  
Conditions/Description  
Current Share  
Min  
Nom  
Max  
Units  
Type  
Active, Single Line  
Maximum Number of Modules  
Connected in Parallel  
IOUT MIN=0  
4
Current Share Accuracy  
IOUT MIN≥20%*IOUT NOM  
±20  
%IOUT  
Interleave  
Default  
0
degree  
degree  
Interleave (Phase Shift)  
0
348.75  
Programmable in 11.25° steps  
Sequencing  
Default  
Programmable in 1ms steps  
0
ms  
ms  
Turn ON Delay  
Turn OFF Delay  
0
0
255  
Default  
Programmable in 1ms steps  
0
ms  
ms  
63  
Tracking  
Default  
Programmable in 7 steps  
0.1  
V/ms  
V/ms  
Turn ON Slew Rate  
Turn OFF Slew Rate  
0.1  
8.331  
Default  
Programmable in 7 steps  
-0.1  
V/ms  
V/ms  
-0.1  
-8.331  
Optimal Voltage Positioning  
Default  
Programmable in 8 steps  
0
mV/A  
mV/A  
Load Regulation  
0
6.9  
Feedback Loop Compensation  
Zero1 (Effects phase lead and  
increases gain in mid-band)  
Default  
Programmable  
4.8  
kHz  
kHz  
0.05  
0.05  
0.05  
1
50  
Zero 2 (Effects phase lead and  
increases gain in mid-band)  
Default  
Programmable  
49.3  
50  
kHz  
kHz  
Pole 1 (Integrator Pole, effects  
loop gain)  
Default  
Programmable  
1.9  
kHz  
kHz  
50  
Pole 2 (Effects phase lag and  
limits gain in mid-band)  
Default  
Programmable  
177  
kHz  
kHz  
1000  
Pole 3 (High frequency low-  
pass filter to limit PWM noise)  
Default  
Programmable  
442  
kHz  
kHz  
1
1000  
Monitoring  
Output Voltage Monitoring  
Accuracy  
-2%VOUT  
– 1 LSB  
2%VOUT  
+ 1 LSB  
1 LSB=22mV  
mV  
%IOUT  
°C  
Output Current Monitoring  
Accuracy  
20%*IOUT NOM < IOUT < IOUT NOM  
-20  
-5  
+20  
+5  
Temperature Monitoring  
Accuracy  
Junction temperature of POL controller  
___________________  
1 Achieving fast slew rates under specific line and load conditions may require feedback loop adjustment  
www.cd4power.com  
Page 6 of 33  
JZY7010L 10A DC-DC Intelligent POL  
3V to 13.2V Input • 0.5V to 5.5V Output  
5.5 Signal Specifications  
Parameter  
Conditions/Description  
Min  
Nom  
Max  
Units  
VDD  
Internal supply voltage  
3.15  
3.3  
3.45  
V
SYNC/DATA Line  
ViL_sd  
ViH_sd  
LOW level input voltage  
HIGH level input voltage  
-0.5  
0.3 x VDD  
VDD + 0.5  
V
V
0.75 x  
VDD  
0.35 x  
VDD  
Vhyst_sd  
Hysteresis of input Schmitt trigger  
V
VoL  
Tr_sd  
LOW level sink current @ 0.5V  
Maximum allowed rise time 10/90%VDD  
Added node capacitance  
14  
mA  
ns  
300  
10  
Cnode_sd  
Ipu_sd  
5
pF  
Pull-up current source at Vsd=0V  
Clock frequency of external SD line  
0.5  
mA  
kHz  
Freq_sd  
475  
22  
525  
28  
% of clock  
cycle  
% of clock  
cycle  
Tsynq  
T0  
Sync pulse duration  
Data=0 pulse duration  
72  
78  
Inputs: ADDR0…ADDR4, Enable, IM, VID0…VID4  
ViL_x  
ViH_x  
LOW level input voltage  
HIGH level input voltage  
-0.5  
0.3 x VDD  
VDD+0.5  
V
V
V
0.7 x VDD  
Vhyst_x  
Hysteresis of input Schmitt trigger  
0.1 x VDD  
External pull down resistance  
ADDRX forced low  
RdnL_ADDR  
10  
kOhm  
Power Good and OK Inputs/Outputs  
Iup_PG  
Iup_OK  
ViL_x  
Pull-up current source input forced low PG  
Pull-up current source input forced low OK  
LOW level input voltage  
60  
μA  
μA  
V
400  
-0.5  
0.3 x VDD  
VDD+0.5  
ViH_x  
Vhyst_x  
IoL  
HIGH level input voltage  
0.7 x VDD  
V
Hysteresis of input Schmitt trigger  
LOW level sink current at 0.5V  
Current Share Bus  
0.1 x VDD  
V
10  
mA  
Iup_CS  
ViL_CS  
Pull-up current source at VCS = 0V  
LOW level input voltage  
1.5  
mA  
V
-0.5  
0.3 x VDD  
VDD+0.5  
0.75 x  
VDD  
ViH_CS  
HIGH level input voltage  
V
V
0.35 x  
VDD  
Vhyst_CS  
Hysteresis of input Schmitt trigger  
IoL  
LOW level sink current at 0.5V  
15  
mA  
ns  
Tr_CS  
Maximum allowed rise time 10/90% VDD  
100  
www.cd4power.com  
Page 7 of 33  
JZY7010L 10A DC-DC Intelligent POL  
3V to 13.2V Input • 0.5V to 5.5V Output  
6. Typical Performance Characteristics  
95  
90  
85  
80  
75  
70  
65  
60  
6.1 Efficiency Curves  
100  
95  
90  
85  
80  
75  
70  
Vout=1.2V  
Vout=3.3V  
Vout=2.5V  
Vout=5.0V  
55  
50  
0
1
2
3
4
5
6
7
8
9
10  
Vo=0.5V  
2
Vo=1.2V  
5
Vo=2.5V  
Output Current, A  
65  
0
1
3
4
6
7
8
9
10  
Output Current, A  
Figure 4. Efficiency vs. Load. Vin=12V, Fsw=500kHz  
Figure 2. Efficiency vs. Load. Vin=3.3V, Fsw=500kHz  
95  
90  
85  
80  
75  
70  
65  
60  
95  
90  
85  
80  
75  
70  
65  
60  
Vin=3.3V  
2.0  
Vin=5.0V  
Vin=12V  
4.5 5.0  
Vout=0.5V  
Vout=2.5V  
Vout=1.2V  
Vout=3.3V  
55  
50  
0.5  
1.0  
1.5  
2.5  
3.0  
3.5  
4.0  
5.5  
Output Voltage, V  
0
1
2
3
4
5
6
7
8
9
10  
Output Current, A  
Figure 5. Efficiency vs. Output Voltage, Iout=10A,  
Fsw=500kHz  
Figure 3. Efficiency vs. Load. Vin=5V, Fsw=500kHz  
www.cd4power.com  
Page 8 of 33  
JZY7010L 10A DC-DC Intelligent POL  
3V to 13.2V Input • 0.5V to 5.5V Output  
95  
90  
85  
80  
75  
70  
65  
60  
55  
85  
80  
75  
70  
Fs=500kHz  
3
Fs=750kHz  
Fs=1000kHz  
Vo=0.5V  
4
Vo=1.2V  
6
Vo=2.5V  
8
65  
3
5
7
9
10  
11  
12  
0
1
2
4
5
6
7
8
9
10  
Input Voltage, V  
Output Current, A  
Figure 6. Efficiency vs. Input Voltage. Iout=10A, Fsw=500kHz  
Figure 8. Efficiency vs. Load. Vin=5V, Vout=1.2V  
96  
95  
94  
93  
92  
91  
90  
92  
90  
88  
86  
84  
82  
80  
78  
76  
74  
72  
Fs=500kHz  
Fs=750kHz  
6
Fs=1000kHz  
Fs=500kHz  
2
Fs=750kHz  
Fs=1000kHz  
89  
0
1
3
4
5
6
7
8
9
10  
0
1
2
3
4
5
7
8
9
10  
Output Current, A  
Output Current, A  
Figure 7. Efficiency vs. Load. Vin=3.3V, Vout=2.5V  
Figure 9. Efficiency vs. Load. Vin=12V, Vout=5V  
www.cd4power.com  
Page 9 of 33  
JZY7010L 10A DC-DC Intelligent POL  
3V to 13.2V Input • 0.5V to 5.5V Output  
91  
90  
89  
88  
87  
86  
85  
84  
83  
82  
81  
80  
79  
78  
Vin(3.3V), Vo(2.5V)  
Vin(12V), Vo(5V)  
Vin(5V), Vo(1.2V)  
500  
750  
Switching Frequency, kHz  
1000  
Figure 12. Turn-On with Different Rising Slew Rates.  
Rising Slew Rates are Programmed as follows: V1-  
1V/ms, V2-0.5V/ms, V3-0.2V/ms.  
Vin=12V, Ch1 – V1, Ch2 – V2, Ch3 – V3  
Figure 10. Efficiency vs. Switching Frequency. Iout=10A  
6.2 Turn-On Characteristics  
Figure 13. Sequenced Turn-On. Rising Slew Rate is  
Programmed at 1V/ms. V2 Delay is 2ms, V3 delay  
is 4ms. Vin=12V, Ch1 – V1, Ch2 – V2, Ch3 – V3  
Figure 11. Tracking Turn-On. Rising Slew Rate is  
Programmed at 0.5V/ms.  
Vin=12V, Ch1 – V1, Ch2 – V2, Ch3 – V3  
www.cd4power.com  
Page 10 of 33  
JZY7010L 10A DC-DC Intelligent POL  
3V to 13.2V Input • 0.5V to 5.5V Output  
6.3 Turn-Off Characteristics  
Figure 14. Turn On with Sequencing and Tracking. Rising  
Slew Rate Programmed at 0.2V/ms, V1 and V3  
delays are programmed at 20ms.  
Vin=12V, Ch1 – V1, Ch2 – V2, Ch3 – V3  
Figure 16. Tracking Turn-Off. Falling Slew Rate is  
Programmed at 0.5V/ms.  
Vin=12V, Ch1 – V1, Ch2 – V2, Ch3 – V3  
Figure 15. Turn On into Prebiased Load. Same as Figure 14,  
with a Diode Between V2 and V3. V3 is Prebiased  
by V2 via the Diode.  
Figure 17. Turn-Off with Tracking and Sequencing. Falling  
Slew Rate is Programmed at 0.5V/ms.  
Vin=12V, Ch1 – V1, Ch2 – V2, Ch3 – V3  
Vin=12V, Ch1 – V1, Ch2 – V2, Ch3 – V3  
www.cd4power.com  
Page 11 of 33  
JZY7010L 10A DC-DC Intelligent POL  
3V to 13.2V Input • 0.5V to 5.5V Output  
6.4 Transient Response  
The pictures below show the deviation of the output  
voltage in response to the 50-100-50% step load at  
2.5A/μs. In all tests the POL converters were  
switching at 1MHz and had 10x22μF ceramic  
capacitors connected across the output pins.  
Bandwidth of the feedback loop was programmed for  
faster transient response.  
Figure 20. Vin=5V, Vout=2.5V, BW~60kHz.  
Figure 18. Vin=12V, Vout=5V, BW~60kHz.  
Figure 21. Vin=5V, Vout=1V, BW~60kHz.  
Figure 19. Vin=12V, Vout=1V, BW~60kHz.  
Figure 22. Vin=3.3V, Vout=1V, BW~60kHz.  
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Page 12 of 33  
JZY7010L 10A DC-DC Intelligent POL  
3V to 13.2V Input • 0.5V to 5.5V Output  
6.5 Thermal Derating Curves  
10  
9
8
7
6
5
0 LFM  
100 LFM  
55  
200 LFM  
65  
400 LFM  
75  
600 LFM  
4
45  
85  
Ambient Temperature, 'C  
Figure 23. Thermal Derating Curves. Vin=13.2V, Vout=5.0V, Fsw=500kHz  
10  
9
8
7
6
5
0 LFM  
100 LFM  
55  
200 LFM  
65  
400 LFM  
75  
600 LFM  
4
45  
85  
Ambient Temperature, 'C  
Figure 24. Thermal Derating Curves. Vin=13.2V, Vout=5.0V, Fsw=1MHz  
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Page 13 of 33  
JZY7010L 10A DC-DC Intelligent POL  
3V to 13.2V Input • 0.5V to 5.5V Output  
7. Typical Application  
Intermediate Voltage Bus  
SD  
I2C  
OK_C  
OK_B  
OK_A  
DPM  
CS  
ZY7010L  
ZY7010L  
ZY7010L  
ZY7010L  
ADDR  
ADDR  
ADDR  
ADDR  
V1  
V2  
V3  
Figure 25. Block Diagram of Typical Multiple Output Application with Digital Power Manager and I2C Interface  
The block diagram of a typical application of JZY7010L point-of-load converters (POL) is shown in Figure 25. The  
system includes multiple POLs and a JZM7100 Series Digital Power Manager (DPM). All POLs are connected to  
the DPM and to each other via a single-wire SD (sync/data) communication bus. The bus provides  
synchronization of all POLs to the master clock generated by the DPM and simultaneously performs bidirectional  
data transfer between POLs and the DPM. Each POL has a unique 5-bit address programmed by grounding  
respective address pins. To enable the current share, CS pins of POLs connected in parallel are linked together.  
There are three groups of POLs in the application, groups A, B, and group C. A group is defined as a number of  
POLs interconnected via OK pins. Grouping of POLs enables users to program, control, and monitor multiple  
POLs simultaneously and execute advanced fault management schemes.  
The complete schematic of the application is shown in Figure 26.  
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Page 14 of 33  
JZY7010L 10A DC-DC Intelligent POL  
3V to 13.2V Input • 0.5V to 5.5V Output  
Figure 26. Complete Schematic of Application Shown in Figure 25. Intermediate Bus Voltage is from 4.75V to 13.2V.  
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Page 15 of 33  
JZY7010L 10A DC-DC Intelligent POL  
3V to 13.2V Input • 0.5V to 5.5V Output  
8. Pin Assignments and Description  
Pin  
Name  
Pin  
No.  
Pin  
Type  
Buffer  
Type  
Pin Description  
Notes  
Connect to an external voltage source higher  
than 4.75V, if VIN<4.75V. Connect to VIN, if  
VIN≥4.75V  
VLDO  
1
P
Low Voltage Dropout  
IM  
2
3
Not Used  
Not Used  
Not Used  
Not Used  
Not Used  
Not Used  
Not Used  
Not Used  
Not Used  
Leave floating  
Leave floating  
Leave floating  
Leave floating  
Leave floating  
Leave floating  
Leave floating  
Leave floating  
Connect to PGND  
VID5  
VID4  
VID3  
VID2  
VID1  
VID0  
VREF  
EN  
4
5
6
7
8
9
10  
Connect to OK pin of other Z-POL and/or  
DPM. Leave floating, if not used  
OK  
11  
I/O  
PU  
Fault/Status Condition  
SD  
12  
13  
14  
I/O  
I/O  
PU  
PU  
Sync/Data Line  
Power Good  
Not Used  
Connect to SD pin of DPM  
PGOOD  
TRIM  
Leave floating  
Connect to CS pin of other Z-POLs connected  
in parallel  
CS  
15  
I/O  
PU  
Current Share  
ADDR4  
ADDR3  
ADDR2  
ADDR1  
ADDR0  
-VS  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
I
I
PU  
PU  
PU  
PU  
PU  
PU  
PU  
POL Address Bit 4  
POL Address Bit 3  
POL Address Bit 2  
POL Address Bit 1  
POL Address Bit 0  
Negative Voltage Sense  
Positive Voltage Sense  
Output Voltage  
Tie to PGND for 0 or leave floating for 1  
Tie to PGND for 0 or leave floating for 1  
Tie to PGND for 0 or leave floating for 1  
Tie to PGND for 0 or leave floating for 1  
Tie to PGND for 0 or leave floating for 1  
Connect to the negative point close to the load  
Connect to the positive point close to the load  
I
I
I
I
+VS  
I
VOUT  
PGND  
VIN  
P
P
P
Power Ground  
Input Voltage  
Legend: I=input, O=output, I/O=input/output, P=power, A=analog, PU=internal pull-up  
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Page 16 of 33  
JZY7010L 10A DC-DC Intelligent POL  
3V to 13.2V Input • 0.5V to 5.5V Output  
JZY7010L converters can be programmed using the  
ZIOSTM Graphical User Interface or directly via the  
I2C bus by using high and low level commands as  
described in the ‘”DPM Programming Manual”.  
9. Programmable Features  
Performance parameters of JZY7010L POL  
converters can be programmed via the industry  
standard I2C communication bus without replacing  
any components or rewiring PCB traces. Each  
parameter has a default value stored in the volatile  
memory registers detailed in Table 1. The setup  
registers 00h through 14h are programmed at the  
system power-up. When the user programs new  
performance parameters, the values in the registers  
are overwritten. Upon removal of the input voltage,  
the default values are restored.  
JZY7010L parameters can be reprogrammed at any  
time during the system operation and service except  
for the digital filter coefficients, the switching  
frequency and the duty cycle limit, that can only be  
changed when the POL is turned off.  
9.1 Output Voltage  
The output voltage can be programmed in the GUI  
Output Configuration window shown in the Figure 27  
or directly via the I2C bus by writing into the VOS  
register shown in Figure 28.  
Table 1. JZY7010L Memory Registers  
Register  
Content  
Address  
PC1  
PC2  
PC3  
DON  
DOF  
TC  
Protection Configuration 1  
Protection Configuration 2  
Protection Configuration 3  
Turn-On Delay  
00h  
01h  
02h  
05h  
06h  
03h  
04h  
Turn-Off Delay  
Tracking Configuration  
Interleave Configuration and  
Frequency Selection  
INT  
RUN  
ST  
VOS  
CLS  
DCL  
B1  
RUN Register  
Status Register  
15h  
16h  
07h  
08h  
09h  
0Ah  
Output Voltage Setpoint  
Current Limit Setpoint  
Duty Cycle Limit  
Dig Controller Denominator z-1  
Coefficient  
B2  
Dig Controller Denominator z-2  
Coefficient  
0Bh  
0Ch  
0Dh  
0Eh  
0Fh  
10h  
11h  
12h  
13h  
14h  
B3  
Dig Controller Denominator z-3  
Coefficient  
C0L  
C0H  
C1L  
C1H  
C2L  
C2H  
C3L  
C3H  
Dig Controller Numerator z0  
Coefficient, Low Byte  
Dig Controller Numerator z0  
Coefficient, High Byte  
Dig Controller Numerator z-1  
Coefficient, Low Byte  
Dig Controller Numerator z-1  
Coefficient, High Byte  
Dig Controller Numerator z-2  
Coefficient, Low Byte  
Dig Controller Numerator z-2  
Coefficient, High Byte  
Dig Controller Numerator z-3  
Coefficient, High Byte  
Dig Controller Numerator z-3  
Coefficient, Low Byte  
Output Voltage Monitoring  
Output Current Monitoring  
Temperature Monitoring  
Figure 27. Output Configuration Window  
R/W-0  
VOS7  
Bit 7  
R/W-0  
VOS6  
R/W-0  
VOS5  
R/W-0  
VOS4  
R/W-0  
VOS3  
R/W-0  
VOS2  
R/W-0  
VOS1  
R/W-0  
VOS0  
Bit 0  
Bit 7:0 VOS[7:0], Output voltage setting  
00h: corresponds to 0.5000V  
01h: corresponds to 0.5125V  
…
R
W
U
= Readable bit  
= Writable bit  
= Unimplemented bit,  
read as ‘0’  
77h: corresponds to 1.9875V  
78h: corresponds to 2.0000V  
79h: corresponds to 2.025V  
…
- n = Value at POR reset  
F9h: corresponds to 5.225V  
FAh: corresponds to 5.250V  
FBh: corresponds to 5.300V  
…
VOM  
IOM  
TMP  
17h  
18h  
19h  
FFh: corresponds to 5.500V  
Figure 28. Output Voltage Setpoint Register VOS  
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JZY7010L 10A DC-DC Intelligent POL  
3V to 13.2V Input • 0.5V to 5.5V Output  
9.1.1  
Output Voltage Setpoint  
VOUT  
The output voltage programming range is from 0.5V  
to 5.5V. Within this range, there are 256 predefined  
voltage setpoints. To improve resolution of the  
output voltage settings, the voltage range is divided  
into three sub-ranges as shown in Table 2.  
Upper Regulation  
Limit  
Operating  
Point  
VI Curve Without  
Load Regulation  
VI Curve With  
Load Regulation  
Headroom without  
Load Regulation  
Headroom with  
Lower Regulation  
Limit  
Table 2. Output Voltage Adjustment Resolution  
VOUT MIN, V  
0.500  
VOUT MAX, V  
2.000  
5.25  
Resolution, mV  
Load Regulation  
Heavy  
Load  
Light  
Load  
IOUT  
12.5  
25  
2.025  
Figure 29. Optimal Voltage Positioning Concept  
5.3  
5.5  
50  
Increased headroom allows tolerating larger voltage  
deviations. For example, the step load change from  
light to heavy load will cause the output voltage to  
drop. If the optimal voltage positioning is utilized, the  
output voltage will stay within the regulation window.  
Otherwise, the output voltage will drop below the  
lower regulation limit. To compensate for the voltage  
drop external output capacitance will need to be  
added, thus increasing cost and complexity of the  
system.  
9.1.2  
Output Voltage Margining  
If the output voltage needs to be varied by a certain  
percentage, the margining function can be utilized.  
The margining can be programmed in the GUI  
Output Configuration window or directly via the I2C  
bus using high level commands as described in the  
‘”DPM Programming Manual”.  
In order to properly margin POLs that are connected  
in parallel, the POLs must be members of one of the  
Parallel Buses.  
The effect of optimal voltage positioning is shown in  
Figure 30 and Figure 31. In this case, switching  
output load causes large peak-to-peak deviation of  
the output voltage. By programming load regulation,  
the peak to peak deviation is dramatically reduced.  
Refer to the GUI System  
Configuration Window shown in Figure 55.  
9.1.3  
Optimal Voltage Positioning  
Optimal voltage positioning increases the voltage  
regulation window by properly positioning the output  
voltage setpoint. Positioning is determined by the  
load regulation that can be programmed in the GUI  
Output Configuration window shown in Error!  
Reference source not found. or directly via the I2C  
bus by writing into the CLS register shown in Figure  
38.  
Figure 29 illustrates optimal voltage positioning  
concept. If no load regulation is programmed, the  
headroom (voltage differential between the output  
voltage setpoint and  
a
regulation limit) is  
approximately half of the voltage regulation window.  
When load regulation is programmed, the output  
voltage will decrease as the output current  
increases, so the VI characteristic will have a  
negative slope. Therefore, by properly selecting the  
operating point, it is possible to increase the  
headroom as shown in the picture.  
Figure 30. Transient Response Without Optimal Voltage  
Positioning  
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Page 18 of 33  
JZY7010L 10A DC-DC Intelligent POL  
3V to 13.2V Input • 0.5V to 5.5V Output  
R/W-0  
DON7  
Bit 7  
R/W-0  
DON6  
R/W-0  
DON5  
R/W-0  
DON4  
R/W-0  
DON3  
R/W-0  
DON2  
R/W-0  
DON1  
R/W-0  
DON0  
Bit 0  
Bit 7:0 DON[7:0]: Turn-on delay time  
00h: corresponds to 0ms delay after turn-on command has occurred  
…
FFh: corresponds to 255ms delay after turn-on command has occurred  
Figure 33. Turn-On Delay Register DON  
9.2.2  
Turn-Off Delay  
U
U
R/W-0  
DOF5  
R/W-0  
DOF4  
R/W-0  
DOF3  
R/W-0  
DOF2  
R/W-0  
DOF1  
R/W-0  
DOF0  
Bit 0  
---  
---  
Bit 7  
Bit 7:6 Unimplemented, read as ‘0’  
Bit 5:0 DOF[5:0]: Turn-off delay time  
Figure 31. Transient Response With Optimal Voltage  
Positioning  
00h: corresponds to 0ms delay after turn-off command has occurred  
…
3Fh: corresponds to 63ms delay after turn-off command has occurred  
Figure 34. Turn-Off Delay Register DOF  
9.2 Sequencing and Tracking  
Turn-on delay, turn-off delay, and rising and falling  
output voltage slew rates can be programmed in the  
GUI Sequencing/Tracking window shown in Figure  
32 or directly via the I2C bus by writing into the DON,  
DOF, and TC registers, respectively. The registers  
are shown in Figure 33, Figure 34, and Figure 36.  
Turn-off delay is defined as an interval from the  
application of the Turn-Off command until the output  
voltage reaches zero (if the falling slew rate is  
programmed) or until both high side and low side  
switches are turned off (if the slew rate is not  
programmed). Therefore, for the slew rate controlled  
turn-off the ramp-down time is included in the turn-off  
delay as shown in Figure 35.  
User programmed turn-off delay, TDF  
Turn-Off  
Command  
Calculated  
Ramp-down time, TF  
delay TD  
Internal  
ramp-down  
command  
Falling slew  
rate dVF/dT  
VOUT  
Figure 32. Sequencing/Tracking Window  
Time  
Figure 35. Relationship between Turn-Off Delay and Falling  
Slew Rate  
9.2.1  
Turn-On Delay  
Turn-on delay is defined as an interval from the  
application of the Turn-On command until the output  
voltage starts ramping up.  
As it can be seen from the figure, the internally  
calculated delay TD is determined by the equation  
below.  
VOUT  
TD = TDF  
−
,
dVF  
dT  
For proper operation TD shall be greater than zero.  
The appropriate value of the turn-off delay needs to  
be programmed to satisfy the condition.  
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JZY7010L 10A DC-DC Intelligent POL  
3V to 13.2V Input • 0.5V to 5.5V Output  
If the falling slew rate control is not utilized, the turn-  
off delay only determines an interval from the  
application of the Turn-Off command until both high  
side and low side switches are turned off. In this  
case, the output voltage ramp-down process is  
determined by load parameters.  
U
---  
R/W-0  
R2  
R/W-0  
R1  
R/W-0  
R0  
R/W-1  
SC  
R/W-0  
F2  
R/W-0  
F1  
R/W-0  
F0  
Bit 7  
Bit 0  
Bit 7  
Unimplemented , read as ‘0’  
R
W
U
= Readable bit  
= Writable bit  
= Unimplemented bit,  
read as ‘0’  
Bit 6:4 R[2:0]: Value of Vo rising slope  
0: corresponds to 0.1V/ms)  
1: corresponds to 0.2V/ms  
2: corresponds to 0.5V/ms  
3: corresponds to 1.0V/ms  
4: corresponds to 2.0V/ms  
5: corresponds to 5.0V/ms  
6: corresponds to 8.33V/ms  
7: corresponds to 8.33V/ms  
- n = Value at POR reset  
9.2.3  
Rising and Falling Slew Rates  
The output voltage tracking is accomplished by  
programming the rising and falling slew rates of the  
output voltage. To achieve programmed slew rates,  
the output voltage is being changed in 12.5mV steps  
where duration of each step determines the slew  
rate. For example, ramping up a 1.0V output with a  
slew rate of 0.5V/ms will require 80 steps duration of  
25μs each.  
Bit 3  
SC, Slew rate control at turn-off  
0: Slew rate control turned off  
1: Slew rate control turned on  
Bit 2:0 F[2:0]: Value of Vo falling slope  
0: corresponds to -0.1V/ms  
1: corresponds to -0.2V/ms  
2: corresponds to -0.5V/ms  
3: corresponds to -1.0V/ms  
4: corresponds to -2.0V/ms  
5: corresponds to -5.0V/ms  
6: corresponds to –8.33V/ms  
7: corresponds to –8.33V/ms  
Duration of each voltage step is calculated by  
dividing the master clock frequency generated by the  
DPM.  
Since all POLs in the system are  
synchronized to the master clock, the matching of  
voltage slew rates of different outputs is very  
accurate as it can be seen in Figure 11 and Figure  
16.  
Figure 36. Tracking Configuration Register TC  
9.3 Protections  
JZY7010L Series converters have a comprehensive  
set of programmable protections. The set includes  
the output over- and undervoltage protections,  
overcurrent protection, overtemperature protection,  
tracking protection, overtemperature warning, and  
Power Good signal. Status of protections is stored in  
the ST register shown in Figure 37.  
During the turn on process, a POL not only delivers  
current required by the load (ILOAD), but also charges  
the load capacitance. The charging current can be  
determined from the equation below:  
dVR  
ICHG = CLOAD  
×
dt  
R-1  
PT  
R-0  
PG  
R-1  
TR  
R-1  
OT  
R-1  
OC  
R-1  
UV  
R-1  
OV  
R-1  
PV  
Where, CLOAD is load capacitance, dVR/dt is rising  
voltage slew rate, and ICHG is charging current.  
Bit 7  
Bit 0  
When selecting the rising slew rate, a user needs to  
ensure that  
Bit 7  
PT: Temperature Warning  
PG: Power Good Warning  
TR: Tracking Fault  
R
W
U
= Readable bit  
= Writable bit  
= Unimplemented bit,  
read as ‘0’  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Note:  
OT: Temperature Fault  
- n = Value at POR reset  
ILOAD + ICHG < IOCP  
OC: Over Current Fault  
UV: Under Voltage Fault  
OV: Over Voltage Error (Fatal)  
PV: Phase Voltage Error (Fatal)  
Where IOCP is the overcurrent protection threshold of  
the JZY7010L. If the condition is not met, then the  
overcurrent protection will be triggered during the  
turn-on process. To avoid this, dVR/dt and the  
overcurrent protection threshold should be  
programmed to meet the condition above.  
- A warning/fault/error shall be encoded as ‘0’  
Figure 37. Protection Status Register ST  
Thresholds of overcurrent, over- and undervoltage  
protections, and Power Good limits can be  
programmed in the GUI Output Configuration  
window or directly via the I2C bus by writing into the  
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Page 20 of 33  
JZY7010L 10A DC-DC Intelligent POL  
3V to 13.2V Input • 0.5V to 5.5V Output  
CLS and PC2 registers shown in Figure 38 and  
Figure 39.  
R/W-0  
LR2  
R/W-0  
LR1  
R/W-0  
LR0  
R/W-1  
TCE  
R/W-1  
CLS3  
R/W-0  
CLS2  
R/W-1  
CLS1  
R/W-1  
CLS0  
Bit 0  
Bit 7  
Bit 7:5 LR[2:0], Load regulation configuration  
000: 0 V/A/Ohm  
R
W
U
= Readable bit  
= Writable bit  
= Unimplemented bit,  
read as ‘0’  
001: 0.39 V/A/Ohm  
010: 0.78 V/A/Ohm  
011: 1.18 V/A/Ohm  
100: 1.57 V/A/Ohm  
- n = Value at POR reset  
101: 1.96 V/A/Ohm  
110: 2.35 V/A/Ohm  
111: 2.75 V/A/Ohm  
Bit 4  
TCE, Temperature compensation enable  
0: disabled  
1: enabled  
Bit 3:0 CLS[3:0], Current limit setting  
0h: corresponds to 37%  
1h: corresponds to 47%  
…
Figure 40. Fault Management Window  
Bh: corresponds to 140%  
Values higher than Bh are translated to Bh (140%)  
R/W-0  
TRE  
R/W-1  
PVE  
R/W-0  
TRP  
R/W-0  
OTP  
R/W-0  
OCP  
R/W-0  
UVP  
R/W-1  
OVP  
R/W-1  
PVP  
Figure 38. Current Limit Setpoint Register CLS  
Bit 7  
Bit 0  
U
---  
U
U
R/W-0  
PGLL  
R/W-1  
R/W-0  
R/W-0  
R/W-0  
Bit 7  
TRE: Tracking fault enable  
1 = enabled  
0 = disabled  
R
W
U
= Readable bit  
= Writable bit  
= Unimplemented bit,  
read as ‘0’  
---  
---  
OVPL1 OVPL0 UVPL1 UVPL0  
Bit 0  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
PVE: Phase voltage error enable  
1 = enabled  
0 = disabled  
- n = Value at POR reset  
Bit 7:5 Unimplemented, read as ‘0’  
Bit 4  
R
W
U
= Readable bit  
= Writable bit  
= Unimplemented bit,  
read as ‘0’  
PGLL: Set Power Good Low Level  
1 = 95% of Vo  
TRC: Tracking fault protection  
1 = latching  
0 = non latching  
0 = 90% of Vo (Default)  
- n = Value at POR reset  
Bit 3:2 OVPL[1:0]: Set Over Voltage Protection  
Level  
OTC: Over temperature protection configuration  
1 = latching  
0 = non latching  
00 = 110% of Vo  
01 = 120% of Vo  
10 = 130% of Vo (Default)  
11 = 130% of Vo  
OCC: Over current protection configuration  
1 = latching  
0 = non latching  
Bit 1:0 UVPL[1:0]: Set Under Voltage Protection Level  
00 = 75% of Vo (Default)  
UVC: Under voltage protection configuration  
1 = latching  
0 = non latching  
01 = 80% of Vo  
10 = 85% of Vo  
OVPC: Over voltage protection configuration  
1 = latching  
0 = non latching  
Figure 39. Protection Configuration Register PC2  
PVC: Phase Voltage Protection  
Note that the overvoltage and undervoltage  
protection thresholds and Power Good limits are  
defined as percentages of the output voltage.  
Therefore, the absolute levels of the thresholds  
change when the output voltage setpoint is changed  
either by output voltage adjustment or by margining.  
0 = non latching  
Figure 41. Protection Configuration Register PC1  
If the non-latching protection is selected, a POL will  
attempt to restart every 130ms until the condition  
that triggered the protection is removed. When  
restarting, the output voltages follow tracking and  
sequencing settings.  
In addition, a user can change type of protections  
(latching or non-latching) or disable certain  
protections. These settings are programmed in the  
GUI Fault Management window shown in Figure 40  
or directly via the I2C by writing into the PC1 register  
shown in Figure 41.  
If the latching type is selected, a POL will turn off and  
stay off. The POL can be turned on after 130ms, if  
the condition that caused the fault is removed and  
the respective bit in the ST register was cleared, or  
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Page 21 of 33  
JZY7010L 10A DC-DC Intelligent POL  
3V to 13.2V Input • 0.5V to 5.5V Output  
the Turn On command was recycled, or the input  
voltage was recycled.  
All protections can be classified into three groups  
based on their effect on system operation: warnings,  
faults, and errors.  
9.3.2  
Faults  
This group includes overcurrent, overtemperature,  
undervoltage, and tracking protections. Triggering  
any protection in this group will turn off the POL.  
9.3.2.1  
Overcurrent Protection  
9.3.1  
Warnings  
Overcurrent protection is active whenever the output  
voltage of the POL exceeds the prebias voltage (if  
any). When the output current reaches the OC  
threshold, the output voltage will start decreasing.  
As soon as the output voltage decreases below the  
undervoltage protection threshold, the OC fault  
signal is generated, the POL turns off and the OC bit  
in the register ST is changed to 0. Both high side  
and low side switches of the POL are turned off  
instantly (fast turn-off).  
This group includes Overtemperature Warning and  
Power Good Signal. The warnings do not turn off  
POLs but rather generate signals that can be  
transmitted to a host controller via the I2C bus.  
9.3.1.1  
Overtemperature Warning  
The Overtemperature Warning is generated when  
temperature of the controller exceeds 120°C. The  
Overtemperature Warning changes the PT bit of the  
status register ST to 0 and sends the signal to the  
The temperature compensation is added to keep the  
DPM.  
Reporting is enabled in the GUI Fault  
Management window or directly via the I2C by writing  
into the PC3 register shown in Figure 43. When the  
temperature falls below 117°C, the PT bit is cleared  
and the Overtemperature Warning is removed.  
OC  
threshold  
approximately  
constant  
at  
temperatures above room temperature. Note that  
the temperature compensation can be disabled in  
the GUI Output Configuration window or directly via  
the I2C by writing into the CLS register. However, it  
is recommended to keep the temperature  
compensation enabled.  
9.3.1.2  
Power Good  
Power Good is an open collector output that is pulled  
low, if the output voltage is outside of the Power  
Good window. The window is formed by the Power  
Good High threshold that is equal to 110% of the  
output voltage and the Power Good Low threshold  
that can be programmed at 90 or 95% of the output  
voltage.  
9.3.2.2  
Undervoltage Protection  
The undervoltage protection is only active during  
steady state operation of the POL to prevent  
nuisance tripping. If the output voltage decreases  
below the UV threshold and there is no OC fault, the  
UV fault signal is generated, the POL turns off, and  
the UV bit in the register ST is changed to 0. The  
output voltage is ramped down according to  
sequencing and tracking settings (regular turn-off).  
The Power Good protection is only enabled after the  
output voltage reaches its steady state level. It is  
disabled during the transitions of the output voltage  
from one level to other as shown in Figure 42.  
9.3.2.3  
Overtemperature Protection  
The Power Good Warning pulls the Power Good pin  
low and changes the PG bit of the status register ST  
to 0. It sends the signal to the DPM, if the reporting  
is enabled. When the output voltage returns within  
the Power Good window, the PG pin is pulled high,  
the PG bit is cleared and the Power Good Warning is  
removed. The Power Good pin can also be pulled  
low by an external circuit to initiate the Power Good  
Warning.  
Overtemperature protection is active whenever the  
POL is powered up. If temperature of the controller  
exceeds 130°C, the OT fault is generated, POL turns  
off, and the OT bit in the register ST is changed to 0.  
The output voltage is ramped down according to  
sequencing and tracking settings (regular turn-off).  
If non-latching OTP is programmed, the POL will  
restart as soon as the temperature of the controller  
decreases below the Overtemperature Warning  
threshold of 120°C.  
Note: To retrieve status information, Status Monitoring in the GUI  
POL Group Configuration Window should be enabled (refer  
to JZM7100 Digital Power Manager Data Sheet). The DPM  
will retrieve the status information from each POL on a  
continuous basis.  
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Page 22 of 33  
JZY7010L 10A DC-DC Intelligent POL  
3V to 13.2V Input • 0.5V to 5.5V Output  
9.3.2.4  
Tracking Protection  
value of the difference exceeds 250mV, the tracking  
fault signal is generated, the POL turns off, and the  
TR bit in the register ST is changed to 0. Both high  
side and low side switches of the POL are turned off  
instantly (fast turn-off).  
Tracking protection is active only when the output  
voltage is ramping up. The purpose of the protection  
is to ensure that the voltage differential between  
multiple rails being tracked does not exceed 250mV.  
This protection eliminates the need for external  
clamping diodes between different voltage rails  
which are frequently recommended by ASIC  
manufacturers.  
The tracking protection can be disabled, if it  
contradicts requirements of a particular system (for  
example turning into high capacitive load where  
rising slew rate is not important). It can be disabled  
in the GUI Fault Management window or directly via  
the I2C bus by writing into the PC1 register.  
When the tracking protection is enabled, the POL  
continuously compares actual value of the output  
voltage to its programmed value as defined by the  
output voltage and its rising slew rate. If absolute  
Vo  
1
RUN  
PT and OT  
OC enabled  
0
continuously enabled  
1
0
Vo_Rise  
Vo_Stable  
Vo_Fall  
Vo_Stable  
Vo_Rise  
Vo_Stable  
Vo_Fall  
OVP Limit  
OVP Limit  
PG High Limit  
PG High Limit  
OVP Limit  
PG High Limit  
Vo  
PGLow Limit  
UVP Limit  
PGLow Limit  
UVP Limit  
PGLow Limit  
UVP Limit  
1.0V  
pre-biased output  
Time  
Figure 42. Protections Enable Conditions  
The OV threshold can be programmed from 110% to  
130% of the output voltage setpoint, but not lower  
than 1.0V.  
9.3.3  
Errors  
The group includes overvoltage protection and the  
phase voltage error. The phase voltage error is not  
available in JZY7010L.  
9.3.4  
Faults and Errors Propagation  
The feature adds flexibility to the fault management  
scheme by giving users control over propagation of  
fault signals within and outside of the system. The  
propagation means that a fault in one POL can be  
programmed to turn off other POLs and devices in  
the system, even if they are not directly affected by  
the fault.  
9.3.3.1  
Overvoltage Protection  
The overvoltage protection is active whenever the  
output voltage of the POL exceeds the pre-bias  
voltage (if any). If the output voltage exceeds the  
overvoltage protection threshold, the overvoltage  
error signal is generated, the POL turns off, and the  
OV bit in the register ST is changed to 0. The high  
side switch is turned off instantly, and simultaneously  
the low side switch is turned on to ensure reliable  
protection of sensitive loads. The low side switch  
provides low impedance path to quickly dissipate  
energy stored in the output filter and achieve  
effective voltage limitation.  
9.3.4.1  
Grouping of POLs  
Z-Series POLs can be arranged in several groups to  
simplify fault management. A group of POLs is  
defined as a number of POLs with interconnected  
OK pins. A group can include from 1 to 32 POLs. If  
fault propagation within a group is desired, the  
propagation bit needs to be checked in the GUI Fault  
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Page 23 of 33  
JZY7010L 10A DC-DC Intelligent POL  
3V to 13.2V Input • 0.5V to 5.5V Output  
Figure 44. Fault and Error Propagation Window  
Management Window. The parameters can also be  
programmed directly via the I2C bus by writing into  
the PC3 register shown in Figure 43.  
In this case low OK line will signal DPM to pull other  
OK lines low to initiate shutdown of other POLs as  
programmed in the GUI Fault and Error Propagation  
window. If an error is propagated, the DPM can also  
generate commands to turn off a front end (a DC-DC  
converter generating the intermediate bus voltage)  
and trigger an optional crowbar protection to  
accelerate removal of the IBV voltage.  
When propagation is enabled, the faulty POL pulls its  
OK pin low. A low OK line initiates turn-off of other  
POLs in the group.  
R/W-0  
PTM  
Bit 7  
R/W-0  
PGM  
R/W-1  
TRP  
R/W-1  
OTP  
R/W-1  
OCP  
R/W-1  
UVP  
R/W-1  
OVP  
R/W-1  
PVP  
9.3.4.2  
Propagation Process  
Bit 0  
Propagation of a fault (OCP, UVP, OTP, and TRP)  
initiates regular turn-off of other POLs. The faulty  
POL in this case performs either the regular or the  
fast turn-off depending on a specific fault as  
described in section 9.3.2.  
Bit 7  
PTM: Temperature warning Message  
1 = enabled  
0 = disabled  
R
W
U
= Readable bit  
= Writable bit  
= Unimplemented bit,  
read as ‘0’  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
PGM: Power good message  
1 = enabled  
0 = disabled  
- n = Value at POR reset  
TRP  
: Tracking fault propagation  
Propagation of an error initiates fast turn-off of other  
POLs. The faulty POL performs the fast turn-off and  
turns on its low side switch.  
1 = enabled  
0 = disabled  
OTP: Over temperature fault propagation  
1 = enabled  
0 = disabled  
Example of the fault propagation is shown in Figure  
45 - Figure 46. In this three-output system (refer to  
the block diagram in Figure 25), the POL powering  
the output V3 (Ch 1 in the picture) encounters the  
undervoltage fault after the turn-on. When the fault  
propagation is not enabled, the POL turns off and  
generates the UV fault signal. Because the UV fault  
triggers the regular turn off, the POL meets its turn-  
off delay and falling slew rate settings during the  
turn-ff process as shown in Figure 45. Since the UV  
fault is programmed to be non-latching, the POL will  
attempt to restart every 130ms, repeating the  
process described above until the condition causing  
the undervoltage is removed.  
OCP: Over current fault propagation  
1 = enabled  
0 = disabled  
UVP: Under voltage fault propagation  
1 = enabled  
0 = disabled  
OVP: Over voltage error propagation  
1 = enabled  
0 = disabled  
PVP: Phase voltage error propagation  
1 = enabled  
0 = disabled  
Figure 43. Protection Configuration Register PC3  
In addition, the OK lines can be connected to the  
DPM to facilitate propagation of faults and errors  
between groups. One DPM can control up to 4  
independent groups. To enable fault propagation  
between groups, the respective bit needs to be  
checked in the GUI Fault and Error Propagation  
window shown in Figure 44.  
If the fault propagation between groups is enabled,  
the POL powering the output V3 pulls its OK line low  
and the DPM propagates the signal to the POL  
powering the output V1 that belongs to other group.  
The POL powering the output V1 (Ch3 in the picture)  
executes the regular turn-off. Since both V1 and V3  
have the same delay and slew rate settings they will  
continue to turn off and on synchronously every  
130ms as shown in Figure 46 until the condition  
causing the undervoltage is removed. The POL  
powering the output V2 continues to ramp up until it  
reaches its steady state level.  
130ms is the interval from the instant of time when  
the output voltage ramps down to zero until the  
output voltage starts to ramp up again. Therefore,  
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Page 24 of 33  
JZY7010L 10A DC-DC Intelligent POL  
3V to 13.2V Input • 0.5V to 5.5V Output  
the 130ms hiccup interval is guaranteed regardless  
of the turn-off delay setting.  
Figure 46. Turn-On into UVP On V3. The UV Fault Is  
Programmed To Be Non-Latching and Propagate  
From Group C to Group A. Ch1 – V3 (Group C),  
Ch2 – V2, Ch3 – V1 (Group A)  
Figure 45. Turn-On into UVP On V3. The UV Fault Is  
Programmed To Be Non-Latching. Ch1 – V3  
(Group C), Ch2 – V2, Ch3 – V1 (Group A)  
Summary of protections, their parameters and features is shown in Table 3.  
Table 3. Summary of Protections Parameters and Features  
Code  
Name  
Type  
When Active  
Turn  
Off  
Low Side  
Switch  
Propagation  
Disable  
PT  
Pretemperature  
Warning  
Power Good  
Warning  
Warning  
Whenever VIN is applied  
During steady state  
No  
N/A  
Sends signal to  
DPM  
Sends signal to  
DPM  
No  
No  
PG  
No  
N/A  
TR  
OT  
OC  
UV  
OV  
Tracking  
Overtemperature  
Overcurrent  
Undervoltage  
Overvoltage  
Fault  
Fault  
Fault  
Fault  
Error  
During ramp up  
Fast  
Regular  
Fast  
Regular  
Fast  
Off  
Off  
Off  
Off  
On  
Regular turn off  
Regular turn off  
Regular turn off  
Regular turn off  
Fast turn off  
Yes  
No  
No  
No  
No  
Whenever VIN is applied  
When VOUT exceeds prebias  
During steady state  
When VOUT exceeds prebias  
Switching actions of all POLs connected to the SD  
line are synchronized to the master clock generated  
by the DPM. Each POL is equipped with a PLL and  
a frequency divider so they can operate at multiples  
(including fractional) of the master clock frequency  
as programmed by a user. The POL converters can  
operate at 500kHz, 750kHz, and 1MHz. Although  
synchronized, switching frequencies of different  
9.4 PWM Parameters  
Z-Series POLs utilize the digital PWM controller.  
The controller enables users to program most of the  
PWM performance parameters, such as switching  
frequency, interleave, duty cycle, and feedback loop  
compensation.  
POLs are independent of each other.  
It is  
9.4.1  
Switching Frequency  
permissible to mix POLs operating at different  
frequencies in one system. It allows optimizing  
efficiency and transient response of each POL in the  
system individually.  
The switching frequency can be programmed in the  
GUI PWM Controller window shown in Figure 47 or  
directly via the I2C bus by writing into the INT register  
shown in Figure 48. Note that the content of the  
register can be changed only when the POL is  
turned off.  
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Page 25 of 33  
JZY7010L 10A DC-DC Intelligent POL  
3V to 13.2V Input • 0.5V to 5.5V Output  
input source from all POLs is added together as  
shown in Figure 49.  
Figure 49. Input Voltage Noise, No Interleave  
Figure 47. PWM Controller Window  
Figure 50 shows the input voltage noise of the three-  
output system with programmed interleave. Instead  
of all three POLs switching at the same time as in  
the previous example, the POLs V1, V2, and V3  
switch at 0°, 123.75°, and 247.5°, respectively.  
Noise is spread evenly across the switching cycle  
resulting in more than 1.5 times reduction. To  
achieve similar noise reduction without the interleave  
will require the addition of an external LC filter.  
R/W-0  
FRQ2  
Bit 7  
R/W-0  
FRQ1  
R/W-0 R/W-01) R/W-01) R/W-01) R/W-01) R/W-01)  
FRQ0  
INT4  
INT3  
INT2  
INT1  
INT0  
Bit 0  
Bit 7:5 FRQ[2:0]: PWM Frequency Selection  
000: 500kHz  
R
W
U
= Readable bit  
= Writable bit  
= Unimplemented bit,  
read as ‘0’  
001: 750kHz  
010: 1000lHz  
011: 1250kHz  
100: 1250kHz  
- n = Value at POR reset  
101: 1500kHz  
110: 1750kHz  
111: 2000kHz  
Bit 4:0 INT[4:0]: Interleave position  
00h: Ton starts with 0.0° Phase lag to SYNQ/DATA Line  
01h: Ton starts with 11.25° Phase lag to SYNQ/DATA Line  
02h: Ton starts with 22.50° Phase lag to SYNQ/DATA Line  
…
1Fh: Ton starts with 348.75° Phase lag to SYNQ/DATA Line  
1) Initial value depends on the state of the Interleave Mode (IM) Input:  
IM=Open: At POR reset the 5 corresponding ADDRESS bits are loaded  
IM=Low: At POR reset a 0 is loaded  
Figure 48. Interleave Configuration Register INT  
9.4.2  
Interleave  
Interleave is defined as a phase delay between the  
synchronizing slope of the master clock on the SD  
pin and PWM signal of a POL. The interleave can  
be programmed in the GUI PWM Controller window  
or directly via the I2C bus by writing into the INT  
register.  
Figure 50. Input Voltage Noise with Interleave  
Similar noise reduction can be achieved on the  
output of POLs connected in parallel. Figure 51 and  
Figure 52 show the output noise of two JZY7010Ls  
connected in parallel without and with 180°  
interleave, respectively. Resulting noise reduction is  
Every POL generates switching noise.  
If no  
interleave is programmed, all POLs in the system  
switch simultaneously and noise reflected to the  
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Page 26 of 33  
JZY7010L 10A DC-DC Intelligent POL  
3V to 13.2V Input • 0.5V to 5.5V Output  
more than 2 times and is equivalent to doubling  
switching frequency or adding extra capacitance on  
the output of the POLs.  
between the two parameters is characterized by the  
duty cycle and can be estimated from the following  
equation:  
VOUT  
DC =  
,
VIN.MIN  
Where, DC is the duty cycle, VOUT is the required  
maximum output voltage (including margining),  
VIN.MIN is the minimum input voltage.  
It is good practice to limit the maximum duty cycle of  
the PWM controller to a somewhat higher value  
compared to the steady-state duty cycle as  
expressed by the above equation. This will further  
protect the output from excessive voltages. The duty  
cycle limit can be programmed in the GUI PWM  
Controller window or directly via the I2C bus by  
writing into the DCL register shown in Figure 53.  
Figure 51. Output Voltage Noise, Full Load, No Interleave  
R/W-1  
DCL5  
Bit 7  
R/W-1  
DCL4  
R/W-1  
DCL3  
R/W-0  
DCL2  
R/W-1  
DCL1  
R/W-0  
DCL0  
R/W-0  
HI  
R/W-0  
LO  
Bit 0  
R
W
U
= Readable bit  
= Writable bit  
= Unimplemented bit,  
read as ‘0’  
Bit 7:2 DCL[5:0], Duty Cycle Limitation  
00h: 0  
01h: 1/64  
…
- n = Value at POR reset  
3Fh: 63/64  
Bit 1: HI, ADC high saturation feed-forward  
0: disabled  
1: enabled  
Bit 0: LO, ADC low saturation feed-forward  
0: disabled  
1: enabled  
Figure 53. Duty Cycle Limit Register  
9.4.4  
ADC Saturation Feedforward  
To speed up the PWM response in case of heavy  
dynamic loads, the duty cycle can be forced either to  
0 or the duty cycle limit depending on the polarity of  
the transient. This function is equivalent to having  
two comparators defining a window around the  
output voltage setpoint. When an error signal is  
inside the window, it will produce gradual duty cycle  
change proportional to the error signal. If the error  
signal goes outside the window (usually due to large  
output current steps), the duty cycle will change to its  
limit in one switching cycle. In most cases this will  
significantly improve transient response of the  
controller, reducing amount of required external  
capacitance.  
Figure 52. Output Voltage Noise, Full Load, 180° Interleave  
The JZY7010L interleave feature is similar to that of  
multiphase converters, however, unlike in the case of  
multiphase converters, interleave does not have to  
be equal to 360/N, where N is the number of POLs in  
a system. JZY7010L interleave is independent of  
the number of POLs in a system and is fully  
programmable in 11.25° steps. It allows maximum  
output noise reduction by intelligently spreading  
switching energy.  
9.4.3  
Duty Cycle Limit  
The JZY7010L is a step-down converter therefore  
VOUT is always less than VIN. The relationship  
Under certain circumstances, usually when the  
maximum duty cycle limit significantly exceeds its  
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Page 27 of 33  
JZY7010L 10A DC-DC Intelligent POL  
3V to 13.2V Input • 0.5V to 5.5V Output  
nominal value, the ADC saturation can lead to the  
overcompensation of the output error. The  
B3). The coefficients are automatically calculated  
when desired frequency of poles and zeros is  
entered in the GUI PWM Controller window. The  
coefficients are stored in the C0H, C0L, C1H, C1L,  
C2H, C2L, C3H, C3L, B1, B2, and B3 registers.  
phenomenon manifests itself as low frequency  
oscillations on the output of the POL. It can usually  
be reduced or eliminated by disabling the ADC  
saturation or limiting the maximum duty cycle to 120-  
140% of the calculated value. It is not recommended  
to use ADC saturation for output voltages higher  
than 2.0V.  
Note: The GUI automatically transforms zero and pole  
frequencies into the digital filter coefficients. It is strongly  
recommended to use the GUI to determine the filter  
coefficients.  
The ADC saturation feedforward can be  
programmed in the GUI PWM Controller window or  
directly via the I2C bus by writing into the DCL  
register.  
Programming feedback loop compensation allows  
optimizing POL performance for various application  
conditions. For example, increase in bandwidth can  
significantly improve dynamic response.  
9.4.5  
Feedback Loop Compensation  
9.5 Current Share  
Feedback loop compensation can be programmed in  
the GUI PWM Controller window by setting  
frequency of poles and zeros of the transfer function.  
The POL converters are equipped with the digital  
current share function. To activate the current share,  
interconnect the CS pins of the POLs connected in  
parallel. The digital signal transmitted over the CS  
line sets output currents of all POLs to the same  
level.  
The transfer function of the POL converter is shown  
in Figure 54. It is a third order function with two  
zeros and three poles. Pole 1 is the integrator pole,  
Pole 2 is used in conjunction with Zero 1 and Zero 2  
to adjust the phase lead and limit the gain increase  
in mid band. Pole 3 is used as a high frequency low-  
pass filter to limit PWM noise.  
When POLs are connected in parallel, they must be  
included in the same parallel bus in the GUI System  
Configuration window shown in Figure 55. In this  
case, the GUI automatically copies parameters of  
one POL onto all POLs connected to the parallel  
bus. It makes it impossible to configure different  
performance parameters for POLs connected in  
parallel except for interleave and load regulation  
settings that are independent. The interleave allows  
to reduce and move the output noise of the  
converters connected in parallel to higher  
frequencies as shown in Figure 51 and Figure 52.  
The load regulation allows controlling the current  
share loop gain in case of small signal oscillations. It  
is recommended to always add a small amount of  
load regulation to one of the converters connected in  
parallel to reduce loop gain and therefore improve  
stability.  
Magnitude[dB]  
50  
40  
30  
20  
10  
Z1 P1 Z2 P2  
P3  
P1: Pole 1  
P2: Pole 3  
P3: Pole 3  
Z1: Zero 1  
Z2: Zero 2  
Freq  
[kHz]  
0.1  
0.1  
1
1
10  
10  
100  
1000  
1000  
Phase  
[°]  
+45  
Freq  
[kHz]  
0
-45  
100  
-90  
9.6 Performance Parameters Monitoring  
-135  
-180  
The POL converters can monitor their own  
performance parameters such as output voltage,  
output current, and temperature.  
Figure 54. Transfer Function of PWM  
Positions of poles and zeroes are determined by  
coefficients of the digital filter. The filter is  
characterized by four numerator coefficients (C0, C1,  
C2, C3) and three denominator coefficients (B1, B2,  
The output voltage is measured at the output sense  
pins, output current is measured using the ESR of  
the output inductor and temperature is measured by  
the thermal sensor built into the controller IC. Output  
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Page 28 of 33  
JZY7010L 10A DC-DC Intelligent POL  
3V to 13.2V Input • 0.5V to 5.5V Output  
current readings are adjusted based on temperature  
readings to compensate for the change of ESR of  
the inductor with temperature.  
Monitored parameters are stored in registers (VOM,  
IOM, and TMON) that are continuously updated. If  
the Retrieve Monitoring bits in the GUI Group  
Configuration window shown in Figure 56 are  
checked, those registers are being copied into the  
ring buffer located in the DPM. Contents of the ring  
buffer can be displayed in the GUI IBS Monitoring  
Window shown in Figure 57 or it can be read directly  
via the I2C bus using high and low level commands  
as described in the ‘”DPM Programming Manual”.  
An 8-Bit Analog to Digital Converter (ADC) converts  
the output voltage, output current, and temperature  
into a digital signal to be transmitted via the serial  
interface. The ADC allows a minimum sampling  
frequency of 1kHz for all three values.  
Figure 55. GUI System Configuration Window  
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Page 29 of 33  
JZY7010L 10A DC-DC Intelligent POL  
3V to 13.2V Input • 0.5V to 5.5V Output  
Figure 56. POL Group Configuration Window  
00 and EN60950, although specific applications may  
have other or additional requirements.  
10. Safety  
The JZY7010L POL converters do not provide  
isolation from input to output. The input devices  
powering JZY7010L must provide relevant isolation  
requirements according to all IEC60950 based  
standards. Nevertheless, if the system using the  
converter needs to receive safety agency approval,  
certain rules must be followed in the design of the  
system. In particular, all of the creepage and  
clearance requirements of the end-use safety  
The JZY7010L POL converters have no internal  
fuse. If required, the external fuse needs to be  
provided to protect the converter from catastrophic  
failure. Refer to the “Input Fuse Selection for DC/DC  
converters” application note on www.cd4power.com  
for proper selection of the input fuse. Both input  
traces and the chassis ground trace (if applicable)  
must be capable of conducting a current of 1.5 times  
the value of the fuse without opening. The fuse must  
not be placed in the grounded input line.  
requirements must be observed.  
requirements are included in UL60950 - CSA60950-  
These  
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Page 30 of 33  
JZY7010L 10A DC-DC Intelligent POL  
3V to 13.2V Input • 0.5V to 5.5V Output  
Abnormal and component failure tests were  
conducted with the POL input protected by a fast-  
acting 65 V, 15 A, fuse. If a fuse rated greater than  
15 A is used, additional testing may be required.  
In order for the output of the JZY7010L POL  
converter to be considered as SELV (Safety Extra  
Low Voltage), according to all IEC60950 based  
standards, the input to the POL needs to be supplied  
by an isolated secondary source providing a SELV  
also.  
Figure 57. IBS Monitoring Window  
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Page 31 of 33  
JZY7010L 10A DC-DC Intelligent POL  
3V to 13.2V Input • 0.5V to 5.5V Output  
11. Mechanical Drawings  
All Dimensions are in mm  
Tolerances:  
0.5-10 ±0.1  
10-100 ±0.2  
Figure 58. Mechanical Drawing  
‘
Figure 59. Pinout Diagram (Bottom View)  
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Page 32 of 33  
JZY7010L 10A DC-DC Intelligent POL  
3V to 13.2V Input • 0.5V to 5.5V Output  
8.6  
32  
3
6
10  
10  
(x 3)  
1.4  
1.1  
0.1  
0.1  
16.9  
Top View  
14.2  
0.8  
1
2.4  
2.03  
1.27  
2.54  
(x 22)  
Figure 60. Recommended PCB Pad Sizes  
AIR Ä  
14.9  
10.6  
14.9  
8.6  
14.6  
15.2  
6.4  
15.1  
11.4  
16.0  
24.2  
Vi+  
Vo+  
8.4  
0.45mm Ø Thermal Via x 48  
0.45mm Ø Thermal Via x 48  
V-  
0.45mm Ø Thermal Via x 56  
41.3  
Figure 61. Recommended PCB Layout for Multilayer PCBs  
Notes:  
1. NUCLEAR AND MEDICAL APPLICATIONS - C&D Technologies products are not designed, intended for use in, or authorized for use as  
critical components in life support systems, equipment used in hazardous environments, or nuclear control systems without the express  
written consent of the respective divisional president of C&D Technologies, Inc.  
2. TECHNICAL REVISIONS - Specifications are subject to change without notice  
2
I C is a trademark of Philips Corporation.  
C&D Technologies, Inc.  
11 Cabot Boulevard, Mansfield,  
MA 02048-1151, USA  
C&D Technologies, Inc.  
3400 E Britannia Drive, Tucson,  
Arizona 85706, USA  
C&D Technologies Inc. reserve the right to alter or improve the specification, internal design or manufacturing process at any time, without notice.  
Please check with your supplier or visit our website to ensure that you have the current and complete specification for your product before use.  
© C&D Technologies Inc. 2005  
Tel: +1 (508) 339-3000  
Fax: +1 (800) 233-276  
email: sales@cdtechno.com  
Tel: +1 (800) 547-2537  
Fax: +1 (520) 741-4598  
Page 33 of 33  
No part of this publication may be copied, transmitted or stored in a retrieval system or reproduced in any way including, but not limited to, photography, photocopy,  
magnetic or other recording means, without prior written permission from C&D Technologies Inc. Instructions for use are available from www.cd4power.com  
www.cd4power.com  
厂商 型号 描述 页数 下载

MURATA

 		JZY7007L [ DC-DC Regulated Power Supply Module, 1 Output, Hybrid, SMT-36 ] 34 页

MURATA

 		JZY7120L [ DC-DC Regulated Power Supply Module, 1 Output, Hybrid, SMT-25 ] 33 页

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