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CYM1861V33PM-25C

型号：

CYM1861V33PM-25C

品牌：

CYPRESS[ CYPRESS ]

页数：

6 页

PDF大小：

162 K

下载PDF手册
3
fax id: 2053  
PRELIMINARY  
CYM1861V33  
2,048K x 32 3.3V Static RAM Module  
packages mounted on an epoxy laminate substrate. Four chip  
selects are used to independently enable the four bytes. Read-  
ing or writing can be executed on individual bytes or any com-  
Features  
• High-density 3.3V 64-megabit SRAM module  
bination of multiple bytes through proper use of selects.  
• 32-bit Standard Footprint supports densities from 16K  
x 32 through 2M x 32  
• High-speed SRAMs  
— Access time of 20 ns  
• 72 pins  
The CYM1861V33 is designed for use with standard 72-pin  
SIMM sockets. The pinout is downward compatible with the  
64-pin JEDEC SIMM module family (CYM1821, CYM1831,  
CYM1836, and CYM1841). Thus, a single motherboard de-  
sign can be used to accommodate memory depth ranging from  
16K words (CYM1821) to 2,048K words (CYM1861V33). The  
CYM1861V33 is offered in vertical SIMM configuration and is  
available with tin-lead edge contacts.  
• Available in SIMM format  
Functional Description  
The CYM1861V33 is a high-performance 3.3V 64-megabit  
static RAM module organized as 2,048K words by 32 bits. This  
module is constructed from sixteen 1,024K x 4 SRAMs in SOJ  
Presence detect pins (PD –PD ) are used to identify module  
0 3  
memory density in applications where modules with alternate  
word depths can be interchanged.  
Logic Block Diagram  
Pin Configuration  
ZIP/SIMM  
Top View  
NC  
PD  
1
3
5
NC  
3
PD  
0
2
4
2
PD  
GND  
6
8
7
9
PD  
1
8
I/O  
0
I/O  
I/O  
1
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
I/O  
I/O  
I/O  
9
10  
11  
I/O  
2
I/O  
3
V
CC  
7
8
A
0
A0–A19  
PD - OPEN  
0
A
A
1
2
PD - GND  
A
1
A
PD - GND  
2
A
9
I/O  
I/O  
I/O  
I/O  
12  
13  
14  
15  
20  
Buffer  
I/O  
I/O  
I/O  
I/O  
PD - OPEN  
4
5
6
7
OE  
3
WE  
I/O – I/O  
I/O –I/O  
4 7  
GND  
4
7
WE  
4
4
1M x 4  
SRAM  
1M x 4  
SRAM  
33  
35  
A
15  
A
14  
I/O – I/O  
0
I/O –I/O  
34  
36  
3
0
3
4
CS  
CS  
4
CS  
2
1
37  
39  
41  
43  
45  
47  
49  
51  
53  
55  
57  
59  
61  
63  
65  
67  
69  
71  
4
CS  
3
16  
38  
40  
42  
44  
46  
48  
50  
52  
54  
56  
58  
60  
62  
64  
66  
68  
70  
72  
A
17  
A
–
I/O  
12 15  
–
I/O  
I/O  
I/O  
OE  
12  
15  
GND  
4
4
4
1M x 4  
SRAM  
1M x 4  
SRAM  
I/O  
I/O  
I/O  
I/O  
24  
25  
26  
27  
I/O – I/O  
8
I/O – I/O  
8 11  
I/O  
11  
16  
4
I/O  
17  
I/O  
18  
I/O  
19  
–CS  
CS  
A
1
3
4
A
10  
–
–
–
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
23  
20  
23  
A
4
A
5
20  
4
4
4
A
1M x 4  
SRAM  
1M x 4  
SRAM  
11  
PAL  
–
I/O  
I/O  
16  
19  
16  
19  
A
12  
A
4
V
CC  
A
20  
13  
A
6
I/O  
20  
I/O  
I/O  
I/O  
I/O  
28  
29  
30  
31  
I/O  
21  
I/O  
–
I/O –I/O  
28  
I/O  
I/O  
22  
31  
28  
31  
4
4
1M x 4  
SRAM  
1M x 4  
SRAM  
I/O  
23  
–
–
I/O  
I/O  
I/O  
I/O  
24  
27  
24  
27  
GND  
4
4
A
18  
20  
A
19  
A
NC  
1861V33–1  
1861V33–2  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
June 30, 1998  
PRELIMINARY  
CYM1861V33  
Selection Guide  
1861V33-20  
25  
1861V33-25  
35  
Maximum Access Time (ns)  
Maximum Operating Current (mA)  
Maximum Standby Current (mA)  
2400  
2400  
1050  
1050  
Maximum Ratings  
Operating Range  
Ambient  
Temperature  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Range  
V
CC  
Commercial  
0°C to +70°C  
3.3 V  
+ 10% –5%  
Storage Temperature ................................. –55°C to +125°C  
Ambient Temperature with  
Power Applied............................................... –10°C to +85°C  
Supply Voltage to Ground Potential ............... –0.5V to +4.6V  
DC Voltage Applied to Outputs  
in High Z State ................................................ –0.5V to +V  
CC  
DC Input Voltage............................................ –0.5V to +4.6V  
Electrical Characteristics Over the Operating Range  
Parameter  
Description  
Output HIGH Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
Test Conditions  
Min.  
Max.  
Unit  
V
V
V
V
= Min., I = −4.0 mA  
OH  
2.4  
OH  
CC  
CC  
V
= Min., I = 4.0 mA  
0.4  
V
OL  
OL  
V
2.2  
–0.3V  
–10  
V
+ 0.3  
CC  
V
IH  
IL  
V
0.8  
+10  
+20  
2400  
V
I
I
I
Input Load Current  
GND < V < V  
CC  
µA  
µA  
mA  
IX  
I
Output Leakage Current  
GND < V < V , Output Disabled  
–20  
OZ  
CC  
O
CC  
V
Operating Supply  
V
= Max., I  
= 0 mA,  
OUT  
CC  
CC  
Current  
CS < V  
N IL  
I
I
Automatic CS Power-Down  
Current  
Max. V , CS > V ,  
Min. Duty Cycle = 100%  
1050  
500  
mA  
mA  
SB1  
SB2  
CC  
IH  
[1]  
Automatic CS Power-Down  
Max. V  
,
CC  
[1]  
Current  
CS > V − 0.2V,  
CC  
V
V
> V − 0.2V, or  
< 0.2V  
IN  
IN  
CC  
Capacitance[2]  
Parameter  
Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
T = 25°C, f = 1 MHz,  
Max.  
7
Unit  
C
C
pF  
pF  
IN  
A
V
= 3.3V  
CC  
14  
OUT  
Notes:  
1. A pull-up resistor to VCC on the CS input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given.  
2. Tested on a sample basis.  
2
PRELIMINARY  
CYM1861V33  
AC Test Loads and Waveforms  
R1 589 Ω  
R1 589  
ALL INPUT PULSES  
90%  
10%  
Ω
3.3V  
3.3V  
OUTPUT  
3.3V  
GND  
90%  
10%  
OUTPUT  
R2  
434  
R2  
434  
Ω
Ω
30 pF  
5 pF  
< 5 ns  
< 5 ns  
INCLUDING  
JIG AND  
SCOPE  
INCLUDING  
JIG AND  
SCOPE  
1861V33–3  
1861V33–4  
(a)  
(b)  
Equivalent to:  
THÉVENIN EQUIVALENT  
250  
Ω
1.40V  
OUTPUT  
[3]  
Switching Characteristics Over the Operating Range  
1861V33-20  
Min. Max.  
1861V33-25  
Min. Max.  
Parameter  
Description  
Unit  
READ CYCLE  
t
t
t
t
t
t
t
t
t
t
Read Cycle Time  
20  
3
25  
3
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RC  
Address to Data Valid  
Data Hold from Address Change  
CS LOW to Data Valid  
OE LOW to Data Valid  
OE LOW to Low Z  
20  
25  
AA  
OHA  
ACS  
DOE  
LZOE  
HZOE  
LZCS  
HZCS  
20  
12  
25  
15  
0
3
4
7
OE HIGH to High Z  
10  
12  
[4]  
CS LOW to Low Z  
[4, 5]  
CS HIGH to High Z  
10  
20  
12  
25  
CS HIGH to Power-Down  
PD  
[6]  
WRITE CYCLE  
t
t
t
t
t
t
t
t
t
t
Write Cycle Time  
20  
17  
17  
3
25  
20  
20  
3
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
CS LOW to Write End  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
SCS  
AW  
HA  
2
2
SA  
15  
12  
2
20  
15  
2
PWE  
SD  
Data Set-Up to Write End  
Data Hold from Write End  
WE HIGH to Low Z  
HD  
3
3
LZWE  
HZWE  
[5]  
WE LOW to High Z  
0
12  
0
12  
Notes:  
3. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified  
OL/IOH and 30-pF load capacitance.  
I
4. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device. These parameters are guaranteed and not 100% tested.  
5. tHZCS and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage.  
6. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can  
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.  
3
PRELIMINARY  
CYM1861V33  
Switching Waveforms  
[7,8]  
Read Cycle No. 1  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
1861V33–5  
[7,9]  
Read Cycle No. 2  
t
RC  
CS  
t
ACS  
OE  
t
HZOE  
t
DOE  
t
HZCS  
t
LZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA VALID  
DATA OUT  
t
LZCS  
t
PD  
t
PU  
ICC  
V
CC  
50%  
50%  
SUPPLY  
CURRENT  
ISB  
1861V33–6  
Notes:  
7. WE is HIGH for read cycle.  
8. Device is continuously selected, CS = VIL, and OE= VIL  
9. Address valid prior to or coincident with CS transition LOW.  
.
4
PRELIMINARY  
CYM1861V33  
Switching Waveforms (continued)  
[6]  
Write Cycle No. 1 (WE Controlled)  
t
WC  
ADDRESS  
CS  
t
SCS  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
t
HD  
SD  
DATA IN  
DATA VALID  
t
t
LZWE  
HZWE  
HIGH IMPEDANCE  
DATA OUT  
DATA UNDEFINED  
1861V33–7  
[6,10]  
Write Cycle No. 2 (CS Controlled)  
t
WC  
ADDRESS  
t
SA  
t
SCS  
CS  
t
t
HA  
AW  
t
PWE  
WE  
t
t
HD  
SD  
DATA IN  
DATA VALID  
t
HZWE  
HIGH IMPEDANCE  
DATA OUT  
DATA UNDEFINED  
1861V33–8  
Note:  
10. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.  
Truth Table  
CS WE OE Inputs/Output  
Mode  
Deselect/Power-Down  
Read  
H
L
L
L
X
H
L
X
L
High Z  
Data Out  
Data In  
High Z  
X
H
Write  
H
Deselect  
5
PRELIMINARY  
CYM1861V33  
Ordering Information  
Speed  
Package  
Type  
Operating  
Range  
(ns)  
Ordering Code  
Package Type  
72-Pin Plastic SIMM Module  
72-Pin Plastic SIMM Module  
25  
CYM1861V33PM-20C  
CYM1861V33PM-25C  
PM48  
PM48  
Commercial  
Commercial  
35  
Document #: 38-M-00091  
Package Diagram  
72-Pin SIMM Module PM48  
© Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
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