IDT8N0QV01 Rev H Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-VCXO
The four configuration registers for the P, M (MINT & MFRAC) and N
dividers which are named Pn, MINTn, MFRACn and Nn with n = 0 to
3. “n” denominates one of the four possible configurations.
Principles of Operation
The block diagram consists of the internal 3rd overtone crystal and
oscillator which provide the reference clock fXTAL of 114.285MHz.
The PLL includes the FemtoClock NGVCO along with the pre-divider
(P), the feedback divider (M) and the post divider (N). The P, M, and
N dividers determine the output frequency based on the fXTAL
reference and must be configured correctly for proper operation. The
feedback divider is fractional supporting a huge number of output
frequencies. The configuration of the feedback divider to integer-only
values results in an improved output phase noise characteristics at
the expense of the range of output frequencies. In addition, internal
registers are used to hold up to four different factory pre-set P, M, and
N configuration settings. These default pre-sets are stored in the I2C
registers at power-up. Each configuration is selected via the
FSEL[1:0] pins and can be read back using the SCLK and SDATA
pins.
As identified previously, the configurations of P, M (MINT & MFRAC)
and N divider settings are stored the I2C register, and the
configuration loaded at power-up is determined by the FSEL[1:0]
pins.
Table 4. Frequency Selection
Input
FSEL1
FSEL0
Selects
Register
0 (def.)
0 (def.)
Frequency 0
Frequency 1
Frequency 2
Frequency 3
P0, MINT0, MFRAC0, N0
P1, MINT1, MFRAC1, N1
P2, MINT2, MFRAC2, N2
P3, MINT3, MFRAC3, N3
0
1
1
1
0
1
The user may choose to operate the device at an output frequency
different than that set by the factory. After power-up, the user may
write new P, N and M settings into one or more of the four
configuration registers and then use the FSEL[1:0] pins to select the
newly programmed configuration. Note that the I2C registers are
volatile and a power supply cycle will reload the pre-set factory
default conditions.
Frequency Configuration
An order code is assigned to each frequency and VCXO pull range
configuration programmed by the factory (default frequencies). For
available order codes, see the FemtoClock NG Ceramic-Package XO
and VCXO Ordering Product Information document.
If the user does choose to write a different P, M, and N configuration,
it is recommended to write to a configuration which is not currently
selected by FSEL[1:0] and then change to that configuration after the
I2C transaction has completed. Changing the FSEL[1:0] controls
results in an immediate change of the output frequency to the
selected register values. The P, M, and N frequency configurations
support an output frequency range 15.476MHz to 260MHz.
For more information and guidelines on programming of the device
for custom frequency configurations, programming for a specific
VCXO pull range, the available APR (absolute pull range), the
register description and the serial interface description, see the
FemtoClock NG Ceramic 5x7 Module Programming Guide.
The devices use the fractional feedback divider with a delta-sigma
modulator for noise shaping and robust frequency synthesis
capability. The relatively high reference frequency minimizes phase
noise generated by frequency multiplication and allows more efficient
shaping of noise by the delta-sigma modulator.
The output frequency is determined by the 2-bit pre-divider (P), the
feedback divider (M) and the 7-bit post divider (N). The feedback
divider (M) consists of both a 7-bit integer portion (MINT) and an
18-bit fractional portion (MFRAC) and provides the means for
high-resolution frequency generation. The output frequency fOUT is
calculated by:
1
MFRAC + 0.5
f
= f
------------ MINT + ------------------------------------- (1)
OUT
XTAL
P N
18
2
IDT8N0QV01HCD REVISION A MARCH 13, 2014
5
©2013 Integrated Device Technology, Inc.
