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HYS72V32200GR-8

型号:

HYS72V32200GR-8

描述:

X72 SDRAM模块\n[ x72 SDRAM Module ]

品牌:

ETC[ ETC ]

页数:

22 页

PDF大小:

220 K

HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
3.3 V 168-pin Registered SDRAM Modules  
64 MB, 128 MB, 256 MB, 512 MB & 1 GB Densities  
• 168-pin JEDEC Standard, Registered 8 Byte • Programmable CAS Latency, Burst Length,  
Dual-In-Line SDRAM Module  
for PC and Server main memory applications  
and Wrap Sequence (Sequential &  
Interleave)  
• One bank 8M × 72, 16M × 72, 32M × 72 and • Auto Refresh (CBR) and Self Refresh  
64M × 72 organization,  
• All inputs and outputs are LVTTL compatible  
two bank 128M × 72 organization  
• Serial Presence Detect with E2PROM  
• Optimized for ECC applications with very low  
input capacitances  
• Utilizes SDRAMs in TSOPII-54 packages  
with registers and PLL.  
• Programmed Latencies:  
The two bank module uses stacked TSOP54  
packages.  
Product Speed  
CL tRCD  
tRP  
2
• Card Size: 133.35 mm × 38.1 mm/  
43.18 mm × 4,00/6.50 mm with Gold contact  
pads  
-8  
PC100  
PC100  
2
3
2
2
-8A  
2
• Single + 3.3 V (± 0.3 V) power supply  
• This specification follows INTEL’s “PC  
SDRAM Registered DIMM Specification”  
Rev. 1.2  
• Performance:  
-8  
-8A  
PC100  
100  
10  
Unit  
PC100  
100  
10  
fCK  
tCK  
tAC  
Clock Frequency (max.)  
Clock Cycle Time (min.)  
Clock Access Time (min.)  
MHz  
ns  
6
6
ns  
The HYS 72Vx2x0GR family are industry standard 168-pin 8-byte Dual in-line Memory Modules  
(DIMMs) which are organized as 8M × 72, 16M × 72, 32M × 72, 64M × 72 & 128M × 72 high speed  
memory arrays designed with Synchronous DRAMs (SDRAMs) for ECC applications. The 32M x 72  
(256MByte) registered DIMM module is available in two versions (12 or 13 row addresses). All  
control and address signals are registered on-DIMM and the design incorporates a PLL circuit for  
the Clock inputs. Use of an on-board register reduces capacitive loading on the input signals but are  
delayed by one cycle in arriving at the SDRAM devices. Decoupling capacitors are mounted on the  
PC board. The DIMMs use a serial presence detects scheme implemented via a serial E2PROM  
using the 2-pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the  
second 128 bytes are available to the end user. All Infineon 168-pin DIMMs provide a high  
performance, flexible 8-byte interface in a 133.35 mm long footprint.  
Data Book  
1
3.00  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
Ordering Information  
Type  
Compliance  
Code  
Description  
SDRAM  
Technology  
HYS 72V8200GR-8  
HYS 72V16200GR-8  
HYS 72V16201GR-8  
HYS 72V32201GR-8  
HYS 72V32200GR-8  
PC100-222-622R one bank 64 MB Reg. DIMM  
64 MBit  
PC100-222-622R one bank 128 MB Reg. DIMM 64 MBit  
PC100-222-622R one bank 128 MB Reg. DIMM 128 MBit  
PC100-222-622R one bank 256 MB Reg. DIMM 128 MBit  
PC100-222-622R one bank 256 MB Reg. DIMM 256 MBit  
HYS 72V32200GR-8A PC100-322-622R  
HYS 72V64200GR-8  
PC100-222-622R one bank 512 MB Reg. DIMM 256 MBit  
HYS 72V64200GR-8A PC100-322-622R  
HYS 72V128220GR-8  
PC100-222-622R two bank 1 GByte Reg. DIMM 256 MBit (stacked)  
HYS 72V128220GR-8A PC100-322-622R  
Note: All part numbers end with a place code (not shown), designating the die revision. Consult  
factory for current revision. Example: HYS 64V8200GR-8-C, indicating Rev. C dies are used  
for SDRAM components.  
Data Book  
2
3.00  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
Pin Definitions and Functions  
A0 - A11, A12 Address Inputs  
DQMB0 - DQMB7 Data Mask  
BA0, BA1  
Bank Selects  
CS0 - CS3  
REGE  
Chip Select  
DQ0 - DQ63 Data Input/Output  
Register Enable  
Power (+ 3.3 V)  
Ground  
CB0 - CB7  
RAS  
Check Bits (x72 organization only) VDD  
Row Address Strobe  
Column Address Strobe  
Read/Write Input  
VSS  
SCL  
SDA  
N.C.  
CAS  
Clock for Presence Detect  
Serial Data Out  
No Connection  
WE  
CKE0  
Clock Enable  
CLK0 - CLK3 Clock Input  
Address Format  
Density Organization Memory SDRAMs # of  
# of row/bank/ Refresh Period Interval  
Banks  
SDRAMs columns bits  
64 MB 8M × 72  
128 MB 16M × 72  
128 MB 16M × 72  
256 MB 32M × 72  
256 MB 32M × 72  
512 MB 64M × 72  
1
1
1
1
1
1
2
8M × 8  
9
12/2/9  
4k  
4k  
4k  
4k  
8k  
8k  
8k  
64 ms 15.6 µs  
64 ms 15.6 µs  
64 ms 15.6 µs  
64 ms 15.6 µs  
64 ms 7.8 µs  
64 ms 7.8 µs  
64 ms 7.8 µs  
16M × 4  
16M x 8  
32M × 4  
32M × 8  
64M × 4  
64M × 4  
18  
9
12/2/10  
12/2/10  
12/2/11  
13/2/10  
13/2/11  
13/2/11  
18  
9
18  
36  
1 GB  
128M × 72  
Pin Configuration  
PIN# Symbol  
PIN# Symbol  
PIN# Symbol  
PIN# Symbol  
1
VSS  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
VSS  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
VSS  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
VSS  
2
DQ0  
DQ1  
DQ2  
DQ3  
VDD  
DU  
DQ32  
DQ33  
DQ34  
DQ35  
VDD  
CKE0  
CS3  
3
CS2  
DQMB2  
DQMB3  
DU  
4
DQMB6  
DQMB7  
N.C.  
5
6
7
DQ4  
DQ5  
DQ6  
DQ7  
DQ8  
VDD  
DQ36  
DQ37  
DQ38  
DQ39  
DQ40  
VDD  
8
N.C.  
N.C.  
CB2  
CB3  
N.C.  
9
N.C.  
10  
11  
CB6  
CB7  
Data Book  
3
3.00  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
Pin Configuration (cont’d)  
PIN# Symbol PIN# Symbol  
PIN# Symbol  
PIN# Symbol  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
VSS  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
VSS  
96  
VSS  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
157  
158  
159  
160  
161  
162  
163  
164  
165  
166  
167  
168  
VSS  
DQ9  
DQ10  
DQ11  
DQ12  
DQ13  
VDD  
DQ16  
DQ17  
DQ18  
DQ19  
VDD  
97  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
VDD  
DQ48  
DQ49  
DQ50  
DQ51  
VDD  
98  
99  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
DQ20  
N.C.  
DU  
DQ52  
N.C.  
DQ14  
DQ15  
CB0  
CB1  
VSS  
DQ46  
DQ47  
CB4  
CB5  
VSS  
DU  
N.C.  
VSS  
REGE  
VSS  
DQ21  
DQ22  
DQ23  
VSS  
DQ53  
DQ54  
DQ55  
VSS  
N.C.  
N.C.  
VDD  
N.C.  
N.C.  
VDD  
WE  
DQ24  
DQ25  
DQ26  
DQ27  
VDD  
CAS  
DQMB4  
DQMB5  
CS1  
RAS  
VSS  
DQ56  
DQ57  
DQ58  
DQ59  
VDD  
DQMB0  
DQMB1  
CS0  
DU  
VSS  
DQ28  
DQ29  
DQ30  
DQ31  
VSS  
DQ60  
DQ61  
DQ62  
DQ63  
VSS  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
CLK2  
N.C.  
WP  
A9  
CLK3  
N.C.  
A10 (AP)  
BA1  
VDD  
BA0  
A11  
SA0  
SDA  
SCL  
VDD  
SA1  
VDD  
CLK1  
A12  
SA2  
CLK0  
VDD  
VDD  
Data Book  
4
3.00  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
RCS0  
CS  
DQM  
DQ0-DQ7  
D0  
CS  
DQM  
RDQMB0  
DQ0-DQ7  
RDQMB4  
DQ32-DQ39  
DQ0-DQ7  
D4  
CS  
DQM  
DQ0-DQ7  
D1  
CS  
DQM  
DQ0-DQ7  
D5  
RDQMB1  
RDQMB5  
DQ8-DQ15  
DQ40-DQ47  
CS WE  
DQM  
DQ0-DQ7  
D8  
RCB0-RCB7  
RCS2  
CS  
DQM  
DQ0-DQ7  
D2  
CS  
DQM  
DQ0-DQ7  
D6  
RDQMB2  
RDQMB4  
DQ16-DQ23  
DQ48-DQ55  
CS  
DQM  
DQ0-DQ7  
D3  
CS  
DQM  
DQ0-DQ7  
D7  
RDQMB3  
RDQMB7  
DQ24-DQ31  
DQ56-DQ63  
E2PROM  
(256 word x 8 Bit)  
VCC  
VSS  
D0-D8, Reg., DLL  
D0-D8, Reg., DLL  
SA0  
SA1  
SA2  
SCL  
SA0  
SA1 SDA  
C
SA2  
SCL  
WP  
47 k  
CLK0  
12 pF  
PLL  
SDRAMs D0-D8  
Notes:  
1) DQ wirding may differ from that  
decribed in this drawing;  
however DQ/DQB relationship  
must be maintained as shown  
2) All resistors are 10 unless  
otherwise noted  
CS0/CS2  
DQMB0-7  
BA0, BA1  
A0-A11,12*)  
RAS  
CAS  
CKE0  
RCS0/RCS2  
RDQMB0-7  
RBA0, RBA1  
RA0-11,12  
RRAS  
SDRAMs D0-D8  
SDRAMs D0-D8  
SDRAMs D0-D8  
SDRAMs D0-D8  
SDRAMs D0-D8  
SDRAMs D0-D8  
RCAS  
*) A12 is only for 32 M x 72  
organisation  
RCKE0  
WE  
RWE  
CLK1, CLK2, CLK3  
12 pF  
REGE  
10 kΩ  
VCC  
SPB04130  
Block Diagram: One Bank 8M × 72, 16M x 72 & 32M × 72 SDRAM DIMM Modules  
HYS 72V8200GR, HYS72V16201GR and HYS 72V32200GR Using x8 Organized SDRAMs  
Data Book  
5
3.00  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
RCS0  
RD
RDQMB4  
DQM  
DQ0-DQ3  
DQM  
DQ0-DQ3  
CS  
CS  
DQ0-DQ3  
DQ4-DQ7  
DQ32-DQ35  
D0  
D8  
DQM  
CS  
DQM  
CS  
DQ36-DQ39  
DQ0-DQ3  
DQ0-DQ3  
D1  
D9  
RDQMB1  
RDQMB5  
DQM  
CS  
DQM  
CS  
DQ8-DQ11  
DQ40-DQ43  
DQ0-DQ3  
DQ0-DQ3  
D2  
D10  
DQM  
DQ0-DQ3  
DQM  
DQ0-DQ3  
CS  
CS  
DQ12-DQ15  
CB0-CB3  
DQ44-DQ47  
CB4-CB7  
D3  
D11  
DQM  
CS  
DQM  
CS  
DQ0-DQ3  
D17  
DQ0-DQ3  
D16  
RCS2  
RDQMB2  
RDQMB6  
CS  
DQ0-DQ3  
CS  
DQ0-DQ3  
D12  
DQM  
DQM  
DQ16-DQ19  
DQ20-DQ23  
DQ48-DQ51  
D4  
DQM  
DQ0-DQ3  
CS  
DQM  
DQ0-DQ3  
D13  
CS  
DQ52-DQ55  
D5  
RDQMB3  
RDQMB7  
DQM  
DQ0-DQ3  
CS  
DQM  
DQ0-DQ3  
D14  
CS  
DQ24-DQ27  
DQ56-DQ59  
D6  
CS  
DQ0-DQ3  
CS  
DQ0-DQ3  
D15  
DQM  
DQM  
DQ28-DQ31  
DQ60-DQ63  
D7  
E2PROM  
(256 word x 8 Bit)  
CLK0  
12 pF  
PLL  
SDRAMs D0-D17  
CLK1, CLK2, CLK3  
SA0  
SA1  
SA2  
SCL  
SA0  
SA1 SDA  
SA2  
SCL  
12 pF  
CS0/CS2  
DQMB0-7  
BA0, BA1  
A0-A11, A12* )  
RAS  
CAS  
CKE0  
WE  
RCS0/RCS2  
WP  
RDQMB0-7  
RBA0, RBA1  
RA0-RA11  
RRAS  
RCAS  
RCKE0  
SDRAMs D0-D17  
47 k  
SDRAMs D0-D17  
SDRAMs D0-D17  
SDRAMs D0-D17  
SDRAMs D0-D17  
SDRAMs D0-D17  
VCC  
VSS  
D0-D17, Reg., DLL  
D0-D17, Reg., DLL  
C
RWE  
REGE  
1) DQ wirding may differ from that decribed  
in this drawing; however DQ/DQB relationship  
must be maintained as shown  
*) A12 is only used for  
128 M x 72 organisation  
10 kΩ  
VCC  
2) All resistors are 10 unless otherwise noted  
SPB04131  
Block Diagram: One Bank 16M × 72 & 64M × 72 SDRAM DIMM Modules  
HYS 72V16200GR, HYS72V32201 and HYS 72V64200GR Using x4 Organized SDRAMs  
Data Book  
6
3.00  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
RCS0  
RCS1  
RDQMB0  
RDQMB4  
DQM  
CS DQM  
CS  
DQM  
CS DQM  
CS  
DQ0-DQ3  
DQ4-DQ7  
DQ32-DQ35  
DQ0-DQ3  
DQ0-DQ3  
DQ0-DQ3  
DQ0-DQ3  
D0  
D1  
D0  
CS  
D8  
D9  
D8  
CS  
CS  
CS  
DQM  
DQM  
DQ0-DQ3  
DQM  
DQM  
DQ0-DQ3  
DQ36-DQ39  
DQ0-DQ3  
DQ0-DQ3  
D1  
D9  
RDQMB1  
RDQMB5  
CS  
CS  
CS  
CS  
DQM  
DQM  
DQM  
DQM  
DQ8-DQ11  
DQ40-DQ43  
DQ0-DQ3  
DQ0-DQ3  
DQ0-DQ3  
DQ0-DQ3  
D2  
D2  
D10  
D10  
DQM  
CS DQM  
CS  
DQM  
CS DQM  
CS  
DQ12-DQ15  
CB0-CB3  
DQ44-DQ47  
CB4-CB7  
DQ0-DQ3  
DQ0-DQ3  
DQ0-DQ3  
DQ0-DQ3  
D3  
CS  
D3  
CS  
D11  
D11  
CS  
DQ0-DQ3  
D17  
CS  
DQM  
DQM  
DQM  
DQM  
DQ0-DQ3  
DQ0-DQ3  
DQ0-DQ3  
D16  
D16  
D17  
RCS2  
RCS3  
RDQMB2  
RDQMB6  
DQM  
DQ0-DQ3  
DQM  
DQ0-DQ3  
DQM  
DQ0-DQ3  
D12  
CS DQM  
CS  
CS  
CS  
DQ16-DQ19  
DQ48-DQ51  
DQ0-DQ3  
D4  
D4  
D12  
DQM  
DQ0-DQ3  
CS DQM  
DQ0-DQ3  
CS  
DQM  
DQ0-DQ3  
D13  
CS DQM  
CS  
DQ20-DQ23  
DQ52-DQ55  
DQ0-DQ3  
D5  
D5  
D13  
RDQMB3  
RDQMB7  
DQM  
DQ0-DQ3  
CS DQM  
DQ0-DQ3  
CS  
DQM  
DQ0-DQ3  
D14  
CS DQM  
CS  
DQ24-DQ27  
DQ56-DQ59  
DQ0-DQ3  
D6  
D6  
D7  
D14  
DQM  
DQ0-DQ3  
DQM  
DQ0-DQ3  
DQM  
DQ0-DQ3  
D15  
CS DQM  
CS  
CS  
CS  
DQ28-DQ31  
DQ61-DQ63  
DQ0-DQ3  
D7  
D15  
E2PROM  
(256 word x 8 Bit)  
CLK0  
12 pF  
PLL  
Stacked SDRAMs D0-D17  
CLK1, CLK2, CLK3  
SA0  
SA1  
SA2  
SCL  
SA0  
SA1 SDA  
SA2  
SCL  
12 pF  
CS0-CS3  
DQMB0-7  
BA0, BA1  
A0-A11, A12* )  
RAS  
CAS  
CKE0  
WE  
RCS0-RCS3  
WP  
RDQMB0-7  
RBA0, RBA1  
RA0-RA11  
RRAS  
RCAS  
RCKE0  
Stacked SDRAMs D0-D17  
Stacked SDRAMs D0-D17  
Stacked SDRAMs D0-D17  
Stacked SDRAMs D0-D17  
Stacked SDRAMs D0-D17  
Stacked SDRAMs D0-D17  
47 kΩ  
VCC  
VSS  
D0-D17, Reg. DLL  
D0-D17, Reg. DLL  
C
RWE  
REGE  
1.) DQ wirding may differ from that decribed  
in this drawing; however DQ/DQB relationship  
must be maintained as shown  
*) A12 is only used for  
128 M x 72 organisation  
10 kΩ  
VCC  
2.) All resistors are 10 unless otherwise noted  
SPB04132  
Block Diagram: Two Bank 128M × 72 SDRAM DIMM Modules  
HYS 72V128220GR Using Stacked x4 Organized SDRAMs  
Data Book  
7
3.00  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
DC Characteristics  
TA = 0 to 70 °C 1); VSS = 0 V; VDD,VDDQ = 3.3 V ± 0.3 V  
Parameter  
Symbol  
Limit Values  
max.  
Unit  
min.  
2.0  
Input High Voltage  
VIH  
VIL  
VDD + 0.3  
V
Input Low Voltage  
– 0.5  
2.4  
0.8  
V
Output High Voltage (IOUT = – 4.0 mA)  
Output Low Voltage (IOUT = 4.0 mA)  
VOH  
VOL  
II(L)  
V
0.4  
10  
V
Input Leakage Current, any input  
– 10  
µA  
(0 V < VIN < 3.6 V, all other inputs = 0 V)  
Output Leakage Current  
IO(L)  
– 10  
10  
µA  
(DQ is disabled, 0 V < VOUT < VDD)  
Capacitance  
TA = 0 to 70 °C 1); VDD = 3.3 V ± 0.3 V, f = 1 MHz  
Parameter  
Symbol  
Limit Values  
Unit  
One Bank  
Modules  
Two Bank  
Modules  
Input Capacitance  
CIN  
10  
20  
pF  
(all inputs except CLK and CKE)  
Input Capacitance (CLK)  
Input Capacitance (CKE)  
CCLK  
CCKE  
CIO  
30  
17  
10  
30  
30  
17  
pF  
pF  
pF  
Input/Output Capacitance  
(DQ0 - DQ63, CB0 - CB7)  
Input Capacitance (SCL, SA0 - 2)  
Input/Output Capacitance (SDA)  
CSC  
CSD  
8
8
8
8
pF  
pF  
Data Book  
8
3.00  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
Operating Currents per SDRAM component  
TA = 0 to 70 °C 1), VDD = 3.3 V ± 0.3 V  
(Recommended Operating Conditions unless otherwise noted)  
Test  
Condition  
Symbol 64Mb  
max.  
128Mb  
max.  
150  
256Mb  
max.  
210  
Unit  
Note  
Parameter  
2)  
Operating current  
ICC1  
110  
tRC = tRC(MIN.), tCK = tCK(MIN.)  
Outputs open, Burst  
mA  
Length = 4, CL = 3. All banks  
operated in random access,  
all banks operated in ping-  
pong manner to maximize  
gapless data access  
2)  
Precharge stand-by current  
in Power Down Mode  
tCK = min. ICC2P  
2
2
2
mA  
CS = VIH(MIN.), CKE VIL(MAX.)  
2)  
No operating current  
CKE ≥  
VIH(MIN.)  
ICC3N  
ICC3P  
ICC4  
45  
8
45  
10  
90  
45  
mA  
mA  
tCK = min., CS = VIH(MIN.),  
2)  
CKE ≤  
VIL(MAX.)  
10  
active state (max. 4 banks)  
2), 3)  
Burst operating current  
70  
120  
tCK = min.,  
mA  
mA  
Read command cycling  
2)  
2)  
Auto refresh current  
ICC5  
130  
1
210  
1.5  
240  
2.5  
tCK = min.,  
Auto Refresh command cycling  
Self refresh current  
Self Refresh Mode,  
CKE = 0.2 V  
ICC6  
mA  
Data Book  
9
3.00  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
4), 5)  
AC Characteristics (SDRAM Device Specification)  
TA = 0 to 70 °C 1); VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns  
Parameter  
Symbol  
Limit Values  
Unit Note  
-8  
PC100-222  
-8A  
PC100-322  
min.  
max. min.  
max.  
Clock and Access times  
Clock Cycle Time  
CAS Latency = 3  
CAS Latency = 2  
tCK  
fCK  
tAC  
10  
10  
10  
15  
ns  
ns  
Clock Frequency  
CAS Latency = 3  
CAS Latency = 2  
100  
100  
100  
66  
MHz  
MHz  
Access Time from Clock  
CAS Latency = 3  
6
6
6
6
ns  
ns  
CAS Latency = 2  
Clock High Pulse Width  
Clock Low Pulse Width  
Transition Time  
tCH  
tCL  
tT  
3
3
ns  
ns  
ns  
3
3
0.5  
10  
0.5  
10  
Setup and Hold Parameters  
Input Setup Time  
tIS  
2
2
ns  
Input Hold Time  
tIH  
1
1
ns  
Power Down Mode Entry Time  
Power Down Mode Exit Setup Time  
Mode Register Set-up Time  
Transition Time  
tSB  
tPDE  
tRSC  
tT  
1
1
CLK  
CLK  
CLK  
ns  
1
1
2
2
0.5  
10  
0.5  
10  
Common Parameters  
Row to Column Delay Time  
Row Precharge Time  
Row Active Time  
tRCD  
tRP  
tRAS  
tRC  
20  
20  
45  
70  
2
20  
20  
ns  
ns  
100k 60  
100k ns  
Row Cycle Time  
70  
2
ns  
Activate (a) to Activate (b) Command  
Period  
tRRD  
CLK  
CAS(a) to CAS(b) Command Period  
tCCD  
1
1
CLK  
Data Book  
10  
3.00  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
AC Characteristics (SDRAM Device Specification) (cont’d) 4), 5)  
TA = 0 to 70 °C 1); VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns  
Parameter  
Symbol  
Limit Values  
Unit Note  
-8  
PC100-222  
-8A  
PC100-322  
min.  
max. min.  
max.  
Refresh Cycle  
Refresh Period  
tREF  
1
64  
1
64  
ms  
6)  
Self Refresh Exit Time  
tSREX  
CLK  
Read Cycle  
Data Out Hold Time  
tOH  
tLZ  
3
0
3
8
2
3
0
3
8
2
ns  
7)  
Data Out to Low Impedance  
Data Out to High Impedance  
DQM Data Out Disable Latency  
ns  
7)  
tHZ  
ns  
tDQZ  
CLK  
Write Cycle  
Data Input to Precharge  
(write recovery)  
tWR  
2
0
2
0
CLK  
CLK  
DQM Write Mask Latency  
tDQW  
Data Book  
11  
3.00  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
Clock Frequency and Latency (Registered DIMM Module Specification) 8)  
Parameter  
Symbol -8  
max. tCK 100  
10  
-8A  
100  
10  
4
Unit Notes  
Clock Frequency  
MHz  
ns  
Clock Cycle Time  
min.  
min.  
min.  
min.  
min.  
min.  
min.  
min.  
min.  
tCK  
9)  
CAS Latency  
tAA  
3
2
6
2
2
5
2
1
1
1
1
1
CLK  
CLK  
CLK  
CLK  
CLK  
CLK  
CLK  
CLK  
CLK  
CLK  
CLK  
CLK  
RAS to CAS Delay  
RAS Latency  
tRCD  
tRL  
2
9)  
7
Precharge Time  
tRP  
2
Data In to Precharge  
Data In to Active/Refresh  
Bank to Bank Delay Time  
CAS to CAS Delay Time  
Write Latency  
tDPL  
tDAL  
tRRD  
tCCD  
2
5
2
1
9)  
fixed tWL  
fixed tDQW  
fixed tDQZ  
fixed tCSL  
1
DQM Write Mask Latency  
DQM Data Disable Latency  
Clock Suspend Latency  
1
1
9)  
1
Data Book  
12  
3.00  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
Notes  
1. The registered DIMM modules are designed to operate under system operating conditions  
between 0-55 deg C ambient, 500 MB/sec sustained bandwidth and 0 LFM airflow.  
2. These parameters depend on the cycle rate. All values are measured at 100 MHz operation  
frequency. Input signals are changed once during tck excepts for Icc6 and for standby currents  
when tck = infinity.  
3. These parameters are measured with continous data stream during read access and all DQ  
toggling. CL=3 and BL=4 is assumed and the Vcc current is excluded.  
4. An initial pause of 100 µs is required after power-up. Then a Precharge All Banks command must  
be given followed by eight Auto Refresh (CBR) cycles before the Mode Register Set Operation  
can begin. Also the on-DIMM PLL must be given enough clock cycles to stabilize before any  
operation can be guaranteed.  
5. AC timing tests have VIL = 0.8 V and VIH = 2.0 V with the timing referenced to the 1.4 V crossover  
point. The transition time is measured between VIH and VIL. All AC measurements assume  
tT = 1 ns with the AC output load circuit shown. Specified tAC and tOH parameters are measured  
with a 50 pF only, without any resistive termination and with a input signal of 1 V/ns edge rate  
between 0.8 V and 2.0 V.  
6. Self Refresh Exit is a synchronous operation and begins on the second positive clock edge after  
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied  
after the Self Refresh Exit command is registered.  
7. Referenced to the time at which the output achieves the open circuit condition, not to output  
voltage levels.  
8. Due to the usage of a register device on all input and address signals, all external command  
cycle are delayed by one clock (Reg-DIMM Latency = 1) on the module board.  
9. Delayed by one clock cycle due to the use of the register device.  
tCH  
2.4 V  
0.4 V  
CLOCK  
tT  
tCL  
tHOLD  
tSETUP  
INPUT  
1.4 V  
tAC  
tAC  
I/O  
tLZ  
tOH  
50 pF  
OUTPUT  
1.4 V  
Measurement conditions for  
AC and tOH  
tHZ  
t
SPT03404  
A serial presence detect storage device - E2PROM 34C02 - is assembled onto the module.  
Information about the module configuration, speed, etc. is written into the E2PROM device during  
module production using a serial presence detect protocol (I2C synchronous 2-wire bus)  
Data Book  
13  
3.00  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
SPD-Table for -8 Registered DIMM Modules with PLL  
Byte# Description  
SPD Entry  
Value  
Hex  
0
1
2
3
Number of SPD Bytes  
128  
80  
08  
04  
0C  
Total Bytes in Serial PD 256  
Memory Type  
Number of Row  
Addresses (without BS  
bits)  
SDRAM  
12/13  
0C  
0C  
0C  
0D  
0D  
0D  
4
Number of Column  
Addresses  
9/10/11  
09  
01  
0A  
01  
0A  
01  
0B  
0A  
01  
0B  
01  
0B  
02  
5
6
7
Number of DIMM Banks  
Module Data Width  
Module Data Width  
(cont’d)  
1
01  
48  
00  
72  
0
8
Module Interface Levels LVTTL  
Cycle Time at CL = 3 10.0 ns  
01  
A0  
60  
9
10  
Access Time from Clock 6.0 ns  
at CL = 3  
11  
12  
DIMM Config (Error Det/ ECC  
Corr.)  
02  
80  
Refresh Rate/Type  
Self-Refresh,  
15.6/7.8 µs  
80  
80  
80  
82  
82  
82  
13  
14  
SDRAM Width, Primary x4, x8  
Error Checking SDRAM n/a/x4  
Data Width  
08  
08  
04  
04  
08  
08  
04  
04  
08  
08  
04  
04  
04  
04  
15  
16  
Minimum tCCD  
Burst Length Supported 1, 2, 4, 8 &  
(full page)  
1 CLK  
01  
0F  
8F  
8F  
0F  
0F  
0F  
0F  
17  
18  
Number of SDRAM  
Banks  
4
04  
06  
SDRAM Supported CAS 2 & 3  
Latencies  
19  
20  
21  
SDRAM CS Latencies  
SDRAM WE Latencies  
SDRAM DIMM Module  
Attributes  
0
01  
01  
16  
0
with PLL  
22  
SDRAM Device  
Attributes  
V
10%  
DD tol +/–  
0E  
Data Book  
14  
3.00  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
SPD-Table for -8 Registered DIMM Modules with PLL (cont’d)  
Byte# Description  
SPD Entry  
Value  
Hex  
23  
24  
25  
26  
Min. Clock Cycle Time at 10 ns  
CL = 2  
A0  
60  
FF  
FF  
Max. Data Access Time 6 ns  
from Clock for CL = 2  
Min. Clock Cycle Time at not supp.  
CL = 1  
Max. Data Access Time not supp.  
from Clock at CL = 1  
27  
28  
29  
30  
31  
SDRAM Minimum tRP  
SDRAM Minimum tRRD  
SDRAM Minimum tRCD  
SDRAM Minimum tRAS  
Module Bank Density  
(per bank)  
20 ns  
16 ns  
14  
10  
14  
2D  
40  
20 ns  
45 ns  
64/128/256/  
512 MByte  
2 ns  
10  
20  
20  
40  
80  
80  
32  
SDRAM Input Setup  
Time  
20  
33  
34  
SDRAM Input Hold Time 1 ns  
10  
20  
SDRAM Data Input  
Setup Time  
2 ns  
35  
SDRAM Data Input Hold 1 ns  
Time  
10  
36-61 Superset Information  
(may be used in future)  
FF  
62  
63  
SPD Revision  
Checksum for Bytes  
0 - 62  
1.2  
12  
08  
11  
99  
BA  
BC  
F5  
F6  
64-125 Manufacturer’s  
Information  
XX  
126  
Frequency Specification 100 MHz  
64  
8F  
FF  
127  
Details of Clocks  
Unused Storage  
Locations  
128+  
1) HYS72V16200GR-8, 2) HYS72V16201GR-8, *) HYS72V32201GR, **) HYS72V32200GR  
Data Book  
15  
3.00  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
SPD-Table for -8A Registered DIMM Modules with PLL  
Byte# Description  
SPD Entry  
Value  
Hex  
0
1
2
3
Number of SPD Bytes  
128  
80  
08  
04  
0D  
80  
80  
08  
04  
0D  
Total Bytes in Serial PD  
Memory Type  
256  
08  
04  
0D  
SDRAM  
13  
Number of Row Addresses (without  
BS bits)  
4
Number of Column Addresses  
Number of DIMM Banks  
Module Data Width  
10/11  
0A  
01  
48  
00  
01  
A0  
60  
02  
82  
0B  
01  
48  
00  
01  
A0  
60  
02  
82  
0B  
02  
48  
00  
01  
A0  
60  
02  
82  
5
1
6
72  
0
7
Module Data Width (cont’d)  
Module Interface Levels  
Cycle Time at CL = 3  
8
LVTTL  
10.0 ns  
6.0 ns  
ECC  
9
10  
11  
12  
Access Time from Clock at CL = 3  
DIMM Config (Error Det/Corr.)  
Refresh Rate/Type  
Self-  
Refresh,  
7.8 µs  
x4, x8  
n/a/x4  
1 CLK  
13  
14  
15  
16  
SDRAM Width, Primary  
Error Checking SDRAM Data Width  
Minimum tCCD  
08  
08  
01  
04  
04  
01  
0F  
04  
04  
01  
0F  
Burst Length Supported  
1, 2, 4, 8 & 0F  
(full page)  
17  
18  
19  
20  
21  
22  
Number of SDRAM Banks  
SDRAM Supported CAS Latencies  
SDRAM CS Latencies  
4
04  
06  
01  
01  
16  
04  
06  
01  
01  
16  
0E  
04  
06  
01  
01  
16  
0E  
2 & 3  
0
SDRAM WE Latencies  
0
SDRAM DIMM Module Attributes  
SDRAM Device Attributes  
with PLL  
V
DD tol +/– 0E  
10%  
23  
24  
Min. Clock Cycle Time at CL = 2  
15 ns  
F0  
60  
F0  
60  
F0  
60  
Max. Data Access Time from Clock for 6 ns  
CL = 2  
25  
26  
Min. Clock Cycle Time at CL = 1  
Max. Data Access Time from Clock at not supp.  
CL = 1  
not supp.  
FF  
FF  
FF  
FF  
FF  
FF  
27  
SDRAM Minimum tRP  
20 ns  
14  
14  
14  
Data Book  
16  
3.00  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
SPD-Table for -8A Registered DIMM Modules with PLL (cont’d)  
Byte# Description  
SPD Entry  
Value  
Hex  
28  
29  
30  
31  
SDRAM Minimum tRRD  
SDRAM Minimum tRCD  
SDRAM Minimum tRAS  
Module Bank Density (per bank)  
20 ns  
20 ns  
60 ns  
256/512  
MByte  
2 ns  
14  
14  
3C  
40  
14  
14  
14  
3C  
80  
14  
3C  
80  
32  
33  
34  
35  
SDRAM Input Setup Time  
SDRAM Input Hold Time  
20  
10  
20  
10  
FF  
20  
10  
20  
10  
FF  
20  
10  
20  
10  
FF  
1 ns  
SDRAM Data Input Setup Time  
SDRAM Data Input Hold Time  
2 ns  
1 ns  
36-61 Superset Information (may be used in –  
future)  
62  
63  
SPD Revision  
1.2  
12  
1F  
12  
58  
12  
59  
Checksum for Bytes  
0 - 62  
63  
Manufacturer’s Information  
XX  
64  
XX  
64  
XX  
64  
64-125 Frequency Specification  
100 MHz  
127  
Details of Clocks  
for HYS72VxxxxxGR-8A-A  
8F  
8D  
FF  
8F  
8D  
FF  
8F  
8D  
FF  
Details of Clocks  
for HYS72VxxxxxGR-8A-B  
and HYS72VxxxxxGR-8A-C  
128+  
Unused Storage Locations  
*) HYS72V32201GR **) HYS72V32200GR  
Data Book  
17  
3.00  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
Package Outlines  
Module Package  
JEDEC MO-161  
64 & 256 MByte Registered Module  
133.35  
127.35  
4
Register  
Register  
1
10  
11  
6.35  
40  
41  
6.35  
84  
1.27±  
0.1  
3
1.27  
42.18  
66.68  
2
85 94  
95  
124 125  
168  
PLL  
Detail of Contacts  
1+0.5  
1.27  
GLD09186  
Data Book  
18  
3.00  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
Module Package  
JEDEC MO-161  
128 & 512 MByte Registered Module  
133.35  
127.35  
4
PLL  
1
10  
11  
6.35  
40  
41  
6.35  
84  
1.27±  
0.1  
3
1.27  
42.18  
66.68  
2
85 94  
95  
124 125  
Register  
168  
Register  
Detail of Contacts  
1+0.5  
1.27  
GLD09185  
Data Book  
19  
3.00  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
Module Package  
JEDEC MO-161  
256 MByte & 1 GByte Registered DIMM Module with Stacked SDRAMs  
133.35  
127.35  
8 max.  
PLL  
1
10  
11  
6.35  
40  
41  
6.35  
84  
1.27±  
0.1  
3
1.27  
42.18  
66.68  
2
85 94  
95  
124 125  
Register  
168  
Register  
Detail of Contacts  
GLD09190  
1+0.5  
1.27  
Data Book  
20  
3.00  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
Functional Description  
All 168-pin Registered DIMMs conform to a compatible set of timing and operation characteristics  
intended to comply with the 100 MHz standards. The Registered DIMMs achieve high speed data  
transfer rate up to 100 MHz.  
All control and address signals are synchronized with the positive edge of externally supplied clocks  
and are registered on-DIMM and hence delayed by one clock cycle in arriving at the SDRAM  
devices. The use of the on-board register reduces the capacitive loading of the DIMM on input  
control and address signals. The SDRAM device data lines (DQ) are connected directly to the DIMM  
tabs through 10 Ohm series resistors. All the following timing diagrams and explanations show  
DIMM operation at the tabs, not SDRAM operation.  
The picture below depicts an overview of the effect of the Registered Mode on the data outputs  
(DQs) for a Read operation. Without the registers, the data is delayed according to the device CAS  
latency, in the case two clocks. With the register, the data is delayed according to the device CAS  
latency plus an additional clock cycle. This is know as the DIMM CAS latency, and in this example  
is four three. The data path can be thought of as a pipeline in which the register effectively lengthens  
the pipe by one clock cycle.  
Registered DIMM Burst Read Operation (BL = 4)  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
CLK  
Command  
Read A  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
Device  
CAS latency = 2  
DOUT A0 DOUT A1 DOUT A2 DOUT A3  
t
CK2, DQ’s  
DIMM  
CAS latency = 3  
DOUT A0 DOUT A1 DOUT A2 DOUT A3  
Added for on-DIMM pipeline register  
t
CK3, DQ’s  
One Clock  
Reg-DIMM Latency = 1  
SPT03968  
In case of a Burst Write Command the data-in is delayed one clock due the op-DIMM pipeline  
register also. Therefore, data for the first Burst Write cycle must be applied on the DQ pins on the  
next clock cycle after the Write command is issued. the remaining data inputs must be supplied on  
each subsequent rising clock edge until the burst length is completed. When the burst has finished,  
any additional data supplied to the DQ pins will be ignored.  
Data Book  
21  
3.00  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
CLK  
Command  
DQ’s  
NOP  
Write A  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
don’t care  
DIN A0  
DIN A1  
DIN A2  
DIN A3  
The first data element and the Write  
are registered on the next clock edge  
Reg-DIMM Latency = 1 CLK  
Extra data is ignored after  
termination of a Burst.  
SPT03969  
Registered DIMM Burst Write Operation (BL = 4)  
Data Book  
22  
3.00  
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HYS64D128021 200针的小型双列直插式内存模块[ 200-Pin Small Outline Dual-In-Line Memory Modules ] 23 页

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