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HYS72V16200GR-8-E

型号:

HYS72V16200GR-8-E

品牌:

ETC[ ETC ]

页数:

22 页

PDF大小:

312 K

HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
3.3 V 168-pin Registered PC100 SDRAM Modules  
64 MB, 128 MB, 256 MB, 512 MB & 1 GB Densities  
168-pin JEDEC Standard, Registered 8 Byte  
Dual-In-Line SDRAM Module  
for PC and Server main memory applications  
Auto Refresh (CBR) and Self Refresh  
All inputs and outputs are LVTTL compatible  
Serial Presence Detect with E2PROM  
One bank 8M × 72, 16M × 72, 32M × 72 and  
64M × 72 organization,  
two bank 128M × 72 organization  
Utilizes SDRAMs in TSOPII-54 packages  
with registers and PLL.  
The two bank module uses stacked TSOP54  
packages.  
Optimized for ECC applications with very low  
input capacitances  
Card Size: 133.35 mm × 38.1 mm/43.18 mm  
with Gold contact pads (JEDEC MO-161)  
Programmed Latencies:  
Product Speed  
-8 PC100  
Single + 3.3 V (± 0.3 V) power supply  
CL tRCD  
tRP  
This specification follows INTEL’s “PC  
SDRAM Registered DIMM Specification”  
Rev. 1.2  
2
2
2
Programmable CAS Latency, Burst Length,  
and Wrap Sequence (Sequential &  
Interleave)  
Performance:  
-8  
Unit  
PC100  
100  
10  
fCK  
tCK  
tAC  
Clock Frequency (max.)  
Clock Cycle Time (min.)  
Clock Access Time (min.)  
MHz  
ns  
6
ns  
The HYS 72Vx2x0GR family are industry standard 168-pin 8-byte Dual in-line Memory Modules  
(DIMMs) which are organized as 8M × 72, 16M × 72, 32M × 72, 64M × 72 & 128M × 72 high speed  
memory arrays designed with Synchronous DRAMs (SDRAMs) for ECC applications. The 32M x 72  
(256MByte) registered DIMM module is available in two versions (12 or 13 row addresses). All  
control and address signals are registered on-DIMM and the design incorporates a PLL circuit for  
the Clock inputs. Use of an on-board register reduces capacitive loading on the input signals but are  
delayed by one cycle in arriving at the SDRAM devices. Decoupling capacitors are mounted on the  
PC board. The DIMMs use a serial presence detects scheme implemented via a serial E2PROM  
using the 2-pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the  
second 128 bytes are available to the end user. All Infineon 168-pin DIMMs provide a high  
performance, flexible 8-byte interface in a 133.35 mm long footprint.  
INFINEON Technologies  
1
9.01  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
Ordering Information  
Type  
Compliance  
Code  
Description  
SDRAM  
Technology  
HYS 72V8200GR-8-C  
HYS 72V8200GR-8-E  
PC100-222-622R one bank 64 MB Reg. DIMM  
64 MBit (x8)  
HYS 72V16200GR-8-C  
HYS 72V16200GR-8-E  
PC100-222-622R one bank 128 MB Reg. DIMM 64 MBit (x4)  
HYS 72V16201GR-8-C2 PC100-222-622R one bank 128 MB Reg. DIMM 128 MBit (x8)  
HYS 72V32201GR-8-C2 PC100-222-622R one bank 256 MB Reg. DIMM 128 MBit (x4)  
HYS 72V32200GR-8-C2 PC100-222-622R one bank 256 MB Reg. DIMM 256 MBit (x8)  
HYS 72V64200GR-8-C2 PC100-222-622R one bank 512 MB Reg. DIMM 256 MBit (x4)  
HYS 72V128220GR-8-C2 PC100-222-622R two bank 1 GByte Reg. DIMM 256 MBit  
(x4 stacked)  
Note: All part numbers end with a place code (not shown), designating the die revision. Consult  
factory for current revision. Example: HYS 64V8200GR-8-C2, indicating Rev. C2 dies are  
used for SDRAM components.  
INFINEON Technologies  
2
9.01  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
Pin Definitions and Functions  
A0 - A11, A12 Address Inputs  
DQMB0 - DQMB7 Data Mask  
BA0, BA1  
Bank Selects  
CS0 - CS3  
REGE *)  
Chip Select  
DQ0 - DQ63 Data Input/Output  
Register Enable  
Hor N.C = registered mode  
L= buffered mode  
CB0 - CB7  
RAS  
Check Bits (x72 organization only) VDD  
Power (+ 3.3 V)  
Ground  
Row Address Strobe  
Column Address Strobe  
Read/Write Input  
VSS  
SCL  
SDA  
N.C.  
CAS  
Clock for Presence Detect  
Serial Data Out  
No Connection  
WE  
CKE0  
Clock Enable  
CLK0 - CLK3 Clock Input  
*) note : To confirm to this specification, motherboards must pull this pin to high state or no connect.  
Address Format  
Density Organization Memory SDRAMs # of  
# of row/bank/ Refresh Period Interval  
Banks  
SDRAMs columns bits  
64 MB 8M × 72  
128 MB 16M × 72  
128 MB 16M × 72  
256 MB 32M × 72  
256 MB 32M × 72  
512 MB 64M × 72  
1
1
1
1
1
1
2
8M × 8  
9
12/2/9  
4k  
4k  
4k  
4k  
8k  
8k  
8k  
64 ms 15.6 µs  
64 ms 15.6 µs  
64 ms 15.6 µs  
64 ms 15.6 µs  
64 ms 7.8 µs  
64 ms 7.8 µs  
64 ms 7.8 µs  
16M × 4  
16M x 8  
32M × 4  
32M × 8  
64M × 4  
64M × 4  
18  
9
12/2/10  
12/2/10  
12/2/11  
13/2/10  
13/2/11  
13/2/11  
18  
9
18  
36  
1 GB  
128M × 72  
Pin Configuration  
PIN# Symbol  
PIN# Symbol  
PIN# Symbol  
PIN# Symbol  
1
2
3
4
5
6
7
8
9
VSS  
43  
44  
45  
46  
47  
48  
49  
50  
51  
VSS  
85  
86  
87  
88  
89  
90  
91  
92  
93  
VSS  
127  
128  
129  
130  
131  
132  
133  
134  
135  
VSS  
DQ0  
DQ1  
DQ2  
DQ3  
VDD  
DU  
DQ32  
DQ33  
DQ34  
DQ35  
VDD  
CKE0  
CS3  
CS2  
DQMB2  
DQMB3  
DU  
DQMB6  
DQMB7  
N.C.  
DQ4  
DQ5  
DQ6  
VDD  
DQ36  
DQ37  
DQ38  
VDD  
N.C.  
N.C.  
N.C.  
N.C.  
INFINEON Technologies  
3
9.01  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
Pin Configuration (contd)  
PIN# Symbol PIN# Symbol  
PIN# Symbol  
PIN# Symbol  
10  
DQ7  
DQ8  
VSS  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
CB2  
94  
DQ39  
DQ40  
VSS  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
157  
158  
159  
160  
161  
162  
163  
164  
165  
166  
167  
168  
CB6  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
CB3  
95  
CB7  
VSS  
96  
VSS  
DQ9  
DQ10  
DQ11  
DQ12  
DQ13  
VDD  
DQ16  
DQ17  
DQ18  
DQ19  
VDD  
97  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
VDD  
DQ48  
DQ49  
DQ50  
DQ51  
VDD  
98  
99  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
DQ20  
N.C.  
DQ52  
N.C.  
DQ14  
DQ15  
CB0  
CB1  
VSS  
DQ46  
DQ47  
CB4  
CB5  
VSS  
DU  
DU  
N.C.  
REGE  
VSS  
VSS  
DQ21  
DQ22  
DQ23  
VSS  
DQ53  
DQ54  
DQ55  
VSS  
N.C.  
N.C.  
VDD  
N.C.  
N.C.  
VDD  
WE  
DQ24  
DQ25  
DQ26  
DQ27  
VDD  
CAS  
DQMB4  
DQMB5  
CS1  
RAS  
VSS  
DQ56  
DQ57  
DQ58  
DQ59  
VDD  
DQMB0  
DQMB1  
CS0  
DU  
VSS  
DQ28  
DQ29  
DQ30  
DQ31  
VSS  
DQ60  
DQ61  
DQ62  
DQ63  
VSS  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
CLK2  
N.C.  
A9  
CLK3  
N.C.  
A10 (AP)  
BA1  
VDD  
BA0  
A11  
WP  
SA0  
SDA  
SCL  
VDD  
SA1  
VDD  
CLK1  
A12  
SA2  
CLK0  
VDD  
VDD  
INFINEON Technologies  
4
9.01  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
RCS0  
CS  
DQM  
CS  
DQM  
RDQMB0  
DQ0-DQ7  
RDQMB4  
DQ32-DQ39  
DQ0-DQ7  
DQ0-DQ7  
D0  
D4  
CS  
DQM  
CS  
DQM  
RDQMB1  
RDQMB5  
DQ8-DQ15  
DQ40-DQ47  
DQ0-DQ7  
DQ0-DQ7  
D1  
D5  
CS WE  
DQM  
CB0- CB7  
RCS2  
DQ0-DQ7  
D8  
CS  
DQM  
CS  
DQM  
RDQMB2  
RDQMB4  
DQ16-DQ23  
DQ48-DQ55  
DQ0-DQ7  
DQ0-DQ7  
D2  
D6  
CS  
DQM  
CS  
DQM  
RDQMB3  
RDQMB7  
DQ24-DQ31  
DQ56-DQ63  
DQ0-DQ7  
DQ0-DQ7  
D3  
D7  
E2PROM  
(256 word x 8 Bit)  
VCC  
VSS  
D0-D8, Reg., DLL  
D0-D8, Reg., DLL  
SA0  
SA1  
SA2  
SCL  
SA0  
SA1 SDA  
C
SA2  
SCL  
WP  
47 k  
CLK0  
12 pF  
PLL  
SDRAMs D0-D8  
Notes:  
1)  
DQ wirding may differ from that  
decribed in this drawing;  
however DQ/DQB relationship  
must be maintained as shown  
CS0/CS2  
DQMB0-7  
BA0, BA1  
A0-A11,12*)  
RAS  
CAS  
CKE0  
WE  
RCS0/RCS2  
RDQMB0-7  
RBA0, RBA1  
RA0-11,12  
RRAS  
RCAS  
RCKE0  
SDRAMs D0-D8  
SDRAMs D0-D8  
SDRAMs D0-D8  
SDRAMs D0-D8  
SDRAMs D0-D8  
SDRAMs D0-D8  
2)  
All resistors are 10 unless  
otherwise noted  
*) A12 is only for 32 M x 72  
organisation  
RWE  
CLK1, CLK2, CLK3  
REGE  
12 pF  
10 k  
VCC  
SPB04130-2  
Block Diagram: One Bank 8M x 72, 16M x 72 & 32M x 72 SDRAM DIMM Modules  
HYS 72V8200GR, HYS72V16201GR and HYS 72V32200GR Using x8 Organized SDRAMs  
INFINEON Technologies  
5
9.01  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
RCS0  
RDQMB0  
RDQMB4  
DQM  
CS  
DQM  
CS  
DQ0-DQ3  
DQ4-DQ7  
DQ32-DQ35  
DQ0-DQ3  
DQ0-DQ3  
D0  
D8  
DQM  
CS  
DQM  
CS  
DQ36-DQ39  
DQ0-DQ3  
DQ0-DQ3  
D1  
D9  
RDQMB1  
RDQMB5  
DQM  
CS  
DQM  
CS  
DQ8-DQ11  
DQ40-DQ43  
DQ0-DQ3  
DQ0-DQ3  
D2  
D10  
DQM  
CS  
DQM  
CS  
DQ12-DQ15  
CB0-CB3  
DQ44-DQ47  
CB4-CB7  
DQ0-DQ3  
DQ0-DQ3  
D3  
D11  
DQM  
CS  
DQM  
CS  
DQ0-DQ3  
D17  
DQ0-DQ3  
D16  
RCS2  
RDQMB2  
RDQMB6  
DQM  
CS  
DQ0-DQ3  
DQM  
DQ0-DQ3  
D12  
CS  
DQ16-DQ19  
DQ20-DQ23  
DQ48-DQ51  
D4  
DQM  
DQ0-DQ3  
CS  
DQM  
DQ0-DQ3  
D13  
CS  
DQ52-DQ55  
D5  
RDQMB3  
RDQMB7  
DQM  
DQ0-DQ3  
CS  
DQM  
DQ0-DQ3  
D14  
CS  
DQ24-DQ27  
DQ56-DQ59  
D6  
DQM  
CS  
DQ0-DQ3  
DQM  
CS  
DQ0-DQ3  
D15  
DQ28-DQ31  
DQ60-DQ63  
D7  
E2PROM  
(256 word x 8 Bit)  
CLK0  
12 pF  
PLL  
SDRAMs D0-D17  
CLK1, CLK2, CLK3  
SA0  
SA1  
SA2  
SCL  
SA0  
SA1 SDA  
SA2  
SCL  
12 pF  
CS0/CS2  
DQMB0-7  
BA0, BA1  
A0-A11, A12* )  
RAS  
CAS  
CKE0  
WE  
RCS0/RCS2  
WP  
RDQMB0-7  
RBA0, RBA1  
RA0-RA11  
RRAS  
RCAS  
RCKE0  
SDRAMs D0-D17  
47 k  
SDRAMs D0-D17  
SDRAMs D0-D17  
SDRAMs D0-D17  
SDRAMs D0-D17  
SDRAMs D0-D17  
VCC  
VSS  
D0-D17, Reg., DLL  
D0-D17, Reg., DLL  
C
RWE  
REGE  
10 k  
1) DQ wirding may differ from that decribed  
*) A12 is only used for  
128 M x 72 organisation  
VCC  
in this drawing; however DQ/DQB relationship  
must be maintained as shown  
2) All resistors are 10  
unless otherwise noted  
SPB04131  
Block Diagram: One Bank 16M x 72 & 64M x 72 SDRAM DIMM Modules  
HYS 72V16200GR, HYS72V32201 and HYS 72V64200GR Using x4 Organized SDRAMs  
INFINEON Technologies  
6
9.01  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
RCS0  
RCS1  
RDQMB0  
RDQMB4  
DQM  
CS DQM  
CS  
DQM  
CS DQM  
CS  
DQ0-DQ3  
DQ4-DQ7  
DQ32-DQ35  
DQ0-DQ3  
DQ0-DQ3  
DQ0-DQ3  
DQ0-DQ3  
D0  
CS DQM  
D0  
CS  
D8  
CS DQM  
D8  
CS  
DQM  
DQM  
DQ36-DQ39  
DQ0-DQ3 DQ0-DQ3  
DQ0-DQ3 DQ0-DQ3  
D1  
D1  
D9  
D9  
RDQMB1  
RDQMB5  
DQM  
DQ0-DQ3  
CS DQM  
DQ0-DQ3  
CS  
DQM  
DQ0-DQ3  
D10  
CS DQM  
CS  
DQ8-DQ11  
DQ40-DQ43  
DQ0-DQ3  
D2  
D2  
D10  
DQM  
DQ0-DQ3  
CS DQM  
DQ0-DQ3  
CS  
DQM  
DQ0-DQ3  
D11  
CS DQM  
CS  
DQ12-DQ15  
CB0-CB3  
DQ44-DQ47  
CB4-CB7  
DQ0-DQ3  
D3  
D3  
D11  
DQM  
CS DQM  
CS  
DQM  
CS DQM  
DQ0-DQ3  
D17  
CS  
DQ0-DQ3 DQ0-DQ3  
DQ0-DQ3  
D16  
D16  
D17  
RCS2  
RCS3  
RDQMB2  
RDQMB6  
DQM  
DQ0-DQ3  
CS DQM  
CS  
DQM  
DQ0-DQ3  
D12  
CS DQM  
CS  
DQ16-DQ19  
DQ48-DQ51  
DQ0-DQ3  
DQ0-DQ3  
D4  
D4  
D12  
DQM  
DQ0-DQ3  
CS DQM  
DQ0-DQ3  
CS  
DQM  
DQ0-DQ3  
D13  
CS DQM  
CS  
DQ20-DQ23  
DQ52-DQ55  
DQ0-DQ3  
D5  
D5  
D13  
RDQMB3  
RDQMB7  
DQM  
DQ0-DQ3  
CS DQM  
DQ0-DQ3  
CS  
DQM  
DQ0-DQ3  
D14  
CS DQM  
CS  
DQ24-DQ27  
DQ56-DQ59  
DQ0-DQ3  
D6  
D6  
D14  
DQM  
DQ0-DQ3  
CS DQM  
DQ0-DQ3  
CS  
DQM  
DQ0-DQ3  
D15  
CS DQM  
CS  
DQ28-DQ31  
DQ61-DQ63  
DQ0-DQ3  
D7  
D7  
D15  
E2PROM  
(256 word x 8 Bit)  
CLK0  
12 pF  
PLL  
Stacked SDRAMs D0-D17  
CLK1, CLK2, CLK3  
SA0  
SA1  
SA2  
SCL  
SA0  
SA1 SDA  
SA2  
SCL  
12 pF  
CS0-CS3  
DQMB0-7  
BA0, BA1  
A0-A11, A12* )  
RAS  
CAS  
CKE0  
WE  
RCS0-RCS3  
WP  
RDQMB0-7  
RBA0, RBA1  
RA0-RA11  
RRAS  
RCAS  
RCKE0  
Stacked SDRAMs D0-D17  
Stacked SDRAMs D0-D17  
Stacked SDRAMs D0-D17  
Stacked SDRAMs D0-D17  
Stacked SDRAMs D0-D17  
Stacked SDRAMs D0-D17  
47 k  
VCC  
VSS  
D0-D17, Reg. DLL  
D0-D17, Reg. DLL  
C
RWE  
REGE  
1.) DQ wirding may differ from that decribed  
*) A12 is only used for  
128 M x 72 organisation  
10 k  
in this drawing; however DQ/DQB relationship  
must be maintained as shown  
VCC  
2.) All resistors are 10  
unless otherwise noted  
SPB04132  
Block Diagram: Two Bank 128M x 72 SDRAM DIMM Modules  
HYS 72V128220GR Using Stacked x4 Organized SDRAMs  
INFINEON Technologies  
7
9.01  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
Absolute Maximum Ratings  
Parameter  
Symbol  
Limit Values  
max.  
Unit  
min.  
VIN, VOUT 1.0  
Input / Output voltage relative to VSS  
Power supply voltage on VDD  
4.6  
V
VDD  
TSTG  
PD  
1.0  
4.6  
+150  
1
V
Storage temperature range  
-55  
oC  
W
mA  
Power dissipation (per SDRAM component)  
Data out current (short circuit)  
IOS  
50  
Permanent device damage may occur if Absolute Maximum Ratingsare exceeded.  
Functional operation should be restricted to recommended operation conditions.  
Exposure to higher than recommended voltage for extended periods of time affect device reliability  
DC Characteristics  
TA = 0 to 70 °C 1); VSS = 0 V; VDD = 3.3 V ± 0.3 V  
Parameter  
Symbol  
Limit Values  
max.  
Unit  
min.  
2.0  
Input High Voltage  
VIH  
VIL  
V
DD + 0.3  
V
Input Low Voltage  
0.5  
2.4  
0.8  
V
Output High Voltage (IOUT = 4.0 mA)  
Output Low Voltage (IOUT = 4.0 mA)  
VOH  
VOL  
II(L)  
V
0.4  
10  
V
Input Leakage Current, any input  
10  
µA  
(0 V < VIN < 3.6 V, all other inputs = 0 V)  
Output Leakage Current  
IO(L)  
10  
10  
µA  
(DQ is disabled, 0 V < VOUT < VDD  
)
Capacitance  
TA = 0 to 70 °C 1); VDD = 3.3 V ± 0.3 V, f = 1 MHz  
Parameter  
Symbol  
Limit Values  
Unit  
One Bank Two Bank  
Modules Modules  
Input Capacitance  
CIN  
10  
20  
pF  
(all inputs except CLK and CKE)  
Input Capacitance (CLK)  
Input Capacitance (CKE)  
CCLK  
CCKE  
CIO  
30  
17  
10  
8
30  
30  
17  
8
pF  
pF  
pF  
pF  
pF  
Input/Output Capacitance (DQ0 - DQ63, CB0 - CB7)  
Input Capacitance (SCL, SA0 - 2)  
CSC  
CSD  
Input/Output Capacitance (SDA)  
8
8
INFINEON Technologies  
8
9.01  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
Operating Currents per SDRAM component  
TA = 0 to 70 °C 1), VDD = 3.3 V ± 0.3 V  
(Recommended Operating Conditions unless otherwise noted)  
Test  
Condition  
Symbol 64Mb  
max.  
128Mb  
max.  
256Mb  
max.  
Unit  
Note  
Parameter  
2)  
Operating current  
t
RC = tRC(MIN.), tCK = tCK(MIN.)  
ICC1  
Outputs open, Burst  
110  
150  
170  
mA  
Length = 4, CL = 3. All banks  
operated in random access,  
all banks operated in ping-  
pong manner to maximize  
gapless data access  
2)  
Precharge stand-by current  
in Power Down Mode  
tCK = min. ICC2P  
2
1.5  
2
mA  
CS = VIH(MIN.), CKE VIL(MAX.)  
2)  
No operating current  
CKE ≥  
VIH(MIN.)  
ICC3N  
ICC3P  
ICC4  
45  
8
45  
10  
90  
45  
mA  
mA  
tCK = min., CS = VIH(MIN.),  
2)  
CKE ≤  
VIL(MAX.)  
10  
active state (max. 4 banks)  
2), 3)  
Burst operating current  
70  
100  
tCK = min.,  
mA  
mA  
Read command cycling  
2)  
2)  
Auto refresh current  
ICC5  
130  
1
210  
1.5  
220  
3
tCK = min.,  
Auto Refresh command cycling  
Self refresh current  
Self Refresh Mode,  
CKE = 0.2 V  
ICC6  
mA  
INFINEON Technologies  
9
9.01  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
4), 5)  
AC Characteristics (SDRAM Device Specification)  
TA = 0 to 70 °C 1); VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns  
Parameter  
Symbol  
Limit Values  
Unit Note  
-8  
PC100-222  
min.  
max.  
Clock and Access Times  
Clock Cycle Time  
CAS Latency = 3  
CAS Latency = 2  
tCK  
fCK  
tAC  
10  
10  
ns  
ns  
Clock Frequency  
CAS Latency = 3  
CAS Latency = 2  
100  
100  
MHz  
MHz  
Access Time from Clock  
CAS Latency = 3  
6
6
ns  
ns  
CAS Latency = 2  
Clock High Pulse Width  
Clock Low Pulse Width  
Transition Time  
tCH  
tCL  
tT  
3
ns  
ns  
ns  
3
0.5  
10  
Setup and Hold Parameters  
Input Setup Time  
tIS  
2
ns  
Input Hold Time  
tIH  
1
ns  
Power Down Mode Entry Time  
Power Down Mode Exit Setup Time  
Mode Register Set-up Time  
Transition Time  
tSB  
tPDE  
tRSC  
tT  
1
CLK  
CLK  
CLK  
ns  
1
2
0.5  
10  
Common Parameters  
Row to Column Delay Time  
Row Precharge Time  
Row Active Time  
tRCD  
tRP  
tRAS  
tRC  
20  
20  
45  
70  
2
ns  
ns  
100k  
ns  
Row Cycle Time  
ns  
Activate (a) to Activate (b) Command  
Period  
tRRD  
CLK  
CAS(a) to CAS(b) Command Period  
tCCD  
1
CLK  
INFINEON Technologies  
10  
9.01  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
AC Characteristics (SDRAM Device Specification) (contd) 4), 5)  
TA = 0 to 70 °C 1); VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns  
Parameter  
Symbol  
Limit Values  
Unit Note  
-8  
PC100-222  
min.  
max.  
Refresh Cycle  
Refresh Period  
tREF  
64  
ms  
6)  
Self Refresh Exit Time  
tSREX  
1
CLK  
Read Cycle  
Data Out Hold Time  
tOH  
tLZ  
3
0
3
8
2
ns  
7)  
Data Out to Low Impedance  
Data Out to High Impedance  
DQM Data Out Disable Latency  
ns  
7)  
tHZ  
ns  
tDQZ  
CLK  
Write Cycle  
Data Input to Precharge  
(write recovery)  
tWR  
2
0
CLK  
CLK  
DQM Write Mask Latency  
tDQW  
INFINEON Technologies  
11  
9.01  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
Clock Frequency and Latency (Registered DIMM Module Specification) 8)  
Parameter  
Symbol -8  
max. tCK 100  
10  
Unit Notes  
Clock Frequency  
MHz  
ns  
Clock Cycle Time  
min.  
min.  
min.  
min.  
min.  
min.  
min.  
min.  
min.  
tCK  
9)  
CAS Latency  
tAA  
3
2
6
2
2
5
2
1
1
1
1
1
CLK  
CLK  
CLK  
CLK  
CLK  
CLK  
CLK  
CLK  
CLK  
CLK  
CLK  
CLK  
RAS to CAS Delay  
RAS Latency  
tRCD  
tRL  
9)  
Precharge Time  
tRP  
Data In to Precharge  
Data In to Active/Refresh  
Bank to Bank Delay Time  
CAS to CAS Delay Time  
Write Latency  
tDPL  
tDAL  
tRRD  
tCCD  
9)  
fixed tWL  
fixed tDQW  
fixed tDQZ  
fixed tCSL  
DQM Write Mask Latency  
DQM Data Disable Latency  
Clock Suspend Latency  
9)  
INFINEON Technologies  
12  
9.01  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
Notes  
1. The registered DIMM modules are designed to operate under system operating conditions  
between 0-55 deg C ambient, maximum sustained bandwidth and 0 LFM airflow. Operating at  
higher ambient temperatures needs sufficient air flow to limit the case temperature of the  
SDRAM components do not exceed 85oC.  
2. These parameters depend on the cycle rate. All values are measured at 100 MHz operation  
frequency. Input signals are changed once during tck excepts for Icc6 and for standby currents  
when tck = infinity.  
3. These parameters are measured with continous data stream during read access and all DQ  
toggling. CL=3 and BL=4 is assumed and the data-out current is excluded.  
4. An initial pause of 100 µs is required after power-up. Then a Precharge All Banks command must  
be given followed by eight Auto Refresh (CBR) cycles before the Mode Register Set Operation  
can begin. Also the on-DIMM PLL must be given enough clock cycles to stabilize before any  
operation can be guaranteed.  
5. AC timing tests have VIL = 0.8 V and VIH = 2.0 V with the timing referenced to the 1.4 V crossover  
point. The transition time is measured between VIH and VIL. All AC measurements assume  
tT = 1 ns with the AC output load circuit shown. Specified tAC and tOH parameters are measured  
with a 50 pF only, without any resistive termination and with a input signal of 1 V/ns edge rate  
between 0.8 V and 2.0 V.  
6. Self Refresh Exit is a synchronous operation and begins on the second positive clock edge after  
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied  
after the Self Refresh Exit command is registered.  
7. Referenced to the time at which the output achieves the open circuit condition, not to output  
voltage levels.  
8. Due to the usage of a register device on all input and address signals, all external command  
cycle are delayed by one clock (Reg-DIMM Latency = 1) on the module board.  
9. Delayed by one clock cycle due to the use of the register device.  
tCH  
2.4 V  
0.4 V  
1.4 V  
CLOCK  
tT  
tCL  
tIH  
tIS  
INPUT  
1.4 V  
tAC  
tAC  
tLZ  
tOH  
I/O  
OUTPUT  
1.4 V  
50 pF  
tHZ  
Measurement conditions for  
AC and tOH  
t
IO.vsd  
Serial Presence Detect  
A serial presence detect storage device - E2PROM 34C02 - is assembled onto the module.  
Information about the module configuration, speed, etc. is written into the E2PROM device during  
module production using a serial presence detect protocol (I2C synchronous 2-wire bus)  
INFINEON Technologies  
13  
9.01  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
SPD-Table for -8 Registered DIMM Modules  
Byte# Description  
SPD Entry  
Value  
Hex  
0
Number of SPD Bytes  
128  
80  
08  
04  
1
2
3
Total Bytes in Serial PD 256  
Memory Type  
SDRAM  
Number of Row  
Addresses (without BS  
bits)  
12/13  
0C  
0C  
0C  
0C  
0D  
0D  
0D  
4
Number of Column  
Addresses  
9/10/11  
09  
01  
0A  
01  
0A  
01  
0B  
0A  
01  
0B  
01  
0B  
02  
5
6
7
Number of DIMM Banks  
Module Data Width  
1
01  
48  
00  
72  
0
Module Data Width  
(contd)  
8
Module Interface Levels LVTTL  
Cycle Time at CL = 3 10.0 ns  
01  
A0  
60  
9
10  
Access Time from Clock 6.0 ns  
at CL = 3  
11  
12  
DIMM Config (Error Det/ ECC  
Corr.)  
02  
80  
Refresh Rate/Type  
Self-Refresh,  
15.6/7.8 µs  
80  
80  
80  
82  
82  
82  
13  
14  
SDRAM Width, Primary x4, x8  
Error Checking SDRAM n/a/x4  
Data Width  
08  
08  
04  
04  
08  
08  
04  
04  
08  
08  
04  
04  
04  
04  
15  
16  
Minimum tCCD  
Burst Length Supported 1, 2, 4, 8 &  
(full page)  
1 CLK  
01  
0F  
8F  
8F  
0F  
0F  
0F  
0F  
17  
18  
Number of SDRAM  
Banks  
SDRAM Supported CAS 2 & 3  
Latencies  
4
04  
06  
19  
20  
21  
SDRAM CS Latencies  
SDRAM WE Latencies  
0
01  
01  
16  
0
SDRAM DIMM Module  
Attributes  
with PLL  
22  
SDRAM Device  
Attributes  
VDD tol +/–  
10%  
0E  
INFINEON Technologies  
14  
9.01  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
SPD-Table for -8 Registered DIMM Modules (contd)  
Byte# Description  
SPD Entry  
Value  
Hex  
23  
Min. Clock Cycle Time at 10 ns  
CL = 2  
A0  
60  
FF  
FF  
24  
25  
26  
Max. Data Access Time 6 ns  
from Clock for CL = 2  
Min. Clock Cycle Time at not supp.  
CL = 1  
Max. Data Access Time not supp.  
from Clock at CL = 1  
27  
28  
29  
30  
31  
SDRAM Minimum tRP  
SDRAM Minimum tRRD  
SDRAM Minimum tRCD  
SDRAM Minimum tRAS  
Module Bank Density  
(per bank)  
20 ns  
14  
10  
14  
2D  
40  
16 ns  
20 ns  
45 ns  
64/128/256/  
512 MByte  
2 ns  
10  
20  
20  
40  
80  
80  
32  
SDRAM Input Setup  
Time  
20  
33  
34  
SDRAM Input Hold Time 1 ns  
10  
20  
SDRAM Data Input  
Setup Time  
2 ns  
35  
SDRAM Data Input Hold 1 ns  
Time  
10  
FF  
36-61 Superset Information  
(may be used in future)  
62  
63  
SPD Revision  
Checksum for Bytes  
0 - 62  
1.2  
12  
B2  
08  
11  
99  
BC  
F5  
F6  
64-125 Manufacturers  
XX  
Information  
126  
Frequency Specification 100 MHz  
64  
8F  
FF  
127  
Details of Clocks  
Unused Storage  
Locations  
128+  
1) HYS72V16200GR-8, 2) HYS72V16201GR-8, *) HYS72V32201GR, **) HYS72V32200GR  
INFINEON Technologies  
15  
9.01  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
Package Outlines  
Module Package  
JEDEC MO-161  
64, 128 &256 MByte Registered Module  
based on x8 organised SDRAMs  
133.35  
127.35  
4 max.  
Register  
Register  
3
1
10  
11  
6.35  
40  
41  
6.35  
84  
1.27±  
0.1  
3
1.27  
42.18  
66.68  
2
85 94  
95  
124 125  
168  
PLL  
Detail of Contacts  
1+0.5  
L-DIM-168-45  
1.27  
note: all tolerances are in accordance with the JEDEC standard  
INFINEON Technologies  
16  
9.01  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
Module Package  
JEDEC MO-161  
128, 256 & 512 MByte Registered Module based  
on x4 organised SDRAMs  
133.35  
127.35  
4 max.  
Register Register  
3
1
10  
11  
6.35  
40  
41  
6.35  
84  
1.27±  
0.1  
3
1.27  
42.18  
66.68  
2
85 94  
95  
124 125  
168  
PLL  
Detail of Contacts  
1+0.5  
L-DIM-168-46  
1.27  
note: all tolerances are in accordance with the JEDEC standard  
INFINEON Technologies  
17  
9.01  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
Module Package  
JEDEC MO-161  
1 GByte Registered DIMM Module with Stacked SDRAMs  
133.35  
127.35  
6.8 max.  
Register Register  
1
10  
11  
6.35  
40  
41  
6.35  
84  
1.27±  
0.1  
3
1.27  
42.18  
66.68  
2
85 94  
95  
124 125  
168  
PLL  
Register  
Detail of Contacts  
1+0.5  
L-DIM-168-47  
1.27  
note: all tolerances are in accordance with the JEDEC standard  
INFINEON Technologies  
18  
9.01  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
Functional Description  
All 168-pin Registered DIMMs conform to a compatible set of timing and operation characteristics  
intended to comply with the 100 MHz standards. The Registered DIMMs achieve high speed data  
transfer rate up to 100 MHz, when in registered mode. The registered modeis achieved when  
the REGE input signal is in highstate or the pin is not connected. Operation in buffered mode”  
(REGE = low) needs careful system design to compensate all input signals for the extra delay time  
of the register components when in buffered mode. Buffered modeis limited to 66 Mhz operation  
and is beyond the scope of this datasheet. All INFINEON PC100 Registered DIMM modules are not  
tested for buffered modeoperation.  
Registered Mode:  
All control and address signals are synchronized with the positive edge of externally supplied clocks  
and are registered on-DIMM and hence delayed by one clock cycle in arriving at the SDRAM  
devices. The use of the on-board register reduces the capacitive loading of the DIMM on input  
control and address signals. The SDRAM device data lines (DQ) are connected directly to the DIMM  
tabs through 10 Ohm series resistors. All the following timing diagrams and explanations show  
DIMM operation at the tabs, not SDRAM operation.  
The picture below depicts an overview of the effect of the Registered Mode on the data outputs  
(DQs) for a Read operation. Without the registers, the data is delayed according to the device CAS  
latency, in the case two clocks. With the register, the data is delayed according to the device CAS  
latency plus an additional clock cycle. This is known as the DIMM CAS latency, and in this example  
is four three. The data path can be thought of as a pipeline in which the register effectively lengthens  
the pipe by one clock cycle.  
Registered DIMM Burst Read Operation (BL = 4)  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
CLK  
Command  
Read A  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
Device  
CAS latency = 2  
DOUT A0 DOUT A1 DOUT A2 DOUT A3  
t
CK2, DQs  
DIMM  
CAS latency = 3  
DOUT A0 DOUT A1 DOUT A2 DOUT A3  
Added for on-DIMM pipeline register  
t
CK3, DQs  
One Clock  
Reg-DIMM Latency = 1  
SPT03968  
In case of a Burst Write Command the data-in is delayed one clock due the op-DIMM pipeline  
register also. Therefore, data for the first Burst Write cycle must be applied on the DQ pins on the  
next clock cycle after the Write command is issued. the remaining data inputs must be supplied on  
INFINEON Technologies  
19  
9.01  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
each subsequent rising clock edge until the burst length is completed. When the burst has finished,  
any additional data supplied to the DQ pins will be ignored.  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
CLK  
Command  
DQs  
NOP  
Write A  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
dont care  
DIN A0  
DIN A1  
DIN A2  
DIN A3  
The first data element and the Write  
are registered on the next clock edge  
Reg-DIMM Latency = 1 CLK  
Extra data is ignored after  
termination of a Burst.  
SPT03969  
Registered DIMM Burst Write Operation (BL = 4)  
INFINEON Technologies  
20  
9.01  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
INFINEON Technologies  
21  
9.01  
HYS 72Vx2xxGR  
PC100 Registered SDRAM-Modules  
Rev. Changes  
12.98  
12.98  
Byte 12 changed from 80h (15.6 µs) to 82h (7.8 µs), CheckSum Byte 63 aju-  
sted, comment added to page 2 will change to Rev 1.2 in future”  
Byte 16 changed from 8Fh to 0Fh (no full page support for 256M based modu-  
les). Spec reference changed to INTEL Rev. 1.2  
2.98  
Values for discrete capacitors on CLK0 inputs changed to 12pF according to  
INTEL Rev.1.2 specification, Ioh & Iol changed to 4mA  
2.98  
Compliance Code changed from 620R to 622R accroding to INTELs Rev. 1.2  
specification  
18.4.1999  
-8A speed sort added for 256M based modules  
-8B speed sort removed for 64M based modules  
Infineon logo added  
SPD updated according to new speedsort for 256M devices  
12.5.99  
16.6.99  
13.8.99  
Some ICC currents changed due to new inputs and measurements  
Input capacitance changed according to new measurements  
Input capacitance changed according to new measurements with flexframe  
stacked components  
2.9.99  
3.9.99  
Typoo on page 2, 64Mx72 to 128Mx72 corrected  
Changed to data book version from R&L  
1 GByte module thickness 4 to 8 mm changes, (masked)  
28.9.99  
19.10.99  
30.11.99  
CL 2 frequency changed to 66 MHz for -8A parts  
Typoo in input capacitance corrected (input stacked from 10 to 20 pF)  
Notes renumbered, Note 1) added, explaining maximum operation tempera-  
ture for registered DIMM modules  
14.12.99  
HYS72V32220GR (64M stacked removed), HYS72V32201GR added  
-8B version removed  
10.1.2000  
7.3.2000  
28.3.2000  
HYS72V16201GR version added  
Check-Sum for HYS72V32201GR-8 corrected from BA to B2  
Byte 127 for -8A modules stays at 8F for 256Mbit S20 (Rev.A)  
Byte 127 for -8A modules changed to 8D for 256Mbit S19&S17 (Rev.B and C)  
for compliance with existing (VL02) and future (VL03) testprograms  
4.12.2000  
Thickness of 1 Gbyte module changed from 8 mm (JEDEC value)  
to 6.4 mm typ. (actual values)  
18.1.2001  
15.02.2001  
5.03.2001  
6.06.2001  
06.09.2001  
Clarification of buffered modeoperation  
Outline Drawings changed to L-DIM-168-45,46 & 47  
-8A speed sort removed  
Typo in SPB04130 corrected (new :SPB04130-2)  
SCR: Thickness of modules with stacked components changed from 6.4 to 6.8  
max.  
INFINEON Technologies  
22  
9.01  
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