HYS64/72D16x01/32x00/64x20GU-6/7/8-B
Unbuffered DDR-I SDRAM-Modules
Operating, Standby and Refresh Currents (PC1600, -8)
128MB 256MB 256MB 512MB 512MB
x64
1bank
-8
x64
1bank
-8
x72
1bank
-8
x64
2bank
-8
x72
2bank Unit
-8
Notes
4
Symbol
Parameter/Condition
MAX
MAX
MAX
MAX
MAX
Operating Current
: one bank; active / precharge; tRC = tRC MIN;
tCK = tCK MIN; DQ, DM, and DQS inputs changing once per clock
cycle; address and control inputs changing once every two clock
cycles
IDD0
380
720
810
1080
1215
mA
1
Operating Current: one bank; active/read/precharge; Burst = 4;
IDD1
420
28
800
56
900
63
1160
112
1305
126
mA
mA
1, 3
2
Refer to the following page for detailed test conditions.
Precharge Power-Down Standby Current: all banks idle; power-
IDD2P
down mode; CKE <= VIL MAX; tCK = tCK MIN
Precharge Floating Standby Current
: /CS >= VIH MIN, all banks
idle; CKE >= VIH MIN; tCK = tCK MIN ,address and other control
inputs changing once per clock cycle, VIN = VREF for DQ, DQS and
DM.
140
280
315
560
630
IDD2F
mA
2
Precharge Quiet Standby Current
: /CS >= VIH MIN, all banks idle;
CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs
stable at >= VIH MIN or <= VIL MAX; VIN = VREF for DQ, DQS and
DM.
88
64
176
128
198
144
352
256
396
288
IDD2Q
IDD3P
mA
mA
2
2
Active Power-Down Standby Current
: one bank active; power-
down mode; CKE <= VIL MAX; tCK = tCK MIN;VIN = VREF for DQ,
DQS and DM.
Active Standby Current
: one bank active; active / precharge;CS >=
VIH MIN; CKE >= VIH MIN; tRC = tRAS MAX; tCK = tCK MIN; DQ,
DM, and DQS inputs changing twice per clock cycle; address and
control inputs changing once per clock cycle
IDD3N
IDD4R
IDD4W
200
440
480
360
760
840
405
855
945
720
1120
1200
810
1260
1350
mA
mA
mA
2
Operating Current
: one bank active; Burst = 2; reads; continuous
burst; address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge; CL = 2 for
DDR200, and DDR266A, CL=3 for DDR333; tCK = tCK MIN; IOUT =
0mA
1, 3
Operating Current
: one bank active; Burst = 2; writes; continuous
burst; address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge; CL = 2 for
DDR200, and DDR266A, CL=3 for DDR333; tCK = tCK MIN
1
1
Auto-Refresh Current: tRC = tRFC MIN, distributed refresh
680
10
1360
20
1530
22,5
1720
40
1935
45
IDD5
IDD6
mA
mA
Self-Refresh Current
: CKE <= 0.2V; external clock on; tCK = tCK
MIN
Operating Current
: four bank; four bank interleaving with BL=4;
IDD7
880
1680
1890
2040
2295
mA
1, 3
Refer to the following page for detailed test conditions.
1. The module IDD values are calculated from the component IDD datasheet values as:
n * IDDx[component]
for single bank modules (n: number of components per module bank)
n * IDDx[component] + n * IDD3N[component]
for two bank modules (n: number of components per module bank)
2. The module IDD values are calculated from the component IDD datasheet values as:
n * IDDx[component]
2 * n * IDDx[component]
for single bank modules (n: number of components per module bank)
for two bank modules (n: number of components per module bank)
3. DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending
on load conditions
4. Test condition for maximum values: VDD = 2.7V ,Ta = 10°C
INFINEON Technologies
12
2002-10-24 (rev. 0.94)
