HYS 64V4200GDL/HYS 64V8220GDL
144-pin SO-DIMM SDRAM Modules
Operating Currents per Memory Bank
TA = 0 to 70 °C, VDD = 3.3 V ± 0.3 V
(Recommended Operating Conditions unless otherwise noted)
Parameter
Test Condition Symbol -7.5 -8
Unit Note
1)
Operating current
–
ICC1
560 520 mA
tRC = tRC(MIN.), tCK = tCK(MIN.)
Outputs open, Burst Length = 4, CL = 3
All banks operated in random access,
all banks operated in ping-pong manner to
maximize gapless data access
1)
1)
Precharge stand-by current
in Power Down Mode
t
t
CK = min.
ICC2P
8
4
8
4
mA
mA
CK = infinity
ICC2PS
CS = VIH(MIN.), CKE ≤ VIL(MAX.)
1)
1)
Precharge Stand-by Current
in Non-Power Down Mode
t
t
CK = min.
ICC2N
160 140 mA
20 20 mA
CK = infinity
ICC2NS
CS = VIH (MIN.), CKE ≥ VIH(MIN.)
1)
1)
No operating current
CKE ≥ VIH(MIN.) ICC3N
CKE ≤ VIL(MAX.) ICC3P
200 180 mA
32 32 mA
tCK = min., CS = VIH(MIN.),
active state (max. 4 banks)
1), 2)
Burst operating current
–
ICC4
ICC5
ICC6
440 400 mA
560 520 mA
tCK = min.,
Read command cycling
1)
Auto refresh current
–
tCK = min.,
Auto Refresh command cycling
1)
Self refresh current
L-version
2
2
mA
Self Refresh Mode, CKE = 0.2 V
Notes
1. These parameters depend on the cycle rate. These values are measured at 133 MHz for -
7.5 parts, 100 MHz for -8 parts, and at 66 MHz for -10 parts. Input signals are changed once
during tCK, excepts for ICC6 and for standby currents when tCK = infinity.
2. These parameters are measured with continuous data stream during read access and all DQ
toggling. CL = 3 and BL = 4 are assumed and the VDDQ current is excluded.
Data Book
7
12.99
