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HYS64V64220GU-7.5-C2

型号：

HYS64V64220GU-7.5-C2

描述：

64位SDRAM模块\n[ x64 SDRAM Module ]

品牌：

ETC[ ETC ]

页数：

16 页

PDF大小：

132 K

下载PDF手册
HYS 64/72V64220GU  
SDRAM-Modules  
3.3 V 64M × 64/72-Bit SDRAM Modules  
168-pin Unbuffered DIMM Modules  
• 168-pin unbuffered 8 Byte Dual-In-Line  
SDRAM Modules for PC main memory  
applications  
• Programmable CAS Latency, Burst Length,  
and Wrap Sequence (Sequential &  
Interleave)  
• PC100-222 and PC133-333 versions  
• Auto Refresh (CBR) and Self Refresh  
• Decoupling capacitors mounted on substrate  
• All inputs and outputs are LVTTL compatible  
• Serial Presence Detect with E2PROM  
• Two bank 64M × 64 and 64M × 72  
organization  
• Optimized for byte-write non-parity or ECC  
applications  
• Uses Infineon 256 Mbit SDRAM components  
in 32M × 8 organization and TSOPII-54  
packages  
• Fully PC board layout compatible to INTEL’s  
Rev. 1.0 module specification  
• JEDEC standard Synchronous DRAMs  
(SDRAM  
• Gold contact pad, card size:  
133.35 mm × 31.75 mm × 4.00 mm  
(JEDEC MO-161-BA)  
• Programmed Latencies:  
Product Speed  
CL tRCD  
tRP  
3
-7.5  
-8  
PC133  
PC100  
3
2
3
2
2
• Single + 3.3 V (± 0.3 V) power supply  
• SDRAM Performance:  
-7.5  
-8  
Unit  
PC133  
133  
PC100  
100  
6
fCK  
tAC  
Clock Frequency (max.)  
Clock Access time  
MHz  
ns  
5.4  
The HYS 64V64220GU and HYS 72V64220GU are industry standard 168-pin 8-byte Dual in-line  
Memory Modules (DIMMs) which are organized as 64M × 64 and 64M × 72 in two banks high speed  
memory arrays designed with 256M Synchronous DRAMs (SDRAMs) for non-parity and ECC  
applications. The DIMMs use 7-5 speed sorted 256 Mbit Synchronous DRAMs (SDRAMs) to meet  
the PC133-333 requirements and -8 components for the standard PC100 applications. Decoupling  
capacitors are mounted on the PC board. The PC board design is according to INTEL’s PC100  
module specification. The DIMMs have a serial presence detect, implemented with a serial  
E2PROM using the 2-pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer  
and the second 128 bytes are available to the end user. All Infineon 168-pin DIMMs provide a high  
performance, flexible 8-byte interface in a 133.35 mm long footprint, with 1.25“ (31.75 mm) height.  
INFINEON Technologies  
1
3.01  
HYS 64/72V64220GU  
SDRAM-Modules  
Ordering Information  
Type  
Code  
Package  
Descriptions  
Module  
Height  
HYS 64V64220GU-7.5-C2 PC133-333-520 L-DIM-168-30 PC133 64M × 64 2 bank 1.25“  
SDRAM module  
HYS 72V64220GU-7.5-C2 PC133-333-520 L-DIM-168-30 PC133 64M × 72 2 bank 1.25“  
SDRAM module  
HYS 64V64220GU-8-C2 PC100-222-620 L-DIM-168-30 PC100 64M × 64 2 bank 1.25“  
SDRAM module  
HYS 72V64220GU-8-C2 PC100-222-620 L-DIM-168-30 PC100 64M × 72 2 bank 1.25“  
SDRAM module  
Note: All part numbers end with a place code, designating the die revision. Consult factory for  
current revision. Example: HYS 64V64220GU-8-C2, indicating Rev.C2 dies are used for  
SDRAM components.  
INFINEON Technologies  
2
3.01  
HYS 64/72V64220GU  
SDRAM-Modules  
Pin Definitions and Functions  
A0 - A12  
Address Inputs  
Bank Selects  
CLK0 - CLK3  
Clock Input  
BA0, BA1  
DQMB0 - DQMB7 Data Mask  
DQ0 - DQ63 Data Input/Output  
CS0 - CS3  
Chip Select  
CB0 - CB7  
RAS  
Check Bits (x72 organization only) VDD  
Power (+ 3.3 V)  
Ground  
Row Address Strobe  
Column Address Strobe  
Read/Write Input  
VSS  
CAS  
SCL  
SDA  
Clock for Presence Detect  
WE  
Serial Data Out for  
Presence Detect  
CKE0, CKE1 Clock Enable  
N.C./DU  
No Connection  
Address Format  
Part Number  
Rows Columns Bank Select Refresh Period Interval  
64M × 64/72 HYS64/72V64220GU 13  
10  
2
8k  
64 ms 7.8 µs  
Pin Configuration  
PIN# Symbol  
PIN# Symbol  
PIN# Symbol  
PIN# Symbol  
1
VSS  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
VSS  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
101  
102  
VSS  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
VSS  
2
DQ0  
DQ1  
DQ2  
DQ3  
VDD  
DU  
DQ32  
DQ33  
DQ34  
DQ35  
VDD  
CKE0  
CS3  
3
CS2  
4
DQMB2  
DQMB3  
DU  
DQMB6  
DQMB7  
N.C.  
5
6
7
DQ4  
DQ5  
DQ6  
DQ7  
DQ8  
VSS  
VDD  
DQ36  
DQ37  
DQ38  
DQ39  
DQ40  
VSS  
VDD  
8
N.C.  
N.C.  
9
N.C.  
N.C.  
10  
11  
12  
13  
14  
15  
16  
17  
18  
N.C. (CB2)  
N.C. (CB3)  
VSS  
CB6  
CB7  
VSS  
DQ9  
DQ10  
DQ11  
DQ12  
DQ13  
VDD  
DQ16  
DQ17  
DQ18  
DQ19  
VDD  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
VDD  
DQ48  
DQ49  
DQ50  
DQ51  
VDD  
DQ20  
DQ52  
INFINEON Technologies  
3
3.01  
HYS 64/72V64220GU  
SDRAM-Modules  
Pin Configuration (cont’d)  
PIN# Symbol PIN# Symbol  
PIN# Symbol  
PIN# Symbol  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
DQ14  
DQ15  
N.C. (CB0)  
N.C. (CB1)  
VSS  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
N.C.  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
DQ46  
DQ47  
N.C. (CB4)  
N.C. (CB5)  
VSS  
145  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
157  
158  
159  
160  
161  
162  
163  
164  
165  
166  
167  
168  
N.C.  
DU  
DU  
CKE1  
VSS  
N.C.  
VSS  
DQ21  
DQ22  
DQ23  
VSS  
DQ53  
DQ54  
DQ55  
VSS  
N.C.  
N.C.  
VDD  
N.C.  
N.C.  
VDD  
WE  
DQ24  
DQ25  
DQ26  
DQ27  
VDD  
CAS  
DQMB4  
DQMB5  
CS1  
DQ56  
DQ57  
DQ58  
DQ59  
VDD  
DQMB0  
DQMB1  
CS0  
DU  
RAS  
VSS  
VSS  
DQ28  
DQ29  
DQ30  
DQ31  
VSS  
DQ60  
DQ61  
DQ62  
DQ63  
VSS  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
CLK2  
N.C.  
A9  
CLK3  
N.C.  
SA0  
A10  
BA0  
BA1  
WP  
A11  
VDD  
SDA  
SCL  
VDD  
SA1  
VDD  
CLK1  
A12  
SA2  
CLK0  
VDD  
VDD  
Note: Pin names in paranthese are for the x72 ECC versions; example: Pin 106 = (CB5)  
INFINEON Technologies  
4
3.01  
HYS 64/72V64220GU  
SDRAM-Modules  
CS1  
CS0  
CS  
CS  
CS  
CS  
DQMB0  
DQ(7:0)  
DQM  
DQM  
DQMB4  
DQM  
DQM  
DQ0-DQ7  
DQ0-DQ7  
DQ(39:32)  
DQ0-DQ7  
DQ0-DQ7  
D0  
D1  
D8  
D9  
D4  
D5  
D12  
D13  
CS  
CS  
CS  
CS  
DQMB1  
DQM  
DQM  
DQMB5  
DQM  
DQM  
DQ(15:8)  
DQ0-DQ7  
DQ0-DQ7  
DQ(47:40)  
DQ0-DQ7  
DQ0-DQ7  
CS  
CS  
DQM  
DQM  
DQ0-DQ7  
CB(7:0)  
DQ0-DQ7  
D16  
D17  
CS3  
CS2  
CS  
CS  
CS  
CS  
DQMB2  
DQM  
DQM  
DQMB6  
DQM  
DQM  
DQ(23:16)  
DQ0-DQ7  
DQ0-DQ7  
DQ(55:48)  
DQ0-DQ7  
DQ0-DQ7  
D2  
D3  
D10  
D11  
D6  
D7  
D14  
D15  
CS  
CS  
CS  
CS  
DQMB3  
DQM  
DQM  
DQMB7  
DQM  
DQM  
DQ(31:24)  
DQ0-DQ7  
DQ0-DQ7  
DQ(63:56)  
DQ0-DQ7  
DQ0-DQ7  
A0-A12, BA0, BA1  
D0-D15, (D16, D17)  
D0-D15, (D16, D17)  
E2PROM (256 Word x 8 Bit)  
SA0  
SA0  
SA1  
SA2  
SCL  
VDD  
SA1  
SA2  
SCL  
SDA  
WP  
C0-C31, (C32...C35)  
VSS  
D0-D7, (D8)  
47 k  
Ω
RAS, CAS, WE  
CKE0  
D0-D15, (D16, D17)  
Clock Wiring  
64 M x 64  
D0-D7, (D16)  
D9-D15, (D17)  
VDD  
64 M x 72  
5 SDRAM  
5 SDRAM  
4 SDRAM + 3.3 pF  
4 SDRAM + 3.3 pF  
10 k  
Ω
CLK0  
4 SDRAM + 3.3 pF  
4 SDRAM + 3.3 pF  
4 SDRAM + 3.3 pF  
4 SDRAM + 3.3 pF  
CLK1  
CLK2  
CLK3  
CKE1  
Note: D16 & D17 is only used in the x72 ECC version and all resistor values are 10 Ω except otherwise noted.  
SPB03971  
Block Diagram: 64M × 64/72 Two Bank SDRAM DIMM Modules  
INFINEON Technologies  
5
3.01  
HYS 64/72V64220GU  
SDRAM-Modules  
DC Characteristics  
TA = 0 to 70 °C; VSS = 0 V; VDD,VDDQ = 3.3 V ± 0.3 V  
Parameter  
Symbol  
Limit Values  
max.  
Unit  
min.  
2.0  
Input High Voltage  
VIH  
VIL  
V
DD + 0.3  
V
Input Low Voltage  
– 0.5  
2.4  
0.8  
–
V
Output High Voltage (IOUT = – 4.0 mA)  
Output Low Voltage (IOUT = 4.0 mA)  
VOH  
VOL  
II(L)  
V
–
0.4  
40  
V
Input Leakage Current, any input  
– 40  
µA  
(0 V < VIN < 3.6 V, all other inputs = 0 V)  
Output Leakage Current  
IO(L)  
– 40  
40  
µA  
(DQ is disabled, 0 V < VOUT < VDD)  
Capacitance  
TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz  
Parameter  
Symbol  
Limit Values  
max.  
Unit  
max.  
64M × 64  
64M × 72  
Input Capacitance  
CI1  
105  
144  
pF  
(A0 to A11, BA0, BA1, RAS, CAS, WE)  
Input Capacitance (CS0 - CS3)  
Input Capacitance (CLK0 - CLK3)  
Input Capacitance (CKE0, CKE1)  
Input Capacitance (DQMB0 - DQMB7)  
CI2  
CICL  
CI3  
CI4  
CIO  
32  
40  
65  
20  
17  
40  
43  
72  
25  
17  
pF  
pF  
pF  
pF  
pF  
Input/Output Capacitance  
(DQ0 - DQ63, CB0 - CB7)  
Input Capacitance (SCL, SA0-2)  
Input/Output Capacitance  
CSC  
CSD  
8
8
8
8
pF  
pF  
INFINEON Technologies  
6
3.01  
HYS 64/72V64220GU  
SDRAM-Modules  
Operating Currents per SDRAM Component 1)  
TA = 0 to 70 oC, VDD = 3.3 V ± 0.3 V  
(Recommended Operating Conditions unless otherwise noted)  
Parameter  
Test  
Symbol -7.5 -8  
Unit Note  
Condition  
max.  
1)  
Operating current  
–
ICC1  
230 170  
mA  
tRC = tRC(MIN.), tCK = tCK(MIN.)  
Outputs open, Burst Length = 4, CL = 3  
All banks operated in random access,  
all banks operated in ping-pong manner  
to maximize gapless data access  
1)  
Precharge stand-by current  
in Power Down Mode  
t
t
CK = min.  
CK = min.  
ICC2P  
2
2
mA  
CS = VIH(MIN.), CKE ≤ VIL(MAX.)  
1)  
Precharge Stand-by Current  
in Non-Power Down Mode  
ICC2N  
40  
30  
mA  
CS = VIH (MIN.), CKE ≥ VIH(MIN.)  
1)  
No operating current  
CKE ≥ VIH(MIN.) ICC3N  
CKE ≤ VIL(MAX.) ICC3P  
50  
10  
45  
10  
mA  
1)  
mA  
tCK = min., CS = VIH(MIN.),  
active state (max. 4 banks)  
1), 2)  
Burst operating current  
–
–
ICC4  
ICC5  
ICC6  
150 100  
240 220  
mA  
tCK = min.,  
Read command cycling  
1)  
Auto refresh current  
mA  
tCK = min.,  
Auto Refresh command cycling  
1)  
Self refresh current  
3
3
mA  
Self Refresh Mode, CKE = 0.2 V  
INFINEON Technologies  
7
3.01  
HYS 64/72V64220GU  
SDRAM-Modules  
3), 4)  
AC Characteristics  
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns  
Parameter  
Symbol  
Limit Values  
Unit Note  
-7.5  
-8  
PC133-333  
PC100-222  
min.  
max.  
min.  
max.  
Clock  
Clock Cycle Time  
tCK  
–
CAS Latency = 3  
CAS Latency = 2  
7.5  
12  
–
–
10  
10  
–
–
ns  
ns  
System Frequency  
fCK  
–
CAS Latency = 3  
CAS Latency = 2  
for HYS64/72V64220GU-7.5-C2  
–
–
133  
100  
–
–
100  
100  
MHz  
MHz *)  
4), 5)  
Clock Access Time  
CAS Latency = 3  
CAS Latency = 2  
tAC  
–
–
5.4  
6
–
–
6
6
ns  
ns  
6)  
Clock High Pulse Width  
Clock Low Pulse Width  
tCH  
tCL  
2.5  
2.5  
–
–
3
3
–
–
ns  
6)  
ns  
Setup and Hold Times  
Input Setup Time  
7)  
tCS  
tCH  
tSB  
1.5  
0.8  
–
–
–
1
–
–
–
2
1
–
1
2
1
–
–
1
–
–
–
ns  
7)  
Input Hold Time  
ns  
8)  
Power Down Mode Entry Time  
CLK  
9)  
Power Down Mode Exit Setup Time tPDE  
1
CLK  
Mode Register Setup Time  
Transition Time (rise and fall)  
tRSC  
tT  
2
CLK  
1
ns  
–
Common Parameters  
RAS to CAS Delay  
Precharge Time  
tRCD  
tRP  
tRAS  
tRC  
20  
20  
45  
67.5  
15  
1
–
20  
20  
50  
70  
16  
1
–
ns  
–
–
–
–
–
–
–
–
ns  
Active Command Period  
Cycle Time  
100k  
100k  
ns  
–
–
–
–
–
–
ns  
Bank to Bank Delay Time  
tRRD  
ns  
CAS to CAS Delay Time (same bank) tCCD  
CLK  
INFINEON Technologies  
8
3.01  
HYS 64/72V64220GU  
SDRAM-Modules  
AC Characteristics (cont’d) 3), 4)  
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns  
Parameter  
Symbol  
Limit Values  
Unit Note  
-7.5  
-8  
PC133-333  
PC100-222  
min.  
max.  
min.  
max.  
Refresh Cycle  
8)  
Refresh Period (8192 cycles)  
Self Refresh Exit Time  
tREF  
–
64  
–
64  
ms  
10)  
tSREX  
1
–
1
–
CLK  
Read Cycle  
4)  
Data Out Hold Time  
tOH  
tLZ  
3
0
3
–
–
–
7
2
3
0
3
–
–
–
8
2
ns  
Data Out to Low Impedance  
Data Out to High Impedance  
DQM Data Out Disable Latency  
ns  
–
11)  
tHZ  
ns  
tDQZ  
CLK  
–
Write Cycle  
Data Input to Precharge  
(write recovery)  
tWR  
2
0
–
–
2
0
–
–
CLK  
CLK  
–
–
DQM Write Mask Latency  
tDQW  
Notes  
1. These parameters depend on the cycle rate. These values are measured at 133 MHz for -7.5  
modules and at 100 Mhz for -8 modules. Input signals are changed once during tCK, except for  
I
CC6 and for standby currents when tCK = infinity. All values are shown per memory component.  
2. These parameters are measured with continuous data stream during read access and all DQ  
toggling. CL = 3 and BL = 4 assumed and the VDDQ current is excluded.  
3. All AC characteristics are shown on SDRAM component level.  
An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must  
be given followed by eight Auto-Refresh (CBR) cycles before the Mode Register Set Operation  
can begin.  
4. AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover  
point. The transition time is measured between VIH and VIL. All AC measurements assume  
tT = 1 ns with the AC output load circuit show. Specified tAC and tOH parameters are measured  
with a 50 pF only, without any resistive termination and with a input signal of 1 V/ns edge rate  
between 0.8 V and 2.0 V.  
5. If clock rising time is longer than 1 ns, a time (tT/2 – 0.5) ns must be added to this parameter.  
INFINEON Technologies  
9
3.01  
HYS 64/72V64220GU  
SDRAM-Modules  
6. Rated at 1.4 V  
7. If tT is longer than 1 ns, a time (tT – 1) ns has to be added to this parameter.  
8. Anytime the Refresh Period has been exceeded, a minimum of two Auto-Refresh (CBR)  
commands must be given to “wake-up” the device.  
9. Timing is asynchronous. If setup time is not met by rising edge of the clock then the CKE signal  
is assumed latched on the next cycle.  
10.Self-Refresh Exit is a synchronous operation and begins on the second positive clock edge after  
CKE returns high. Self-Refresh Exit is not complete until a time period equal to tRC is satisfied  
after the Self Refresh Exit command is registered.  
11.This is referenced to the time at which the output achieves the open circuit condition, not to  
output voltage levels.  
tCH  
2.4 V  
0.4 V  
CLOCK  
tT  
tCL  
tHOLD  
tSETUP  
INPUT  
1.4 V  
tAC  
tAC  
I/O  
tLZ  
tOH  
50 pF  
OUTPUT  
1.4 V  
Measurement conditions for  
AC and tOH  
tHZ  
t
SPT03404  
Note: *) 256MByte PC133 modules with place codes earlier than “-C2” (f.e. “A” and “B”) are only  
backward compatible to PC100 3-2-2 when operating on a 100 Mhz memory bus.  
A serial presence detect storage device - E2PROM - is assembled onto the module. Information  
about the module configuration, speed, etc. is written into the E2PROM device during module  
production using a serial presence detect protocol (I2C synchronous 2-wire bus).  
INFINEON Technologies  
10  
3.01  
HYS 64/72V64220GU  
SDRAM-Modules  
SPD-Table for PC133 Modules  
Byte# Description  
SPD Entry Value  
Hex  
64M × 64 64M × 72  
-7.5  
80  
-7.5  
80  
0
1
2
3
Number of SPD Bytes  
Total Bytes in Serial PD  
Memory Type  
128  
256  
08  
08  
SDRAM  
13  
04  
04  
Number of Row Addresses (without BS  
bits)  
0D  
0D  
4
Number of Column Addresses  
Number of DIMM Banks  
Module Data Width  
10  
0A  
02  
40  
00  
01  
75  
54  
00  
82  
08  
00  
01  
0A  
02  
48  
00  
01  
75  
54  
02  
82  
08  
08  
01  
5
2
6
64 /72  
0
7
Module Data Width (cont’d)  
Module Interface Levels  
SDRAM Cycle Time at CL = 3  
8
LVTTL  
7.5 ns  
9
10  
11  
12  
13  
14  
15  
SDRAM Access Time from Clock at CL = 3 5.4 ns  
DIMM Config  
none/ECC  
Refresh Rate/Type  
Self-Refresh, 7.8 µs  
SDRAM Width, Primary  
Error Checking SDRAM Data Width  
Minimum Clock Delay for Back-to-Back  
Random Column Address  
Burst Length Supported  
Number of SDRAM Banks  
Supported CAS Latencies  
CS Latencies  
x8  
na / x8  
tCCD = 1 CLK  
16  
17  
18  
19  
20  
21  
22  
23  
1, 2, 4 & 8  
4
0F  
04  
0F  
04  
06  
01  
01  
00  
0E  
A0  
CAS latency = 2 & 3 06  
CS latency = 0  
01  
01  
WE Latencies  
Write latency = 0  
SDRAM DIMM Module Attributes  
SDRAM Device Attributes: General  
non buffered/non reg. 00  
V
DD tol +/– 10%  
0E  
A0  
Min. Clock Cycle Time at CAS Latency = 2 10.0 ns  
for HYS64//72V64220GU-7.5-C2  
24  
Max. Data Access Time from Clock for  
CL = 2  
6.0 ns  
60  
60  
25  
26  
Minimum Clock Cycle Time at CL = 1  
not supported  
FF  
FF  
FF  
FF  
Maximum Data Access Time from Clock at not supported  
CL = 1  
27  
28  
Minimum Row Precharge Time  
20 ns  
14  
0F  
14  
0F  
Minimum Row Active to Row Active Delay 15  
tRRD  
29  
30  
31  
32  
Minimum RAS to CAS Delay tRCD  
Minimum RAS Pulse Width tRAS  
Module Bank Density (per bank)  
SDRAM Input Setup Time  
20 ns  
14  
2D  
40  
15  
14  
2D  
40  
15  
45 ns  
256 MByte  
1.5 ns  
INFINEON Technologies  
11  
3.01  
HYS 64/72V64220GU  
SDRAM-Modules  
SPD-Table for PC133 Modules (cont’d)  
Byte# Description  
SPD Entry Value  
Hex  
64M × 64 64M × 72  
-7.5  
08  
-7.5  
08  
33  
34  
35  
SDRAM Input Hold Time  
0.8 ns  
1.5 ns  
0.8 ns  
–
SDRAM Data Input Hold Time  
SDRAM Data Input Setup Time  
15  
15  
08  
08  
36-61 Superset Information (may be used in  
future)  
FF  
FF  
62  
63  
SPD Revision  
Revision 1.2  
12  
37  
12  
49  
Checksum for Bytes 0 - 62  
for HYS64/72V64220GU-7.5-C2  
–
64-125 Manufacturers Information  
(FFH if not used)  
–
XX  
64  
XX  
64  
126  
127  
Frequency Specification  
100 MHz Support Details  
for HYS64/72V64220GU-7.5-C2  
Unused Storage Locations  
–
–
FF  
FF  
FF  
FF  
128+  
INFINEON Technologies  
12  
3.01  
HYS 64/72V64220GU  
SDRAM-Modules  
SPD-Table for PC100 Modules  
Byte# Description  
SPD Entry Value  
Hex  
64M × 64 64M × 72  
-8  
-8  
0
1
2
3
Number of SPD Bytes  
Total Bytes in Serial PD  
Memory Type  
128  
80  
08  
04  
0D  
80  
08  
04  
0D  
256  
SDRAM  
13  
Number of Row Addresses (without BS  
bits)  
4
Number of Column Addresses  
Number of DIMM Banks  
Module Data Width  
10  
0A  
02  
40  
00  
01  
A0  
60  
00  
82  
08  
00  
01  
0A  
02  
48  
00  
01  
A0  
60  
02  
82  
08  
08  
01  
5
2
6
64 / 72  
0
7
Module Data Width (cont’d)  
Module Interface Levels  
SDRAM Cycle Time at CL = 3  
8
LVTTL  
10.0 ns  
9
10  
11  
12  
13  
14  
15  
SDRAM Access Time from Clock at CL = 3 6.0 ns  
DIMM Config  
none/ECC  
Refresh Rate/Type  
Self-Refresh, 7.8 µs  
SDRAM Width, Primary  
Error Checking SDRAM Data Width  
Minimum Clock Delay for Back-to-Back  
Random Column Address  
Burst Length Supported  
Number of SDRAM Banks  
Supported CAS Latencies  
CS Latencies  
x8  
na / x8  
tCCD = 1 CLK  
16  
17  
18  
19  
20  
21  
22  
23  
24  
1, 2, 4 & 8  
0F  
04  
06  
01  
01  
0F  
04  
06  
01  
01  
00  
0E  
A0  
60  
4
CAS latency = 2 & 3  
CS latency = 0  
Write latency = 0  
WE Latencies  
SDRAM DIMM Module Attributes  
SDRAM Device Attributes: General  
non buffered/non reg. 00  
V
DD tol +/– 10%  
0E  
A0  
60  
Min. Clock Cycle Time at CAS Latency = 2 10.0ns  
Max. Data Access Time from Clock for  
CL = 2  
6.0 ns  
25  
26  
Minimum Clock Cycle Time at CL = 1  
not supported  
FF  
FF  
FF  
FF  
Maximum Data Access Time from Clock at not supported  
CL = 1  
27  
28  
Minimum Row Precharge Time  
20 ns  
14  
10  
14  
10  
Minimum Row Active to Row Active Delay 16 ns  
tRRD  
29  
30  
31  
32  
33  
Minimum RAS to CAS Delay tRCD  
Minimum RAS Pulse Width tRAS  
Module Bank Density (per bank)  
SDRAM Input Setup Time  
20 ns  
14  
32  
40  
20  
10  
14  
32  
40  
20  
10  
50 ns  
256 MByte  
2 ns  
SDRAM Input Hold Time  
1 ns  
INFINEON Technologies  
13  
3.01  
HYS 64/72V64220GU  
SDRAM-Modules  
SPD-Table for PC100 Modules  
Byte# Description  
SPD Entry Value  
Hex  
64M × 64 64M × 72  
-8  
-8  
34  
35  
SDRAM Data Input Setup Time  
SDRAM Data Input Hold Time  
2 ns  
1 ns  
–
20  
10  
FF  
20  
10  
FF  
36-61 Superset Information (may be used in  
future)  
62  
63  
SPD Revision  
Revision 1.2  
12  
9A  
XX  
64  
FF  
FF  
12  
Checksum for Bytes 0 - 62  
–
AC  
XX  
64  
64-125 Manufacturers Information  
–
126  
Frequency Specification  
100 MHz Support Details  
Unused Storage Locations  
100 MHz  
127  
–
–
FF  
FF  
128+  
INFINEON Technologies  
14  
3.01  
HYS 64/72V64220GU  
SDRAM-Modules  
Package Outlines  
L-DIM-168-30 (JEDEC MO-161-BA)  
SDRAM DIMM Module Package  
HYS 64/72V64220GU  
133.35  
127.35  
4 max.  
*)  
3
1
10  
11  
6.35  
40  
41  
6.35  
84  
1.27  
3
1.27  
42.18  
91 x 1.27 = 115.57  
2
85 94  
95  
124 125  
168  
*)  
3
3 min.  
Detail of Contacts  
*) on ECC modules only  
Note: All tolerances according to JEDEC standard  
1
1.27  
L-DIM-168-30  
INFINEON Technologies  
15  
3.01  
HYS 64/72V64220GU  
SDRAM-Modules  
Change List:  
14.1.1999  
Input capacitances adjusted  
18.4.1999  
-8A speed sort added  
Infineon logo added  
SPD codes updated according to new 256M speedsorts  
Some ICC current values changed due to new inputs  
PC133 merged into this datasheet  
12.5.99  
3.8.99  
23.8.99  
6.9.99  
Byte 126 changed to 64h for PC133 modules  
Template from R&L  
20.10.99  
2.12.99  
20.1.2000  
10.3.2000  
CL=2 max. frequency changed to 83 Mhz for -7.5 modules  
Some timing parameters adjusted according to INTELs PC133 specification  
Capacitance values for x72 adjusted (new measurements)  
Implemented differences between 256Mbit S20 and S17 PC133 modules  
256Mbit S20 based PC133 modules are backward compatible to PC100 3-2-2  
256Mbit S17 based modules are backwards compatible to PC100-2-2-2  
leading to changes in SPD code of bytes 23, 63 (checksum) and 126  
TPCR issued  
10.5.2000  
5.03.2001  
Reference to JEDEC MO-161-BA added  
-8A and -8B speed sorts removed  
PC133 timing parameters only for 256M S17 and later versions  
References to 256M S20 removed  
ICC currents according to 256M S17 datasheet  
INFINEON Technologies  
16  
3.01  
厂商 型号 描述 页数 下载

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