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HYS64V32220GCDL-8

型号：

HYS64V32220GCDL-8

描述：

64位SDRAM模块\n[ x64 SDRAM Module ]

品牌：

ETC[ ETC ]

页数：

16 页

PDF大小：

144 K

下载PDF手册
3.3V SDRAM Modules  
HYS64V32220GCDL  
144 pin SO-DIMM SDRAM Modules  
PC100 & PC133  
256MB density in COB technique  
• 144 Pin Eight Byte Small Outline Dual-In-Line Synchronous DRAM Modules  
for notebook applications  
• Two bank 32M x 64 non-parity module organisation  
• suitable for use in PC100 and PC133 applications  
• Performance:  
-7.5  
-8  
PC133  
3-3-3  
PC100  
2-2-2  
Units  
fCK  
tAC  
Clock frequency (max.)  
133  
5.4  
100  
6
MHz  
ns  
Clock access time  
CAS latency = 2 & 3  
• Single +3.3V(± 0.3V ) power supply  
• Programmable CAS Latency, Burst Length and Wrap Sequence  
(Sequential & Interleave)  
• Auto Refresh (CBR) and Self Refresh  
• Decoupling capacitors mounted on substrate  
• All inputs, outputs are LVTTL compatible  
2
• Serial Presence Detect with E PROM  
• Uses COB (“Chip-on-Board”) technique  
• 4096 refresh cycles every 64 ms  
• Gold contact pad  
• This module family is fully pin and functional compatible  
with the latest INTEL SO-DIMM specification  
Semiconductor Group  
1
172.99  
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HYS64V32220GCDL  
144 pin SO-DIMM SDRAM Modules  
This INFINEON module is an industry standard 144 pin 8-byte Synchronous DRAM (SDRAM) Small  
Outline Dual In-line Memory Modules (SO-DIMM) which are organised as 32Mx64 high speed  
memory arrays designed for use in non-parity applications. These SO-DIMMs use COB (“Chip-on-  
Board”) technology. Decoupling capacitors are mounted on the board.  
2
The DIMMs use optional serial presence detects implemented via a serial E PROM using the two  
2
pin I C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128  
bytes are available to the end user.  
All INFINEON 144-pin SO-DIMMs provide a high performance, flexible 8-byte interface in a 67,5  
mm long footprint.  
Product Spectrum:  
SDRAMs RowAddr.  
used  
Bank  
Select  
Column Refresh Period  
Addr.  
32M x 64  
32M x 64  
HYS64V32220GCDL-7.5 16 16Mx8  
HYS64V322220GCDL-8 16 16Mx8  
12  
12  
BA0, BA1  
BA0, BA1  
10  
10  
4k  
4k  
64 ms  
64 ms  
Note: All partnumbers end with a place code (not shown), designating the die revision. Consult factory for current  
revision. Example: HYS64V32220GCDL-8-C, indicating Rev.C dies are used for SDRAM components.  
Card Dimensions:  
Organisation  
32M x 64  
PCB-Board  
L x H x T [mm]  
L-DIM-144-Cx  
67.60 x TBD x 3.80  
Pin Names  
A0-A11  
BA0,BA1  
DQ0 - DQ63  
RAS  
Address Inputs  
Bank Selects  
Data Input/Output  
Row Address Strobe  
Column Address Strobe  
Read / Write Input  
Clock Enable  
CAS  
WE  
CKE0  
CLK0  
Clock Input  
DQMB0 - DQMB7  
CS0 - CS3  
Vcc  
Data Mask  
Chip Select  
Power (+3.3 Volt)  
Ground  
Vss  
SCL  
Clock for Presence Detect  
SDA  
Serial Data Out for Presence Detect  
No Connection  
N.C.  
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HYS64V32220GCDL  
144 pin SO-DIMM SDRAM Modules  
Pin Configuration  
Front  
Side  
Back  
Side  
Front  
Side  
Back  
Side  
PIN #  
PIN #  
PIN #  
PIN #  
1
VSS  
2
VSS  
73  
NC  
Vss  
NC  
NC  
Vcc  
74  
CLK1  
3
DQ0  
DQ1  
DQ2  
DQ3  
VCC  
DQ4  
DQ5  
DQ6  
DQ7  
Vss  
4
DQ32  
DQ33  
DQ34  
DQ35  
Vcc  
75  
76  
Vss  
5
6
77  
78  
NC  
7
8
79  
80  
NC  
9
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
38  
40  
42  
44  
46  
48  
50  
52  
54  
56  
58  
60  
62  
64  
66  
68  
70  
72  
81  
82  
Vcc  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
35  
37  
39  
41  
43  
45  
47  
49  
51  
53  
55  
57  
59  
61  
63  
65  
67  
69  
71  
83  
DQ16  
DQ17  
DQ18  
DQ19  
Vss  
84  
DQ48  
DQ49  
DQ50  
DQ51  
Vss  
DQ36  
DQ37  
DQ38  
DQ39  
Vss  
85  
86  
87  
88  
89  
90  
91  
92  
93  
DQ20  
DQ21  
DQ22  
DQ23  
Vcc  
94  
DQ52  
DQ53  
DQ54  
DQ55  
Vcc  
DQMB0  
DQMB1  
Vcc  
DQMB4  
DQMB5  
Vcc  
95  
96  
97  
98  
99  
100  
102  
104  
106  
108  
110  
112  
114  
116  
118  
120  
122  
124  
126  
128  
130  
132  
134  
136  
138  
140  
142  
144  
A0  
A3  
101  
103  
105  
107  
109  
111  
113  
115  
117  
119  
121  
123  
125  
127  
129  
131  
133  
135  
137  
139  
141  
143  
A1  
A4  
A6  
A7  
A2  
A5  
A8  
BA0  
Vss  
Vss  
Vss  
Vss  
DQ8  
DQ9  
DQ10  
DQ11  
Vcc  
DQ40  
DQ41  
DQ42  
DQ43  
Vcc  
A9  
BA1  
A10  
A11  
Vcc  
Vcc  
DQMB2  
DQMB3  
Vss  
DQMB6  
DQMB7  
Vss  
DQ12  
DQ13  
DQ14  
DQ15  
Vss  
DQ44  
DQ45  
DQ46  
DQ47  
Vss  
DQ24  
DQ25  
DQ26  
DQ27  
Vcc  
DQ56  
DQ57  
DQ58  
DQ59  
Vcc  
NC  
NC  
NC  
NC  
DQ28  
DQ29  
DQ30  
DQ31  
Vss  
DQ60  
DQ61  
DQ62  
DQ63  
Vss  
CLK0  
Vcc  
CKE0  
Vcc  
RAS  
WE  
CAS  
CKE1  
(A12)  
(A13)  
CS0  
CS1  
SDA  
SCL  
Vcc  
Vcc  
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HYS64V32220GCDL  
144 pin SO-DIMM SDRAM Modules  
CS1  
CS0  
CS  
CS  
CS  
CS  
DQM  
DQM  
DQMB0  
DQ(7:0)  
DQM  
DQM  
DQMB4  
DQ0-DQ7  
DQ0-DQ7  
DQ0-DQ7  
DQ0-DQ7  
DQ(39:32)  
DQM  
DQM  
DQM  
DQM  
DQMB1  
DQMB5  
DQ(15:8)  
DQ(47:40)  
DQ0-DQ7  
DQ0-DQ7  
DQ0-DQ7  
DQ0-DQ7  
D6  
D0  
D4  
D2  
CS  
CS  
CS  
CS  
DQMB2  
DQM  
DQM  
DQM  
DQM  
DQMB6  
DQ(23:16)  
DQ(55:48)  
DQ0-DQ7  
DQ0-DQ7  
DQ0-DQ7  
DQ0-DQ7  
DQMB3  
DQM  
DQM  
DQMB7  
DQM  
DQM  
DQ(31:24)  
DQ(63:56)  
DQ0-DQ7  
DQ0-DQ7  
D5  
DQ0-DQ7  
DQ0-DQ7  
D7  
D1  
D3  
D0 - D7  
A0-A11,BA0,BA1  
VDD  
E2PROM (256wordx8bit)  
D0 - D7  
D0 - D7  
SA0  
SA1  
C
VSS  
SA2  
SCL  
SDA  
RAS, CAS, WE  
D0 - D15  
CKE0  
CKE1  
D0 - D3  
D4 - D7  
4 SDRAM  
4 SDRAM  
CLK0  
CLK1  
Note: 1. DQ wiring may differ than describes in this  
drawing, however DQ/DQMB/CKE/CS relationship  
must be maintained as shown.  
2. In this design each of the D0 - D7 components  
are represented by two 16M x 8 chips. These two  
chips effectively work as a single 16M x 16 device.  
Block Diagram for two bank 32M x 64 SDRAM DIMM - Module  
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HYS64V32220GCDL  
144 pin SO-DIMM SDRAM Modules  
DC Characteristics  
TA = 0 to 70 °C; VSS = 0 V; VDD,VDDQ = 3.3 V ± 0.3 V  
Parameter  
Symbol  
Limit Values  
Unit  
min.  
max.  
Vcc+0.3  
0.8  
Input high voltage  
VIH  
VIL  
2.0  
– 0.5  
2.4  
V
Input low voltage  
V
Output high voltage (IOUT = – 4.0 mA)  
Output low voltage (IOUT = 4.0 mA)  
VOH  
VOL  
II(L)  
–
V
–
0.4  
V
Input leakage current, any input  
– 20  
20  
µA  
(0 V < VIN < 3.6 V, all other inputs = 0 V)  
Output leakage current  
IO(L)  
– 20  
20  
µA  
(DQ is disabled, 0 V < VOUT < VCC)  
Capacitance  
TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz  
Parameter  
Symbol  
Limit  
Unit  
Values  
16M x 64  
max.  
Input capacitance (A0 to A11, BA0, BA1)  
Input capacitance (RAS, CAS, WE)  
Input Capacitance (CLK0, CLK1)  
Input capacitance (CS0, CS1)  
CI1  
CI2  
CI3  
CI4  
CI5  
CI6  
CIO  
65  
75  
58  
40  
15  
50  
18  
8
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
Input capacitance (DQMB0-DQMB7)  
Input capacitance (CKE0, CKE1)  
Input / Output capacitance (DQ0-DQ63)  
Input Capacitance (SCL,SA0-2)  
Input/Output Capacitance  
C
sc  
sd  
C
10  
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HYS64V32220GCDL  
144 pin SO-DIMM SDRAM Modules  
o
Operating Currents per memory bank (T = 0 to 70 C, Vdd = 3.3V ± 0.3V  
A
(Recommended Operating Conditions unless otherwise noted)  
Symb.  
32Mx64  
256Mbyte  
Note  
Parameter & Test Condition  
OPERATING CURRENT  
trc=trcmin., tck=tckmin.  
ICC1  
960  
12  
mA  
mA  
1
1
Ouputs open, Burst Length = 4, CL=3  
All banks operated in random access,  
all banks operated in ping-pong manner  
to maximize gapless data access  
PRECHARGE STANDBY CURRENT  
in Power Down Mode  
tck = min.  
ICC2P  
tck = Infinity  
tck = min.  
ICC2PS  
ICC2N  
8
mA  
mA  
1
1
CS =VIH (min.), CKE<=Vil(max)  
PRECHARGE STANDBY CURRENT  
in Non-Power Down Mode  
280  
tck = Infinity  
ICC2NS  
40  
360  
64  
mA  
mA  
mA  
1
1
1
CS = VIH (min.), CKE>=Vih(min)  
NO OPERATING CURRENT  
CKE>=VIH(min.) ICC3N  
CKE<=VIL(max.) ICC3P  
tck = min., CS = VIH(min),  
active state ( max. 4 banks)  
BURST OPERATING CURRENT  
tck = min.,  
Read command cycling  
ICC4  
ICC5  
960  
mA 1,2  
AUTO REFRESH CURRENT  
tck = min.,  
1
1360  
mA  
Auto Refresh command cycling  
SELF REFRESH CURRENT  
Self Refresh Mode, CKE=0.2V  
ICC6  
6.4  
mA  
1
Notes:  
1. These parameters depend on the cycle rate. These values are measured at 100 MHz operation frequency.  
Input signals are changed once during tck, excepts for ICC6 and for standby currents when tck=infinity.  
2. These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3  
and BL=4 is assumed and the VDDQ current is excluded.  
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HYS64V32220GCDL  
144 pin SO-DIMM SDRAM Modules  
AC Characteristics 1)2)  
TA = 0 to 70 °C; VSS = 0 V; Vdd = 3.3 V ± 0.3 V, tT = 1 ns  
Symbol  
Unit  
Parameter  
Limit Values  
-7.5  
PC133-333  
-8  
PC100-222  
min.  
max.  
min.  
max.  
Clock and Access Time  
Clock Cycle Time  
CAS Latency = 3  
CAS Latency = 2  
7.5  
10  
–
–
10  
10  
–
–
ns  
ns  
tCK  
tCK  
tAC  
Clock Frequency  
CAS Latency = 3  
CAS Latency = 2  
–
–
133  
100  
–
–
100 MHz  
100 MHz  
Access Time from Clock  
CAS Latency = 3  
CAS Latency = 2  
2,  
3
–
–
5.4  
6
–
–
6
6
ns  
ns  
Clock High Pulse Width  
tCH  
tCL  
tT  
2.5  
2.5  
0.3  
–
–
3
3
–
–
ns  
ns  
ns  
Clock Low Pulse Width  
Transition time  
1.2  
0.5  
10  
Setup and Hold Parameters  
Input Setup Time  
4
4
4
4
tIS  
1.5  
0.8  
–
–
–
1
–
–
2
1
–
1
2
–
–
1
–
–
ns  
Input Hold Time  
tIH  
ns  
Power Down Mode Entry Time  
Power Down Mode Exit Setup Time  
Mode Register Set-up time  
tSB  
tPDE  
tRSC  
CLK  
CLK  
CLK  
1
2
Common Parameters  
Row to Column Delay Time  
Row Precharge Time  
Row Active Time  
5
5
5
5
5
tRCD  
tRP  
tRAS  
tRC  
20  
20  
45  
67  
14  
–
–
20  
20  
50  
70  
16  
–
–
ns  
ns  
ns  
ns  
ns  
100k  
–
100k  
–
Row Cycle Time  
Activate(a) to Activate(b) Command  
period  
tRRD  
–
–
CAS(a) to CAS(b) Command period  
tCCD  
1
–
1
–
CLK  
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HYS64V32220GCDL  
144 pin SO-DIMM SDRAM Modules  
Symbol  
Unit  
Parameter  
Limit Values  
-7.5  
PC133-333  
-8  
PC100-222  
min.  
max.  
min.  
max.  
Refresh Cycle  
Refresh Period  
(4096 cycles)  
tREF  
–
1
64  
–
–
1
64  
–
ms  
6
7
Self Refresh Exit Time  
tSREX  
CLK  
Read Cycle  
Data Out Hold Time  
tOH  
tLZ  
3
1
3
–
–
–
7
2
3
0
3
–
–
–
8
2
ns  
Data Out to Low Impedance Time  
Data Out to High Impedance Time  
DQM Data Out Disable Latency  
ns  
tHZ  
ns  
tDQZ  
CLK  
Write Cycle  
Data Input to Precharge  
(write recovery)  
tWR  
2
0
–
–
2
0
–
–
CLK  
CLK  
DQM Write Mask Latency  
tDQW  
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144 pin SO-DIMM SDRAM Modules  
Notes:  
1. An initial pause of 100µs is required after power-up, then a Precharge All Banks command must  
be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can  
begin.  
2. AC timing tests have V = 0.4 V and V = 2.4 V with the timing referenced to the 1.4 V crossover  
il  
ih  
point. The transition time is measured between V and V . All AC measurements assume t =1ns  
ih  
il  
T
with the AC output load circuit shown.Specified tac and toh parameters are measured with a 50  
pF only, without any resistive termination and with a input signal of 1V / ns edge rate between  
0.8V and 2.0 V.  
tCH  
2.4 V  
0.4 V  
CLOCK  
tT  
tCL  
tHOLD  
tSETUP  
INPUT  
1.4 V  
tAC  
tAC  
tLZ  
tOH  
I/O  
50 pF  
OUTPUT  
1.4 V  
tHZ  
Measurement conditions for  
tac and toh  
SPT03404  
3. If clock rising time is longer than 1ns, a time (t -0.5) ns has to be added to this parameter.  
T
4. If t is longer than 1ns, a time (t -1) ns has to be added to this parameter.  
T
T
5. Any time that the refresh Period has been exceeded, a minimum of two Auto (CRB) Refresh  
commands must be given to “wake-up“ the device.  
6. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after  
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied  
once the Self Refresh Exit command is registered.  
7. Referenced to the time which the output achieves the open circuit condition, not to output voltage  
levels.  
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HYS64V32220GCDL  
144 pin SO-DIMM SDRAM Modules  
Serial Presence Detects:  
A serial presence detect storage device - E2PROM - is assembled onto the module. Information about the module  
configuration, speed, etc. is written into the E2PROM device during module production using a serial presence  
detect protocol ( I2C synchronous 2-wire bus)  
SPD-Table for PC100 2-2-2 SO-DIMM Modules:  
Byte#  
Description  
SPD Entry  
Value  
Hex  
32Mx64  
-8  
0
1
2
3
Number of SPD bytes  
128  
256  
80  
08  
04  
0C  
Total bytes in Serial PD  
Memory Type  
SDRAM  
Number of Row Addresses  
(without BS)  
4
5
Number of Column Addresses  
Number of DIMM Banks  
Module Data Width  
10  
02  
40  
00  
01  
A0  
60  
1 / 2  
64  
6
7
Module Data Width (cont’d)  
Module Interface Levels  
SDRAM Cycle Time at CL=3  
0
8
LVTTL  
10.0 ns  
6.0 ns  
9
10  
SDRAM Access time from Clock at  
CL=3  
11  
12  
Dimm Config (Error Det/Corr.)  
Refresh Rate/Type  
none  
00  
80  
Self-Refresh,  
15.6µs  
13  
14  
15  
SDRAM width, Primary  
x16  
10  
00  
01  
Error Checking SDRAM data width  
n/a / x8  
Minimum clock delay for back-to-  
back random column address  
tccd = 1 CLK  
16  
Burst Length supported  
1, 2, 4, 8 & full  
page  
8F  
17  
18  
19  
20  
Number of SDRAM banks  
Supported CAS Latencies  
CS Latencies  
2
04  
06  
01  
01  
2, & 3  
CS latency = 0  
WE Latencies  
Write latency =  
0
21  
22  
SDRAM DIMM module attributes  
SDRAM Device Attributes :General  
SDRAM Cycle Time at CL = 2  
non buffered/  
non reg.  
00  
0E  
Vcc tol +/-  
10%  
23  
24  
10.0 ns  
6.0 ns  
A0  
60  
SDRAM Access Time from Clock at  
CL=2  
25  
26  
SDRAM Cycle Time at CL = 1  
not supported  
not supported  
FF  
FF  
SDRAM Access Time from Clock at  
CL=1  
27  
Minimum Row Precharge Time  
20 ns  
14  
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HYS64V32220GCDL  
144 pin SO-DIMM SDRAM Modules  
SPD-Table (cont’d):  
Byte#  
Description  
SPD Entry  
Value  
Hex  
32Mx64  
-8  
28  
Minimum Row Active to Row Active  
delay  
16 ns  
10  
29  
30  
31  
32  
33  
34  
35  
Minimum RAS to CAS delay  
Minimum Ras pulse width  
Module Bank Density (per bank)  
SDRAM input setup time  
20 ns  
45 ns  
128 MB  
2 ns  
14  
2D  
20  
20  
SDRAM input hold time  
1 ns  
10  
SDRAM data input setup time  
SDRAM data input hold time  
2 ns  
20  
1 ns  
10  
36-61 Superset information  
FF  
12  
62  
63  
SPD Revision  
Revision 1.2  
Checksum for bytes 0 - 62  
TBD  
FF  
64- Manufactures’s information (optional)  
125  
126 Frequency Specification  
127 Details  
PC100  
64  
C7  
FF  
128+ Unused storage locations  
Infineon Technologies  
11  
12.99  
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HYS64V32220GCDL  
144 pin SO-DIMM SDRAM Modules  
SPD-Table for PC133 3-3-3 SO-DIMM Modules:  
Byte#  
Description  
SPD Entry  
Value  
Hex  
32Mx64  
-7.5  
0
1
2
3
Number of SPD bytes  
128  
256  
80  
08  
04  
0C  
Total bytes in Serial PD  
Memory Type  
SDRAM  
Number of Row Addresses  
(without BS)  
4
5
Number of Column Addresses  
Number of DIMM Banks  
Module Data Width  
10  
02  
40  
00  
01  
75  
54  
1 / 2  
64  
6
7
Module Data Width (cont’d)  
Module Interface Levels  
SDRAM Cycle Time at CL=3  
0
8
LVTTL  
7.5 ns  
5.4 ns  
9
10  
SDRAM Access time from Clock at  
CL=3  
11  
12  
Dimm Config (Error Det/Corr.)  
Refresh Rate/Type  
none  
00  
80  
Self-Refresh,  
15.6µs  
13  
14  
15  
SDRAM width, Primary  
x16  
10  
00  
01  
Error Checking SDRAM data width  
n/a / x8  
Minimum clock delay for back-to-  
back random column address  
tccd = 1 CLK  
16  
Burst Length supported  
1, 2, 4, 8 & full  
page  
8F  
17  
18  
19  
20  
Number of SDRAM banks  
Supported CAS Latencies  
CS Latencies  
2
04  
06  
01  
01  
2, & 3  
CS latency = 0  
WE Latencies  
Write latency =  
0
21  
22  
SDRAM DIMM module attributes  
SDRAM Device Attributes :General  
SDRAM Cycle Time at CL = 2  
non buffered/  
non reg.  
00  
0E  
Vcc tol +/-  
10%  
23  
24  
10.0 ns  
6.0 ns  
A0  
60  
SDRAM Access Time from Clock at  
CL=2  
25  
26  
SDRAM Cycle Time at CL = 1  
not supported  
not supported  
FF  
FF  
SDRAM Access Time from Clock at  
CL=1  
27  
Minimum Row Precharge Time  
20 ns  
14  
Infineon Technologies  
12  
12.99  
Powered by ICminer.com Electronic-Library Service CopyRight 2003  
HYS64V32220GCDL  
144 pin SO-DIMM SDRAM Modules  
SPD-Table (cont’d):  
Byte#  
Description  
SPD Entry  
Value  
Hex  
32Mx64  
-7.5  
28  
Minimum Row Active to Row Active  
delay  
14 ns  
0F  
29  
30  
31  
32  
33  
34  
35  
Minimum RAS to CAS delay  
Minimum Ras pulse width  
Module Bank Density (per bank)  
SDRAM input setup time  
20 ns  
45 ns  
14  
2D  
20  
128 MB  
1.5 ns  
0.8 ns  
1.5 ns  
0.8 ns  
15  
SDRAM input hold time  
08  
SDRAM data input setup time  
SDRAM data input hold time  
15  
08  
36-61 Superset information  
FF  
12  
62  
63  
SPD Revision  
Revision 1.2  
Checksum for bytes 0 - 62  
TBD  
FF  
64- Manufactures’s information (optional)  
125  
126 Frequency Specification  
127 Details  
PC133  
85  
C7  
FF  
128+ Unused storage locations  
Infineon Technologies  
13  
12.99  
Powered by ICminer.com Electronic-Library Service CopyRight 2003  
HYS64V32220GCDL  
144 pin SO-DIMM SDRAM Modules  
256 MByte SO-DIMM Module package (PRELIMINARY !!)  
(144 pin, dual read-out, single in-line memory module)  
67.6  
63.6  
3.8  
1
59  
61  
143  
144  
1±  
0.1  
3.3  
23.2  
24.5  
32.8  
2.5  
4.6  
±0.1  
1.5  
60  
1.8  
3.7  
2
62  
Detail of Contacts  
±0.05  
0.6  
0.8  
GLD09192  
Infineon Technologies  
14  
12.99  
Powered by ICminer.com Electronic-Library Service CopyRight 2003  
HYS64V32220GCDL  
144 pin SO-DIMM SDRAM Modules  
Infineon Technologies  
15  
12.99  
Powered by ICminer.com Electronic-Library Service CopyRight 2003  
HYS64V32220GCDL  
144 pin SO-DIMM SDRAM Modules  
Rev Changes:  
9.8.1999  
3.12.99  
First version  
256MByte COB-SO-DIMM based on 128 Mb (16M x 8) chips  
some PC133 timing parameters changed according to INTELs PC133 specifi-  
cation  
Infineon Technologies  
16  
12.99  
Powered by ICminer.com Electronic-Library Service CopyRight 2003  
厂商 型号 描述 页数 下载

INFINEON

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 		HYS6472V16200GU 3.3 V 16M ×64 /72-位SDRAM模块3.3 V 32M ×64 /72-位SDRAM模块3.3 V 64M ×64 /72-位SDRAM模块[ 3.3 V 16M x 64/72-Bit SDRAM Modules 3.3 V 32M x 64/72-Bit SDRAM Modules 3.3 V 64M x 64/72-Bit SDRAM Modules ] 17 页

INFINEON

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INFINEON

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ETC

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INFINEON

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INFINEON

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QIMONDA

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INFINEON

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