HYS64/72D32000/64020GU
Unbuffered DDR-I SDRAM-Modules
Operating, Standby and Refresh Currents (PC2100)
Parameter/Condition
DRAM Technology:
256Mbit
typ. typ.
typ.
680
typ.
Operating Current - One bank Active - Precharge;
tRC = tRC MIN; tCK = 7.5 ns; DQ, DM, and DQS inputs changing
once per clock cycle; address and control inputs changing once
per every two cycles
765
1104 1242 mA 1,3
1128 1269 mA 1,3
IDD0
Operating Current - One bank Active / Read / Precharge;
Burst = 4; Reads; Refer to the detailed test conditions in the
component datasheet
704
104
792
117
IDD1
Precharge Power-Down Standby Current: all banks idle;
power-down mode; CKE ≤ VIL MAX; tCK = 7.5 ns
208
464
234
522
mA 1,4
mA 1,4
IDD2P
Precharge Floating Standby Current: CS ≥ VIH MIN, all banks
idle; CKE ≥ VIH MIN; tCK = 7.5 ns, address and other control
inputs changing once per clock cycle,
232
261
IDD2F
VIN = VREF for DQ, DQS and DM.
Precharge Quiet Standby Current: CS ≥ VIH MIN, all banks
idle; CKE ≥ VIH MIN; tCK = 7.5 ns,address and other control inputs 216
stable at ≥ VIH MIN or ≤ VIL MAX; VIN = VREF for DQ, DQS and DM.
243
117
432
208
486
234
mA 1,4
mA 1,4
IDD2Q
Active Power-Down Standby Current: one bank active;
104
IDD3P
power-down mode; CKE ≤ VIL MAX; tCK = 7.5 ns
Active Standby Current: one bank; active / precharge;CS ≥
VIH MIN; CKE ≥ VIH MIN; tRC = tRAS MAX; tCK = 7.5 ns; DQ, DM, and
424
477
848
954
mA 1,4
IDD3N
IDD4R
IDD4W
DQS inputs changing twice per clock cycle; address and control
inputs changing once per clock cycle
Operating Current - Burst Read: one bank; Burst = 2; reads;
continuous burst; address and control inputs changing once per
1088 1224 1512 1701 mA 1,3
clock cycle; DQ and DQS outputs changing twice per clock
cycle; CL = 2; tCK = 7.5 ns;IOUT = 0mA
Operating Current - Burst Write: one bank; Burst = 2; writes;
continuous burst; address and control inputs changing once per
clock cycle; DQ and DQS inputs changing twice per clock cycle;
CL = 2; tCK = 7.5 ns
1112 1251 1536 1728 mA 1,3
1352 1521 2704 3042 mA 1,4
Auto-Refresh Current: tRC = tRFC MIN, distributed refresh
Self-Refresh Current: CKE ≤ 0.2V
IDD5
IDD6
15.2
17.1
30.4
34.2 mA 1,2,4
Operating Current - Four bank operation; four bank inter-
leaving with BL=4; Refer to the detailed test conditions in the
component datasheet
1576 1773 2000 2250 mA 1,3
IDD7
1. IDD currents are measured after the device is properly initialized. Typical values are obtained from characteri-
sation data measured at VDD = 2.5 V and R.T. with an input slew rate = 1V/ns.
2. Enables on-chip refresh and address counters.
3. For two bank modules only : the other bank is in IDD3N mode
4. For two bank modules only : both banks operate in the same current mode
INFINEON Technologies
12
12.01
