Internal Memory-System
Versatile Interfaces
•
•
•
•
16kByte RAM, two 2kByte instruction/data caches
8kByte Mask ROM (Boot loader)
128kByte SRAM
32kByte Shared SRAM (Ethernet)
32-Bit data and address bus
•
Dual 10/100 Mbit/s Ethernet MAC with two MII and
one Ethernet PHY supporting real-time standard
(IEEE 1588), also fully compliant with Ethernet
standards such as IEEE 802.3, 802.3u, and ANSI
X3.263-1995 (FDDI-TP- PMD)
•
•
USB 1.1 device controller with integrated
transceiver, supports up to 12Mbit/s serial data
transmission
Key Features
•
4 internal busses with multi channel DMA controller
o
Peripheral Bus with variable frequency, to reduce
power consumption
Multi-master/multi-slave high frequency System Bus
Ethernet Bus
•
•
PCM Interface connecting to an external IOM-2 bus
Controller Area Network (CAN) Interface,
compatible to CAN 2.0 and extended format, and
Philips SJA1000
Asynchronous Transfer Mode (ATM) – UTOPIA
Level-2 Interface, for connection of up to 3 external
ATM physical layer controller (PHYs)
Multiplexed Processor Interface (MPI) configurable
for CPU independent external transfers, accessible
directly by the CPU or a DMA, connects up to 15
external Power Line physical layer controllers for
TDM transmission
o
o
o
Coprocessor Bus
•
•
•
Direct Memory Access Controller with 6
independent configurable channels
Memory Management Unit (MMU)
Time Processor Unit (TPU) programmable timer
with one 32-bit counter and two 16 bit counters
Efficient Power Management
•
•
•
•
Management Unit including reset manager, clock
manager, configuration unit
•
Communication Engine, programmable serial
communication providing 16 I/O lines or software
controlled general purpose I/Os, providing eight
communication channels and commands including
UART, IrDA, I2C Master and Slave, Synchronous
Communication and interface options to various
devices such as A/D or D/A converters, codecs and
serial memories
•
•
Interrupt Controller
Galois Factory Coprocessor: hardware calculation
of Galois field operations
Clock Synchronization Core according to IEEE 1588
standard
YUV interface CCIR656-compliant video input
interface reassembling raw video data out of a
CCIR656 YCrCb 4:2:2 8-bit data stream
•
•
•
JTAG (Boundary Scan)
compliant to the IEEE P1149.1
Real Time Clock
Com
hyyppeerrsstotonnee
Galois
Factory
128kB
128 KB
System
System
Bus
Boot
Boot
Watch-
Mgmt.
Watch Mgmt.
Interrupt
Controller
-Engine
RISC / DSP
SRAM
SRAM
ROM
ROM
dog
-dog
Bus
Unit
•
•
Unit
E1 -32XSR™
Coprocessor
UART
UART 1,2
Controller
Controller
IrDA,
IrDA,
2
C,
I C,
Watchdog
1616KkBBRRAAMM LL11CCaacchhee
2
Memory,
TTiimmeerr RTC
CAN
16 GPIO
I/O, SDRAM
Controller
MMMMUU
LL22CCaacchhee
System Bus
Peripheral Bus
Bus Bridge SP
Bus Bridge SP
External Bus
Interface
hyNet 32XS Block Diagram
USB
PCM
IOM -2
6 channel DMA
controller
Bus
Bridge SE
Bridge SE
64 KB SRAM
32kB SRAM
YUV
1.1
Shared
Shared
Ethernet Sub-System
Ethernet Sub -System:
AATTMM
UUTTOOPPIAIA
-
TracnTesraicveneisrver
MPI
DMA
DMA FFIIFFOO
DDMMAA FIFO
MAC 1
MMIIII
SYN1588
MIIS
Bus
Bus
Con -
Controller
PHY
PHY
MMAACC00
MMIIII
troller
Development Software and Hardware Support
All necessary development software and hardware is available from Hyperstone. Available options include an inexpensive
starter-kit option as well as the Hyperstone real-time kernel (hyRTK), DSP software library (hyDSP), macro assembler,
C-compiler, debugger, file linker, library manager, and profiler.
Hyperstone AG
Hyperstone Taiwan
Line-Eid-Strasse 3
78467 Konstanz, Germany
Phone: +49 7531 98030
11F, No.183, Sec.2, Tiding Blvd.
Neihu District, Taipei, Taiwan, R.O.C.
Phone: +886 2 8751 0203
Fax:
E-mail: info@hyperstone.de
Web: www.hyperstone.com
+49 7531 51725
Fax:
E-mail: taiwan@hyperstone.com
Web: www.hyperstone.com.tw
+886 2 8797 2321
Content is subject to change without prior notice. hyNet, hyNet 32XS, hyRTK and hyDSP are trademarks of Hyperstone AG. Other brand, product or company names
are property of the respective holder. Warranties, implied or expressed as well as liablities for any damage resulting from using provided information in this document
are excluded until part of a separate written contract.
HS-Mkt-AM-005-04-01
