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CYM52KNP72V33A-15BBC

型号：

CYM52KNP72V33A-15BBC

品牌：

CYPRESS[ CYPRESS ]

页数：

24 页

PDF大小：

233 K

下载PDF手册
PRELIMINARY  
CYM52KNP72AV33  
512Kx72 Pipelined MCM with NoBL™ Architecture  
Clock Enable (CEN) and Byte Write Enables (BWSa-  
BWSh).Address and control signals are applied to the SRAM  
Features  
• NoBusLatency, no deadcyclesbetweenwriteandread  
cycles  
during one clock cycle, and two cycles later, its associated  
data occurs, either read or write.  
• Internally synchronized registered outputs eliminate  
the need to control OE  
• Single 3.3V –5% and +5% power supply VDD  
• Separate VDDQ for 3.3V or 2.5V I/O  
A
Clock Enable (CEN) pin allows operation of the  
CYM52KNP72AV33 to be suspended as long as necessary.  
All synchronous inputs are ignored when CEN is HIGH and the  
internal device registers will hold their previous values.  
• Single WE (READ/WRITE) control pin  
• Positive clock-edge triggered, address, data, and con-  
trol signal registers for fully pipelined applications  
• Interleaved or linear 4-word burst capability  
• Individual byte write (BWSa – BWSh) control (may be  
tied LOW)  
• CEN pin to enable clock and suspend operations  
• Three chip enables for simple depth expansion  
• Available in 209 fine pitch ball BGA package  
There are three chip enable pins (CE1, CE2, CE3) that allow  
the user to deselect the device when desired. If any one of  
these three are not active when ADV/LD is LOW, no new mem-  
ory operation can be initiated and any burst cycle in progress  
is stopped. However, any pending data transfers (read or write)  
will be completed. The data bus will be in high-impedance  
state two cycles after the chip is deselected or a write cycle is  
initiated.  
The CYM52KNP72AV33 has an on-chip 2-bit burst counter.  
In the burst mode, the CYM52KNP72AV33 provides four cy-  
cles of data for a single address presented to the SRAM. The  
order of the burst sequence is defined by the MODE input pin.  
The MODE pin selects between linear and interleaved burst  
sequence. The ADV/LD signal is used to load a new external  
address (ADV/LD = LOW) or increment the internal burst  
counter (ADV/LD = HIGH)  
Functional Description  
The CYM52KNP72AV33 is designed to eliminate dead cycles  
when transitions from READ to WRITE or vice versa. This  
SRAM module is optimized for 100 percent bus utilization and  
achieve Zero Bus Latency. This Synchronous Burst SRAM  
family employs high-speed, low-power CMOS designs using  
advanced single layer polysilicon, three layer metal technolo-  
gy. Each memory cell consists of six transistors.  
Output enable (OE) and burst sequence select (MODE) are  
the asynchronous signals. OE can be used to disable the out-  
puts at any given time. Four pins are used to implement JTAG  
test capabilities. The JTAG circuitry is used to serially shift data  
to and from the device. JTAG inputs use LVTTL/LVCMOS lev-  
els to shift data during this testing mode of operation.  
All synchronous inputs are gated by registers controlled by a  
positive-edge-triggered Clock Input (CLK). The synchronous  
inputs include all addresses, all data inputs, depth-expansion  
Chip Enables (CE1, CE2, and CE3), cycle start input (ADV/LD),  
Logic Block Diagram  
F/T  
CLK  
DQ  
[0:31]  
512K x 36  
TDO  
ADV/LD  
DP  
[a:d]  
A
TDI  
[0:18]  
BWS  
CEN  
CE  
CE  
CE  
[a:d]  
1
2
3
WE  
TDI  
DQ  
[32:63]  
OE  
Mode  
512K x 36  
DP  
[e:h  
TCK  
TMS  
TDO  
TDO  
BWS  
[e:h]  
Common Signals for Both  
SRAM’s  
.
Cypress Semiconductor Corporation  
Document #: 38-05093 Rev. **  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Revised August 10, 2001  
PRELIMINARY  
CYM52KNP72AV33  
Selection Guide  
150 MHz  
133 MHz  
100 MHz  
5.0  
Maximum Access Time (ns)  
3.8  
4.2  
280  
30  
Maximum Operating Current (mA)  
Maximum CMOS Standby Current (mA)  
Com’l  
310  
30  
260  
10  
Pin Configurations  
209-Ball Grid Array  
1
DQg  
DQg  
DQg  
2
3
4
5
6
7
8
9
10  
DQb  
11  
A
B
C
D
E
F
DQg  
DQg  
CE  
CE  
ADV/LD  
WE  
DQb  
DQb  
3
2
A
A
A
A
A
BWS  
NC  
NC  
DQb  
DQb  
BWS  
BWS  
BWS  
b
c
f
g
DQg  
DQg  
DPc  
DQc  
DQc  
NC  
NC  
BWS  
NC  
BWS  
CE  
BWS  
a
BWS  
DQb  
DQb  
DPb  
DQf  
DQf  
e
d
1
h
DQg  
V
NC  
OE  
V
NC  
V
SSQ  
DQb  
SSQ  
DPg  
DQc  
V
V
V
V
V
V
V
V
DD  
DDQ  
DDQ  
DDQ  
SSQ  
DDQ  
DD  
DD  
DPf  
DQf  
V
V
V
V
V
V
V
SSQ  
SS  
DD  
SSQ  
SS  
DD  
SS  
SSQ  
DDQ  
G
H
J
DQc  
DQc  
V
V
V
V
V
DDQ  
DDQ  
DQf  
DQf  
DD  
DDQ  
SSQ  
V
V
V
V
V
V
V
V
V
DQc  
DQc  
NC  
V
SSQ  
SSQ  
SS  
SS  
SSQ  
SS  
DQf  
DQf  
NC  
DQc  
NC  
V
V
V
V
V
V
DDQ  
DD  
DD  
DDQ  
DDQ  
DDQ  
DQf  
NC  
DD  
K
L
CLK  
V
CEN  
F/T  
NC  
V
SS  
SS  
NC  
NC  
DQh  
DQh  
DQh  
V
V
V
V
DDQ  
DD  
SS  
DD  
SS  
DDQ  
DDQ  
DQa  
DQa  
DQa  
DDQ  
M
N
P
R
T
V
V
V
V
V
V
V
V
DQh  
DQh  
DQh  
V
V
SSQ  
SSQ  
DDQ  
SSQ  
SS  
SSQ  
SSQ  
DQa  
DQa  
DQa  
V
V
V
V
V
DDQ  
DQh  
DQh  
DPd  
DQd  
DQd  
V
V
V
V
V
NC  
DD  
DD  
SS  
DDQ  
DDQ  
DQa  
DQa  
DPa  
DQe  
DQe  
V
V
V
V
V
V
SS  
SSQ  
DDQ  
SSQ  
SS  
SSQ  
DDQ  
SSQ  
DPh  
DQd  
DQd  
DQd  
DQd  
V
V
DDQ  
SSQ  
DD  
DD  
DDQ  
DD  
DPe  
DQe  
DQe  
DQe  
DQe  
NC  
V
NC  
NC  
NC  
A
MODE  
A
U
V
W
NC  
A
A
NC  
NC  
A
A
A1  
A
DQd  
DQd  
A
A
A
A
DQe  
DQe  
TDI  
TDO  
TCK  
A0  
A
TMS  
Document #: 38-05093 Rev. **  
Page 2 of 24  
PRELIMINARY  
CYM52KNP72AV33  
Pin Definitions  
Name  
A0  
A1  
I/O Type  
Description  
Input-  
Synchronous  
Address Inputs used to select one of the 524,288 address locations. Sampled at the  
rising edge of the CLK.  
A (2–18)  
BWSa  
BWSb  
BWSc  
BWSh  
Input-  
Synchronous  
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the  
SRAM. Sampled on the rising edge of CLK. BWSa controls DQa and DPa, BWSb  
controls DQb and DPb, BWSc controls DQc and DPc, BWSd controls DQd and DPd.  
WE  
Input-  
Synchronous  
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active  
LOW. This signal must be asserted LOW to initiate a write sequence.  
ADV/LD  
Input-  
Synchronous  
Advance/Load Input used to advance the on-chip address counter or load a new  
address. When HIGH (and CEN is asserted LOW) the internal burst counter is ad-  
vanced. When LOW, a new address can be loaded into the device for an access. After  
being deselected, ADV/LD should be driven LOW in order to load a new address.  
CLK  
CE1  
CE2  
CE3  
OE  
Input-Clock  
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified  
with CEN. CLK is only recognized if CEN is active LOW.  
Input-  
Synchronous  
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in con-  
junction with CE2 and CE3 to select/deselect the device.  
Input-  
Synchronous  
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in con-  
junction with CE1 and CE3 to select/deselect the device.  
Input-  
Synchronous  
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in con-  
junction with CE1 and CE2 to select/deselect the device.  
Input-  
Asynchronous  
Output Enable, active LOW. Combined with the synchronous logic block inside the  
device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to  
behaveas outputs. Whendeasserted HIGH, I/O pins arethree-stated, andactas input  
data pins. OE is masked during the data portion of a write sequence, during the first  
clock when emerging from a deselected state and when the device has been dese-  
lected.  
CEN  
Input-  
Synchronous  
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized  
by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting  
CEN does not deselect the device, CEN can be used to extend the previous cycle  
when required.  
DQa  
DQb  
DQc  
DQh  
I/O-  
Synchronous  
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is  
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the  
memory location specified by A[18:0] during the previous clock rise of the read cycle.  
The direction of the pins is controlled by OE and the internal control logic. When OE  
is asserted LOW, the pins can behave as outputs. When HIGH, DQa–DQd are placed  
in a three-state condition. The outputs are automatically three-stated during the data  
portion of a write sequence, during the first clock when emerging from a deselected  
state, and when the device is deselected, regardless of the state of OE.  
DPa  
DPb  
DPc  
DPh  
I/O-  
Synchronous  
BidirectionalDataParity I/Olines. Functionally, thesesignals areidenticalto DQ[31:0].  
During write sequences, DPa is controlled by BWSa, DPb is controlled by BWSb, DPc  
is controlled by BWSc, and DPd is controlled by BWSd.  
F/T  
Input  
Strap pin  
Flowthrough Input: Used as a control pin to select flowthrough or pipelined operation.  
High for Pieplined. Connect to VDD for normal operation.  
MODE  
Input  
Strap Pin  
Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved  
burstorder. PulledLOWselectsthelinearburstorder. MODEshouldnotchangestates  
during operation. When left floating MODE will default HIGH, to an interleaved burst  
order.  
TDO  
JTAG serial  
output  
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. (BGA  
Only)  
Synchronous  
Document #: 38-05093 Rev. **  
Page 3 of 24  
PRELIMINARY  
CYM52KNP72AV33  
Pin Definitions  
Name  
TDI  
I/O Type  
Description  
JTAG serial  
input  
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. (BGA Only)  
Synchronous  
TMS  
TCK  
Test Mode Select  
Synchronous  
This pin controls the Test Access Port state machine. Sampled on the rising edge of  
TCK. (BGA Only)  
JTAG serial  
output  
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. (BGA  
Only)  
Synchronous  
VDD  
Power Supply  
Power supply inputs to the core of the device.  
Power supply for the I/O circuitry.  
VDDQ  
I/O Power  
Supply  
VSS  
VSSQ  
NC  
Ground  
Ground  
-
Ground for the device. Should be connected to ground of the system.  
Ground for the I/O circuitry. Should be connected to ground of the system.  
No connects.  
Document #: 38-05093 Rev. **  
Page 4 of 24  
PRELIMINARY  
CYM52KNP72AV33  
linear burst mode, a HIGH selects an interleaved burst se-  
quence. Both burst counters use A0 and A1 in the burst se-  
quence, and will wrap-around when incremented sufficiently.  
A HIGH input on ADV/LD will increment the internal burst  
counter regardless of the state of chip enables inputs or WE.  
WE is latched at the beginning of a burst cycle. Therefore, the  
type of access (Read or Write) is maintained throughout the  
burst sequence.  
Introduction  
Functional Overview  
The CYM52KNP72AV33 is a synchronous-pipelined Burst  
NoBL SRAM module designed specifically to eliminate wait  
states during Write/Read transitions. All synchronous inputs  
pass through input registers controlled by the rising edge of  
the clock. The clock signal is qualified with the Clock Enable  
input signal (CEN). If CEN is HIGH, the clock signal is not  
recognized and all internal states are maintained. All synchro-  
nous operations are qualified with CEN. All data outputs pass  
through output registers controlled by the rising edge of the  
clock. Maximum access delay from the clock rise (tCO) is  
4.2 ns (133-MHz device).  
Single Write Accesses  
Write access are initiated when the following conditions are  
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,  
and CE3 are ALL asserted active, and (3) the write signal WE  
is asserted LOW. The address presented to Ax is loaded into  
the Address Register. The write signals are latched into the  
Control Logic block.  
Accesses can be initiated by asserting all three Chip Enables  
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock  
Enable (CEN) is active LOW and ADV/LDis asserted LOW, the  
address presented to the device will be latched. The access  
can either be a read or write operation, depending on the sta-  
tus of the Write Enable (WE). BWS[h:a] can be used to conduct  
byte write operations.  
On the subsequent clock rise the data lines are automatically  
three-stated regardless of the state of the OE input signal. This  
allows the external logic to present the data on DQ and DQP  
(DQa-h/DPa-h for CYM52KNP72AV33) . In addition, the  
address for the subsequent access (Read/Write/Deselect) is  
latched into the Address Register (provided the appropriate  
control signals are asserted).  
Write operations are qualified by the Write Enable (WE). All  
writes are simplified with on-chip synchronous self-timed write  
circuitry.  
On the next clock rise the data presented to DQ and DP (DQa-  
h/DPa-h for CYM52KNP72AV33) (or a subset for byte write  
operations, see Write Cycle Description table for details) in-  
puts is latched into the device and the write is complete.  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) simplify depth expansion.  
All operations (Reads, Writes, and Deselects) are pipelined.  
ADV/LD should be driven LOW once the device has been de-  
selected in order to load a new address for the next operation.  
The data written during the Write operation is controlled by  
BWS (BWSa-h for CYM52KNP72AV33) signals. The  
CYM52KNP72AV33 provides byte write capability that is de-  
scribed in the Write Cycle Description table. Asserting the  
Write Enable input (WE) with the selected Byte Write Select  
(BWS) input will selectively write to only the desired bytes.  
Bytes not selected during a byte write operation will remain  
unaltered. A Synchronous self-timed write mechanism has  
been provided to simplify the write operations. Byte write ca-  
pability has been included in order to greatly simplify  
Read/Modify/Write sequences, which can be reduced to sim-  
ple byte write operations.  
Single Read Accesses  
A read access is initiated when the following conditions are  
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,  
and CE3 are ALL asserted active, (3) the Write Enable input  
signal WE is deasserted HIGH, and (4) ADV/LD is asserted  
LOW. The address presented to the address inputs is latched  
into the Address Register and presented to the memory core  
and control logic. The control logic determines that a read ac-  
cess is in progress and allows the requested data to propagate  
to the input of the output register. At the rising edge of the next  
clock the requested data is allowed to propagate through the  
output register and onto the data bus within 3.8 ns (150-MHz  
device) provided OE is active LOW. After the first clock of the  
read access the output buffers are controlled by OE and the  
internal control logic. OE must be driven LOW in order for the  
device to drive out the requested data. During the second  
clock, a subsequent operation (Read/Write/Deselect) can be  
initiated. Deselecting the device is also pipelined. Therefore,  
when the SRAM is deselected at clock rise by one of the chip  
enable signals, its output will three-state following the next  
clock rise.  
Because the CYM52KNP72AV33 is a common I/O device,  
data should not be driven into the device while the outputs are  
active. The Output Enable (OE) can be deasserted HIGH be-  
fore presenting data to the DQ and DP (DQa-h/DPa-h for  
CYM52KNP72AV33 ) inputs. Doing so will three-state the out-  
put drivers. As a safety precaution, DQ and DP (DQa-h/DPa-h  
for CYM52KNP72AV33 are automatically three-stated during  
the data portion of a write cycle, regardless of the state of OE.  
Burst Write Accesses  
The CYM52KNP72AV33 has an on-chip burst counter that  
allows the user the ability to supply a single address and con-  
duct up to four WRITE operations without reasserting the ad-  
dress inputs. ADV/LD must be driven LOW in order to load the  
initial address, as described in the Single Write Access section  
above. When ADV/LD is driven HIGH on the subsequent clock  
rise, the chip enables (CE1, CE2, and CE3) and WE inputs are  
ignored and the burst counter is incremented. The correct  
BWS (BWSa-h for CYM52KNP72AV33 ) inputs must be driven  
in each cycle of the burst write in order to write the correct  
bytes of data.  
Burst Read Accesses  
The CYM52KNP72AV33 has an on-chip burst counter that  
allows the user the ability to supply a single address and con-  
duct up to four Reads without reasserting the address inputs.  
ADV/LD must be driven LOW in order to load a new address  
into the SRAM, as described in the Single Read Access sec-  
tion above. The sequence of the burst counter is determined  
by the MODE input signal. A LOW input on MODE selects a  
Document #: 38-05093 Rev. **  
Page 5 of 24  
PRELIMINARY  
CYM52KNP72AV33  
Cycle Description Truth Table[1, 2, 3, 4, 5, 6]  
Address  
ADV/  
Operation  
Used  
CE  
CEN  
LD/  
WE  
BWSx  
CLK  
L-H  
Comments  
Deselected  
External  
1
0
L
X
X
I/Os three-state following next  
recognized clock.  
Suspend  
-
X
1
X
X
X
L-H  
Clock ignored, all operations  
suspended.  
Begin Read  
Begin Write  
External  
External  
0
0
0
0
0
0
1
0
X
L-H  
L-H  
Address latched.  
Valid  
Address latched, data presented  
two valid clocks later.  
Burst Read  
Operation  
Internal  
X
0
1
X
X
L-H  
Burst Read operation. Previous ac-  
cess was a Read operation. Ad-  
dresses incremented internally in  
conjunction with the state of Mode.  
Burst Write  
Operation  
Internal  
X
0
1
X
Valid  
L-H  
Burst Write operation. Previous ac-  
cess was a Write operation. Ad-  
dresses incremented internally in  
conjunction with the state of  
MODE. Bytes written are deter-  
mined by BWS[d:a]  
.
Interleaved Burst Sequence  
Linear Burst Sequence  
First  
Address  
Second  
Address  
Third  
Address  
Fourth  
Address  
First  
Address  
Second  
Address  
Third  
Address  
Fourth  
Address  
A[1:0]  
A[1:0]  
A[1:0]  
A[1:0]  
A[1:0]  
A[1:0]  
A[1:0]  
A[1:0]  
00  
01  
10  
11  
01  
00  
11  
10  
10  
11  
00  
01  
11  
10  
01  
00  
00  
01  
10  
11  
01  
10  
11  
00  
10  
11  
00  
01  
11  
00  
01  
10  
Notes:  
1. X = “Don't Care,” 1 = Logic HIGH, 0 = Logic LOW, CE stands for ALL Chip Enables active. BWS = 0 signifies at least one Byte Write Select is active, BWS  
=
x
x
Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.  
2. Write is defined by WE and BWS . See Write Cycle Description table for details.  
x
3. The DQ and DP pins are controlled by the current cycle and the OE signal.  
4. CEN = 1 inserts wait states.  
5. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.  
6. OE assumed LOW.  
Document #: 38-05093 Rev. **  
Page 6 of 24  
PRELIMINARY  
CYM52KNP72AV33  
1
Write Cycle Description[1]  
Function (CYM52KNPAV33)  
Read  
WE  
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BWSh  
X
1
BWSg  
X
1
BWSf  
X
1
BWSe  
X
1
BWSd  
X
1
BWSc  
X
1
BWSb  
X
1
BWSa  
X
1
Write - No bytes written  
Write Byte 0 - (DQa and DPa)  
Write Byte 1 - (DQb and DPb)  
Write Bytes 1, 0  
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
Write Byte 2 - (DQc and DPc)  
Write Bytes 2, 0  
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
0
Write Bytes 2, 1  
1
1
1
1
1
0
0
1
Write Bytes 2, 1, 0  
Write Byte 3 - (DQd and DPd)  
Write Bytes 3, 0  
1
1
1
1
1
0
0
0
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
0
Write Bytes 3, 1  
1
1
1
1
0
1
0
1
Write Bytes 3, 1, 0  
Write Bytes 3, 2  
1
1
1
1
0
1
0
0
1
1
1
1
0
0
1
1
Write Bytes 3, 2, 0  
Write Bytes 3, 2, 1  
Write Bytes 3,2,1,0  
Write Bytes 4 - (DQe and DPe)  
Write Bytes 4, 0  
1
1
1
1
0
0
1
0
1
1
1
1
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
0
Write Bytes 4, 1  
1
1
1
0
1
1
0
1
Write Bytes 4, 1, 0  
Write Bytes 4, 2  
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
1
Write Bytes 4, 2, 0  
Write Bytes 4, 2, 1  
Write Bytes 4, 2, 1, 0  
Write Bytes 4, 3  
1
1
1
0
1
0
1
0
1
1
1
0
1
0
0
1
1
1
1
0
1
0
0
0
1
1
1
0
0
1
1
1
Write Bytes 4, 3, 0  
Write Bytes 4, 3, 1  
Write Bytes 4, 3, 1, 0  
Write Bytes 4, 3, 2  
Write Bytes 4, 3, 2, 0  
Write Bytes 4, 3, 2, 1  
1
1
1
0
0
1
1
0
1
1
1
0
0
1
0
1
1
1
1
0
0
1
0
0
1
1
1
0
0
0
1
1
1
1
1
0
0
0
1
0
1
1
1
0
0
0
0
1
Document #: 38-05093 Rev. **  
Page 7 of 24  
PRELIMINARY  
CYM52KNP72AV33  
Write Cycle Description[1] (continued)  
Function (CYM52KNPAV33)  
Write Bytes 4, 3, 2, 1, 0  
Write Bytes 5 - DQf and DPf  
Write Bytes 5,0  
WE  
0
BWSh  
BWSg  
BWSf  
BWSe  
BWSd  
BWSc  
BWSb  
BWSa  
1
1
1
1
1
0
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
1
1
1
0
Write Bytes 5,1  
0
1
1
0
1
1
1
0
1
Write Bytes 5, 1, 0  
0
1
1
0
1
1
1
0
0
Write Bytes 5, 2  
0
1
1
0
1
1
0
1
1
Write Bytes 5, 2, 0  
0
1
1
0
1
1
0
1
0
* Write Bytes ““  
“ “  
0
“ “  
0
“ “  
0
“ “  
0
“ “  
0
“ “  
0
“ “  
0
“ “  
0
“ “  
1
Write Bytes 7, 6, 5, 4, 3, 2, 1  
Write All Bytes  
0
0
0
0
0
0
0
0
0
* Not all Combo’s are specified  
Document #: 38-05093 Rev. **  
Page 8 of 24  
PRELIMINARY  
CYM52KNP72AV33  
instruction registers. Data is serially loaded into the TDI pin on  
the rising edge of TCK. Data is output on the TDO pin on the  
falling edge of TCK.  
IEEE 1149.1 Serial Boundary Scan (JTAG)  
The CYM52KNP72AV33 incorporates a serial boundary scan  
Test Access Port (TAP) in the BGA package only. The TQFP  
package does not offer this functionality. This port operates in  
accordance with IEEE Standard 1149.1-1900, but does not  
have the set of functions required for full 1149.1 compliance.  
These functions from the IEEE specification are excluded be-  
cause their inclusion places an added delay in the critical  
speed path of the SRAM. Note that the TAP controller func-  
tions in a manner that does not conflict with the operation of  
other devices using 1149.1 fully compliant TAPs. The TAP op-  
erates using JEDEC standard 3.3V I/O logic levels.  
Instruction Register  
Three-bit instructions can be serially loaded into the instruction  
register. This register is loaded when it is placed between the  
TDI and TDO pins as shown in the TAP Controller Block Dia-  
gram. Upon power-up, the instruction register is loaded with  
the IDCODE instruction. It is also loaded with the IDCODE  
instruction if the controller is placed in a reset state as de-  
scribed in the previous section.  
When the TAP controller is in the CaptureIR state, the two least  
significant bits are loaded with a binary “01” pattern to allow for  
fault isolation of the board level serial test path.  
Disabling the JTAG Feature  
It is possible to operate the SRAM without using the JTAG  
feature. To disable the TAP controller, TCK must be tied LOW  
(VSS) to prevent clocking of the device. TDI and TMS are in-  
ternally pulled up and may be unconnected. They may alter-  
nately be connected to VDD through a pull-up resistor. TDO  
should be left unconnected. Upon power-up, the device will  
come up in a reset state which will not interfere with the oper-  
ation of the device.  
Bypass Register  
To save time when serially shifting data through registers, it is  
sometimes advantageous to skip certain states. The bypass  
register is a single-bit register that can be placed between TDI  
and TDO pins. This allows data to be shifted through the  
SRAM with minimal delay. The bypass register is set LOW  
(VSS) when the BYPASS instruction is executed.  
Test Access Port (TAP) - Test Clock  
Boundary Scan Register  
The test clock is used only with the TAP controller. All inputs  
are captured on the rising edge of TCK. All outputs are driven  
from the falling edge of TCK.  
The boundary scan register is connected to all the input and  
output pins on the SRAM. Several no connect (NC) pins are  
also included in the scan register to reserve pins for higher  
density devices. The x36 configuration has a 69-bit-long reg-  
ister, and the x18 configuration has a 69-bit-long register.  
Test Mode Select  
The TMS input is used to give commands to the TAP controller  
and is sampled on the rising edge of TCK. It is allowable to  
leave this pin unconnected if the TAP is not used. The pin is  
pulled up internally, resulting in a logic HIGH level.  
The boundary scan register is loaded with the contents of the  
RAM Input and Output ring when the TAP controller is in the  
Capture-DR state and is then placed between the TDI and  
TDO pins when the controller is moved to the Shift-DR state.  
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-  
tions can be used to capture the contents of the Input and  
Output ring.  
Test Data-In (TDI)  
The TDI pin is used to serially input information into the regis-  
ters and can be connected to the input of any of the registers.  
The register between TDI and TDO is chosen by the instruc-  
tion that is loaded into the TAP instruction register. For infor-  
mation on loading the instruction register, see the TAP Con-  
troller State Diagram. TDI is internally pulled up and can be  
unconnected if the TAP is unused in an application. TDI is  
connected to the Most Significant Bit (MSB) on any register.  
The Boundary Scan Order tables show the order in which the  
bits are connected. Each bit corresponds to one of the bumps  
on the SRAM package. The MSB of the register is connected  
to TDI, and the LSB is connected to TDO.  
Identification (ID) Register  
The ID register is loaded with a vendor-specific, 32-bit code  
during the Capture-DR state when the IDCODE command is  
loaded in the instruction register. The IDCODE is hardwired  
into the SRAM and can be shifted out when the TAP controller  
is in the Shift-DR state. The ID register has a vendor code and  
other information described in the Identification Register Defi-  
nitions table.  
Test Data Out (TDO)  
The TDO output pin is used to serially clock data-out from the  
registers. The output is active depending upon the current  
state of the TAP state machine (see TAP Controller State Dia-  
gram). The output changes on the falling edge of TCK. TDO is  
connected to the Least Significant Bit (LSB) of any register.  
Performing a TAP Reset  
TAP Instruction Set  
A Reset is performed by forcing TMS HIGH (VDD) for five rising  
edges of TCK. This RESET does not affect the operation of the  
SRAM and may be performed while the SRAM is operating. At  
power-up, the TAP is reset internally to ensure that TDO  
comes up in a High-Z state.  
Eight different instructions are possible with the three-bit in-  
struction register. All combinations are listed in the Instruction  
Code table. Three of these instructions are listed as RE-  
SERVED and should not be used. The other five instructions  
are described in detail below.  
The TAP controller used in this SRAM is not fully compliant to  
the 1149.1 convention because some of the mandatory 1149.1  
instructions are not fully implemented. The TAP controller can-  
not be used to load address, data, or control signals into the  
SRAM and cannot preload the Input or Output buffers. The  
TAP Registers  
Registers are connected between the TDI and TDO pins and  
allow data to be scanned into and out of the SRAM test circuit-  
ry. Only one register can be selected at a time through the  
Document #: 38-05093 Rev. **  
Page 9 of 24  
PRELIMINARY  
CYM52KNP72AV33  
SRAM does not implement the 1149.1 commands EXTEST or  
INTEST or the PRELOAD portion of SAMPLE / PRELOAD;  
rather it performs a capture of the Inputs and Output ring when  
these instructions are executed.  
When the SAMPLE / PRELOAD instructions are loaded into  
the instruction register and the TAP controller is in the Capture-  
DR state, a snapshot of data on the inputs and output pins is  
captured in the boundary scan register.  
Instructions are loaded into the TAP controller during the Shift-  
IR state when the instruction register is placed between TDI  
and TDO. During this state, instructions are shifted through the  
instruction register through the TDI and TDO pins. To execute  
the instruction once it is shifted in, the TAP controller needs to  
be moved into the Update-IR state.  
The user must be aware that the TAP controller clock can only  
operate at a frequency up to 10 MHz, while the SRAM clock  
operates more than an order of magnitude faster. Because  
there is a large difference in the clock frequencies, it is possible  
that during the Capture-DR state, an input or output will under-  
go a transition. The TAP may then try to capture a signal while  
in transition (metastable state). This will not harm the device,  
but there is no guarantee as to the value that will be captured.  
Repeatable results may not be possible.  
EXTEST  
EXTEST is a mandatory 1149.1 instruction which is to be ex-  
ecuted whenever the instruction register is loaded with all 0s.  
EXTEST is not implemented in the TAP controller, and there-  
fore this device is not compliant to the 1149.1 standard.  
To guarantee that the boundary scan register will capture the  
correct value of a signal, the SRAM signal must be stabilized  
long enough to meet the TAP controller’s capture set-up plus  
hold times (tCS and tCH). The SRAM clock input might not be  
captured correctly if there is no way in a design to stop (or  
slow) the clock during a SAMPLE / PRELOAD instruction. If  
this is an issue, it is still possible to capture all other signals  
and simply ignore the value of the CK and CK# captured in the  
boundary scan register.  
The TAP controller does recognize an all-0 instruction. When  
an EXTEST instruction is loaded into the instruction register,  
the SRAM responds as if a SAMPLE / PRELOAD instruction  
has been loaded. There is one difference between the two  
instructions. Unlike the SAMPLE / PRELOAD instruction,  
EXTEST places the SRAM outputs in a High-Z state.  
Once the data is captured, it is possible to shift out the data by  
putting the TAP into the Shift-DR state. This places the bound-  
ary scan register between the TDI and TDO pins.  
IDCODE  
The IDCODE instruction causes a vendor-specific, 32-bit code  
to be loaded into the instruction register. It also places the  
instruction register between the TDI and TDO pins and allows  
the IDCODE to be shifted out of the device when the TAP con-  
troller enters the Shift-DR state. The IDCODE instruction is  
loaded into the instruction register upon power-up or whenever  
the TAP controller is given a test logic reset state.  
Note that since the PRELOAD part of the command is not  
implemented, putting the TAP into the Update to the Update-  
DR state while performing a SAMPLE / PRELOAD instruction  
will have the same effect as the Pause-DR command.  
Bypass  
When the BYPASS instruction is loaded in the instruction reg-  
ister and the TAP is placed in a Shift-DR state, the bypass  
register is placed between the TDI and TDO pins. The advan-  
tage of the BYPASS instruction is that it shortens the boundary  
scan path when multiple devices are connected together on a  
board.  
SAMPLE Z  
The SAMPLE Z instruction causes the boundary scan register  
to be connected between the TDI and TDO pins when the TAP  
controller is in a Shift-DR state. It also places all SRAM outputs  
into a High-Z state.  
SAMPLE / PRELOAD  
Reserved  
SAMPLE / PRELOAD is a 1149.1 mandatory instruction. The  
PRELOAD portion of this instruction is not implemented, so  
the TAP controller is not fully 1149.1 compliant.  
These instructions are not implemented but are reserved for  
future use. Do not use these instructions.  
Document #: 38-05093 Rev. **  
Page 10 of 24  
PRELIMINARY  
CYM52KNP72AV33  
TAP Controller State Diagram  
TEST-LOGIC  
1
RESET  
1
1
1
TEST-LOGIC/  
IDLE  
SELECT  
DR-SCAN  
SELECT  
IR-SCAN  
0
0
0
1
1
CAPTURE-DR  
CAPTURE-DR  
0
0
SHIFT-DR  
0
SHIFT-IR  
0
1
1
EXIT1-DR  
0
1
EXIT1-IR  
0
1
0
0
PAUSE-DR  
1
PAUSE-IR  
1
0
0
EXIT2-DR  
1
EXIT2-IR  
1
UPDATE-DR  
UPDATE-IR  
1
1
0
0
Note: The 0/1 next to each state represents the value at TMS at the rising edge of TCK.  
Document #: 38-05093 Rev. **  
Page 11 of 24  
PRELIMINARY  
CYM52KNP72AV33  
TAP Controller Block Diagram  
0
Bypass Register  
Selection  
Circuitry  
Selection  
Circuitry  
TDO  
2
1
0
TDI  
Instruction Register  
29  
Identification Register  
31 30  
.
.
2
1
1
0
0
.
.
.
.
.
2
Boundary Scan Register  
TCK  
TMS  
TAP Controller  
TAP Electrical Characteristics Over the Operating Range[7, 8]  
Parameter  
VOH1  
VOH2  
VOL1  
VOL2  
VIH  
Description  
Test Conditions  
Min.  
2.1  
Max.  
Unit  
V
Output HIGH Voltage  
Output HIGH Voltage  
Output LOW Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
Input Load Current  
IOH = −2.0 mA  
IOH = −100 µA  
IOL = 2.0 mA  
IOL = 100 µA  
2.0  
V
0.7  
0.2  
V
V
2.0  
−0.3  
−5  
V
DD+0.3  
V
VIL  
0.7  
V
IX  
GND ≤ VI ≤ VDDQ  
5
µA  
Notes:  
7. All Voltage referenced to Ground  
8. Overshoot: VIH(AC) < VDD+1.5V for t < tTCYC/2. Undershoot: VIL(AC) < 0.5V for t < tTCYC/2. Power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms.  
Document #: 38-05093 Rev. **  
Page 12 of 24  
PRELIMINARY  
CYM52KNP72AV33  
TAP AC Switching Characteristics Over the Operating Range[9, 10]  
Parameter  
tTCYC  
tTF  
Description  
Min.  
Max.  
Unit  
ns  
TCK Clock Cycle Time  
TCK Clock Frequency  
TCK Clock HIGH  
100  
10  
MHz  
ns  
tTH  
40  
40  
tTL  
TCK Clock LOW  
ns  
Set-up Times  
tTMSS  
tTDIS  
TMS Set-up to TCK Clock Rise  
TDI Set-up to TCK Clock Rise  
Capture Set-up to TCK Rise  
10  
10  
10  
ns  
ns  
ns  
tCS  
Hold Times  
tTMSH  
tTDIH  
TMS Hold after TCK Clock Rise  
TDI Hold after Clock Rise  
10  
10  
10  
ns  
ns  
ns  
tCH  
Capture Hold after Clock Rise  
Output Times  
tTDOV  
TCK Clock LOW to TDO Valid  
TCK Clock LOW to TDO Invalid  
20  
ns  
ns  
tTDOX  
0
Notes:  
9. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.  
10. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.  
Document #: 38-05093 Rev. **  
Page 13 of 24  
PRELIMINARY  
CYM52KNP72AV33  
TAP Timing and Test Conditions  
1.25V  
50Ω  
ALL INPUT PULSES  
TDO  
2.5V  
Z =50Ω  
0
1.25V  
C =20 pF  
L
0V  
GND  
(a)  
tTL  
tTH  
Test Clock  
TCK  
tTCYC  
tTMSS  
tTMSH  
Test Mode Select  
TMS  
tTDIS  
tTDIH  
Test Data-In  
TDI  
Test Data-Out  
TDO  
tTDOX  
tTDOV  
Document #: 38-05093 Rev. **  
Page 14 of 24  
PRELIMINARY  
CYM52KNP72AV33  
Identification Register Definitions  
Value  
Instruction Field  
Revision Number  
CYM52KNP72AV33  
Description  
000  
Version number.  
(31:29)  
Cypress Device ID  
(28:12)  
TBD  
TBD  
1
Defines the type of SRAM.  
Cypress JEDEC ID  
(11:1)  
Allows unique identification of SRAM vendor.  
Indicate the presence of an ID register.  
ID Register Presence  
(0)  
Scan Register sizes  
Register Name  
Instruction  
Bit Size  
3
Bypass  
1
ID  
32  
TBD  
Boundary Scan  
Identification Codes  
Instruction  
Code  
Description  
EXTEST  
000  
Captures the Input/Output ring contents. Places the boundary scan register  
between the TDI and TDO. Forces all SRAM outputs to High-Z state. This  
instruction is not 1149.1 compliant.  
IDCODE  
001  
010  
Loads the ID register with the vendor ID code and places the register be-  
tween TDI and TDO. This operation does not affect SRAM operation.  
SAMPLE Z  
Captures the Input/Output contents. Places the boundary scan register be-  
tween TDI and TDO. Forces all SRAM output drivers to a High-Z state.  
RESERVED  
011  
100  
Do Not Use: This instruction is reserved for future use.  
SAMPLE/PRELOAD  
Captures the Input/Output ring contents. Places the boundary scan register  
between TDI and TDO. Does not affect the SRAM operation. This instruction  
does not implement 1149.1 preload function and is therefore not 1149.1  
compliant.  
RESERVED  
RESERVED  
BYPASS  
101  
110  
111  
Do Not Use: This instruction is reserved for future use.  
Do Not Use: This instruction is reserved for future use.  
Places the bypass register between TDI and TDO. This operation does not  
affect SRAM operation.  
Document #: 38-05093 Rev. **  
Page 15 of 24  
PRELIMINARY  
CYM52KNP72AV33  
Boundary Scan Order (To be Determined)  
Document #: 38-05093 Rev. **  
Page 16 of 24  
PRELIMINARY  
CYM52KNP72AV33  
Current into Outputs (LOW) ........................................ 20 mA  
Maximum Ratings  
Static Discharge Voltage .......................................... >2001V  
(per MIL-STD-883, Method 3015)  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Latch-Up Current.................................................... >200 mA  
Storage Temperature .................................–65°C to +150°C  
Ambient Temperature with  
Power Applied.............................................–55°C to +125°C  
Operating Range  
Ambient  
Supply Voltage on VDD Relative to GND ....... –0.5V to +3.6V  
Range Temperature[11]  
VDD  
VDDQ  
DC Voltage Applied to Outputs  
in High Z State[12] ............................... –0.5V to VDDQ + 0.5V  
Com’l  
0°C to +70°C  
3.3V + 10%/  
2.375V–VDD  
–5%  
DC Input Voltage[12]............................ –0.5V to VDDQ + 0.5V  
Electrical Characteristics Over the Operating Range  
Parameter  
VDD  
Description  
Test Conditions  
Min.  
3.135  
2.375  
1.7  
Max.  
3.6  
Unit  
Power Supply Voltage  
I/O Supply Voltage  
Output HIGH Voltage  
V
V
VDDQ  
VOH  
3.3 V I/O  
3.6  
VDD = Min., IOH = –1.0 mA  
VDD = Min., IOH = –1.0 mA  
2.5V  
3.3V  
V
2.0  
V
VOL  
VIH  
VIL  
IX  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
Input Load Current  
Input Current of MODE  
VDD = Min., IOL = 1.0 mA, either VDDQ  
0.4  
V
2.0 VDD + 0.3V  
V
–0.5  
0.8  
10  
60  
5
V
GND < VI < VDDQ  
mA  
mA  
mA  
IOZ  
IDD  
Output Leakage  
Current  
GND < VI < VDDQ, Output Disabled  
VDD Operating Supply VDD = Max., IOUT = 0 mA,  
f = fMAX = 1/tCYC  
6.7-ns cycle, 150 MHz  
7.5-ns cycle, 133 MHz  
10-ns cycle,100 MHz  
6.7-ns cycle, 150 MHz  
7.5-ns cycle, 133 MHz  
10-ns cycle, 100 MHz  
460  
380  
320  
160  
100  
70  
mA  
mA  
mA  
mA  
mA  
ISB1  
Automatic CE  
Power-Down  
Current—TTL Inputs  
Max. VDD, Device Deselected,  
IN ≥ VIH or VIN ≤ VIL  
f = fMAX = 1/tCYC  
V
ISB2  
Automatic CE  
Power-Down  
Max. VDD, DeviceDeselected, VIN All speed grades  
< 0.3V or VIN > VDDQ – 0.3V,  
60  
mA  
Current—CMOS Inputs f = 0  
ISB3  
Automatic CE  
Power-Down  
Current—CMOS Inputs f = fMAX = 1/tCYC  
Max. VDD, Device Deselected, or 6.7-ns cycle, 150 MHz  
140  
80  
mA  
mA  
mA  
mA  
VIN < 0.3V or VIN > VDDQ – 0.3V  
7.5-ns cycle, 133 MHz  
10-ns cycle, 100MHz  
All Speeds  
50  
ISB4  
Automatic CS  
Power-Down  
Max. VDD, Device Deselected,  
VIN > VIH or VIN < VIL, f = 0  
40  
Current—TTL Inputs  
Notes:  
11. TA is the case temperature.  
12. Minimum voltage equals –2.0V for pulse durations of less than 20 ns.  
13. The load used for VOH and VOL testing is shown in figure (b) of the A/C test conditions.  
Document #: 38-05093 Rev. **  
Page 17 of 24  
PRELIMINARY  
CYM52KNP72AV33  
Capacitance[15]  
Parameter  
Description  
Test Conditions  
Max.  
Unit  
pF  
CIN  
Input Capacitance  
TA = 25°C, f = 1 MHz,  
VDD = VDDQ = 3.3V  
4
4
6
CCLK  
CI/O  
Clock Input Capacitance  
Input/Output Capacitance  
pF  
pF  
AC Test Loads and Waveforms  
R=317Ω  
3.3V  
[14]  
OUTPUT  
ALL INPUT PULSES  
90%  
OUTPUT  
V
CC  
90%  
10%  
Z =50Ω  
0
R =50Ω  
10%  
L
5 pF  
GND  
R=351Ω  
< 1V/ns  
< 1V/ns  
V = 1.5V  
L
INCLUDING  
JIG AND  
SCOPE  
(c)  
(a)  
(b)  
Thermal Resistance[15]  
Description  
Test Conditions  
Symbol  
BGATyp.  
Units  
Thermal Resistance (Junc- Still Air, soldered on a 4.25 x 1.125 inch, 4-layer  
QJA  
xx  
°C/W  
tion to Ambient)  
printed circuit board  
Thermal Resistance (Junc-  
tion to Case)  
QJC  
xx  
°C/W  
Notes:  
14. Input waveform should have a slew rate of > 1 V/ns.  
15. Tested initially and after any design or process change that may affect these parameters.  
Document #: 38-05093 Rev. **  
Page 18 of 24  
PRELIMINARY  
CYM52KNP72AV33  
Switching Characteristics Over the Operating Range[16]  
-150  
-133  
-100  
Parameter  
Clock  
Description  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Unit  
tCYC  
Clock Cycle Time  
6.7  
7.5  
10.0  
ns  
MHz  
ns  
FMAX  
tCH  
Maximum Operating Frequency  
Clock HIGH  
150  
133  
100  
2.6  
2.6  
3.0  
3.0  
4.0  
4.0  
tCL  
Clock LOW  
ns  
Output Times  
tCO  
Data Output Valid After CLK Rise  
OE LOW to Output Valid[15, 17, 19]  
Data Output Hold After CLK Rise  
Clock to High-Z[15, 16, 17, 18, 19]  
Clock to Low-Z[15, 16, 17, 18, 19]  
OE HIGH to Output High-Z[16, 17, 19]  
OE LOW to Output Low-Z[16, 17, 19]  
3.8  
3.8  
4.2  
4.2  
5.0  
5.0  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tEOV  
tDOH  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
tCHZ  
3.0  
3.0  
3.5  
3.5  
3.5  
4.8  
tCLZ  
tEOHZ  
tEOLZ  
Set-Up Times  
tAS  
0
0
0
Address Set-Up Before CLK Rise  
Data Input Set-Up Before CLK Rise  
CEN Set-Up Before CLK Rise  
WE, BWSx Set-Up Before CLK Rise  
ADV/LD Set-Up Before CLK Rise  
Chip Select Set-Up  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
2.0  
2.0  
2.0  
2.0  
2.0  
2.0  
ns  
ns  
ns  
ns  
ns  
ns  
tDS  
tCENS  
tWES  
tALS  
tCES  
Hold Times  
tAH  
Address Hold After CLK Rise  
Data Input Hold After CLK Rise  
CEN Hold After CLK Rise  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
ns  
ns  
ns  
ns  
ns  
ns  
tDH  
tCENH  
tWEH  
WE, BWx Hold After CLK Rise  
ADV/LD Hold After CLK Rise  
Chip Select Hold After CLK Rise  
tALH  
tCEH  
Notes:  
16. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and  
output loading of the specified IOL/IOH and load capacitance. Shown in (a), (b) and (c) of AC Test Loads.  
17.  
tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with AC test conditions shown in part (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state  
voltage.  
18. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same  
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed  
to achieve High-Z prior to Low-Z under the same system conditions.  
19. This parameter is sampled and not 100% tested.  
Document #: 38-05093 Rev. **  
Page 19 of 24  
PRELIMINARY  
CYM52KNP72AV33  
Switching Waveforms  
READ/WRITE/DESELECT Sequence  
CLK  
CEN  
tCENH  
tCENS  
tCL  
tCH  
tCYC  
tAH  
tAS  
CEN HIGH blocks  
all synchronous inputs  
WA2  
WA5  
RA1  
RA3  
RA4  
RA6  
ADDRESS  
RA7  
WE &  
BWSx  
tWS  
tWH  
tCEH  
tCES  
CE  
tDH  
tDS  
tCHZ  
tCHZ  
tDOH  
tCLZ  
tDOH  
Q1  
Out  
D2  
In  
Data  
In/Out  
Q4  
Out  
D5  
In  
Q3  
Out  
Q6  
Out  
Q7  
Out  
Device  
originally  
tCO  
deselected  
The combination of WE & BWSx define a write cycle  
(see Write Cycle Description table) CE is the combination of CE1, CE2, and CE3. All chip enables need to be active  
in order to select the device. Any chip enable can deselect the device. RAx stands for Read Address X, WAx  
Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. ADV/LD held LOW.  
OE held LOW.  
= UNDEFINED  
= DON’T CARE  
Document #: 38-05093 Rev. **  
Page 20 of 24  
PRELIMINARY  
CYM52KNP72AV33  
Switching Waveforms (continued)  
Burst Sequences  
CLK  
tCYC  
tALH  
tALS  
ADV/LD  
tCL  
tCH  
tAH  
tAS  
RA1  
WA2  
ADDRESS  
WE  
RA3  
tWS  
tWH  
tWS  
tWH  
BWSx  
tCES  
tCEH  
CE  
tCLZ  
tCHZ  
tDH  
tDOH  
tCLZ  
Q3  
Out  
Data  
In/Out  
Q1  
Q1+2  
Out  
Q1+3  
Out  
D2  
In  
D2+2  
In  
D2+3  
In  
Q1+1  
Out  
D2+1  
In  
Out  
Device  
originally  
deselected  
tCO  
tCO  
tDS  
The combination of WE & BWSx (x = a, b c, d) define a write cycle (see Write Cycle Description table).  
CE is the combination of CE1, CE2, and CE3. All chip enables need to be active in order to select  
the device. Any chip enable can deselect the device. RAx stands for Read Address X, WA stands for  
Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. CEN held  
LOW. During burst writes, byte writes can be conducted by asserting the appropriate BWSx input signals.  
Burst order determined by the state of the MODE input. CEN held LOW. OE held LOW.  
= UNDEFINED  
= DON’T CARE  
Document #: 38-05093 Rev. **  
Page 21 of 24  
PRELIMINARY  
CYM52KNP72AV33  
Switching Waveforms (continued)  
OE Timing  
OE  
tEOV  
tEOHZ  
Three-State  
I/Os  
tEOLZ  
Ordering Information  
Speed  
Package  
Name  
Operating  
Range  
(MHz)  
Ordering Code  
Package Type  
209-Lead FBGA (14 x 22 x 2.2mm)  
209-Lead FBGA (14 x 22 x 2.2mm)  
209-Lead FBGA (14 x 22 x 2.2mm)  
150  
CYM52KNP72V33A-15BBC  
CYM52KNP72V33A-13BBC  
CYM52KNP72V33A-10BBC  
BB209  
BB209  
BB209  
Commercial  
Commercial  
Commercial  
133  
100  
Document #: 38-05093 Rev. **  
Page 22 of 24  
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
PRELIMINARY  
CYM52KNP72AV33  
Package Diagram  
209-Ball FBGA (14 x 22 x 2.20 mm) BB209  
Part Numbering Scheme  
CY  
M
Depth  
Architecture Width Revision Voltage  
Speed  
Package Temperature  
C - Commercial  
BB - 209PBGA  
Frequency(100-150Mhz)  
Core Voltage (V33 - 3.3V)  
Module Revision (A -First Revision)  
Bus Width(72 - 72Bits)  
Architecture (NP - NoBL Pipelined)  
Module Depth(52K = 512K)  
Module  
Cypress  
Document #: 38-05093 Rev. **  
Page 23 of 24  
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
PRELIMINARY  
CYM52KNP72AV33  
Document Title: CYM52KNP72AV33 512Kx72 Pipelined MCM with NoBL™ Architecture  
Document Number: 38-05093  
ORIG. OF  
REV.  
ECN NO.  
ISSUE DATE  
CHANGE  
DESCRIPTION OF CHANGE  
New Data Sheet  
**  
107603  
08/13/01  
MEG  
Document #: 38-05093 Rev. **  
Page 24 of 24  
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