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PZ3128AS12BE

型号：

PZ3128AS12BE

品牌：

NXP[ NXP ]

页数：

18 页

PDF大小：

120 K

下载PDF手册
INTEGRATED CIRCUITS  
PZ3128A/PZ3128D  
128 macrocell CPLD with enhanced  
clocking  
Preliminary specification  
Supersedes data of 1999 May 07  
IC27 Data Handbook  
1999 Jun 29  
Philips  
Semiconductors  
Philips Semiconductors  
Product specification  
128 macrocell CPLD with enhanced clocking  
PZ3128A/PZ3128D  
FEATURES  
DESCRIPTION  
The PZ3128A/PZ3128D CPLD (Complex Programmable Logic  
Device) is a member of the Fast Zero Power (FZP ) family of  
CPLDs from Philips Semiconductors. These devices combine high  
speed and zero power in a 128 macrocell CPLD. With the FZP  
design technique, the PZ3128A/PZ3128D offers true pin-to-pin  
speeds of 7.5ns, while simultaneously delivering power that is less  
than 100µA at standby without the need for ‘turbo bits’ or other  
power down schemes. By replacing conventional sense amplifier  
methods for implementing product terms (a technique that has been  
used in PLDs since the bipolar era) with a cascaded chain of pure  
CMOS gates, the dynamic power is also substantially lower than  
any competing CPLD – 70% lower at 50MHz. These devices are the  
first TotalCMOS PLDs, as they use both a CMOS process  
technology and the patented full CMOS FZP design technique.  
• Industry’s first TotalCMOS PLD – both CMOS design and  
process technologies  
• Fast Zero Power (FZP ) design technique provides ultra-low  
power and very high speed  
• 3 Volt, In-System Programmable (ISP) using a JTAG interface  
– On-chip supervoltage generation  
– ISP commands include: Enable, Erase, Program, Verify  
– Supported by multiple ISP programming platforms  
– 4 pin JTAG interface (TCK, TMS, TDI, TDO)  
– JTAG commands include: Bypass, Idcode  
• High speed pin-to-pin delays of 7.5ns  
• Ultra-low static power of less than 100µA  
• Dynamic power that is 70% lower at 50MHz than competing  
The Philips FZP CPLDs introduce the new patented XPLA  
(eXtended Programmable Logic Array) architecture. The XPLA  
architecture combines the best features of both PLA and PAL type  
structures to deliver high speed and flexible logic allocation that  
results in superior ability to make design changes with fixed pinouts.  
The XPLA structure in each logic block provides a fast 7.5ns  
PAL path with 5 dedicated product terms per output. This PAL  
path is joined by an additional PLA structure that deploys a pool of  
32 product terms to a fully programmable OR array that can allocate  
the PLA product terms to any output in the logic block. This  
combination allows logic to be allocated efficiently throughout the  
logic block and supports as many as 37 product terms on an output.  
The speed with which logic is allocated from the PLA array to an  
output is only 1.5ns, regardless of the number of PLA product terms  
devices  
• 5V tolerant I/Os to support mixed voltage systems  
• 100% routable with 100% utilization while all pins and all  
macrocells are fixed  
• Deterministic timing model that is extremely simple to use  
• Up to 20 clocks available  
• Support for complex asynchronous clocking  
• Innovative XPLA architecture combines high speed with  
extreme flexibility  
• 1000 erase/program cycles guaranteed  
• 20 years data retention guaranteed  
• Logic expandable to 37 product terms  
used, which results in worst case t ’s of only 9ns from any pin to  
PD  
any other pin. In addition, logic that is common to multiple outputs  
can be placed on a single PLA product term and shared across  
multiple outputs via the OR array, effectively increasing design  
density.  
2
• Advanced 0.35µ E CMOS process  
• Security bit prevents unauthorized access  
• Design entry and verification using industry standard and Philips  
CAE tools  
The PZ3128A/PZ3128D CPLDs are supported by industry standard  
CAE tools (Cadence, Exemplar Logic, Mentor, OrCAD, Synopsys,  
Synario, Viewlogic, MINC), using text (Abel, VHDL, Verilog) and/or  
schematic entry. Design verification uses industry standard  
simulators for functional and timing simulation. Development is  
supported on personal computer, Sparc, and HP platforms. Device  
fitting uses either MINC or Philips Semiconductors-developed tools.  
• Reprogrammable using industry standard device programmers  
• Innovative Control Term structure provides either sum terms or  
product terms in each logic block for:  
– Programmable 3-State buffer  
– Asynchronous macrocell register preset/reset  
– up to 2 asynchronous clocks  
The PZ3128A/PZ3128D CPLD is electrically reprogrammable using  
industry standard device programmers from vendors such as Data  
I/O, BP Microsystems, SMS, and others. The PZ3128A/PZ3128D  
also includes an industry-standard, IEEE 1149.1, JTAG interface  
through which In-System Programming (ISP) and reprogramming of  
the device are supported.  
• Programmable global 3-State pin facilitates ‘bed of nails’ testing  
without using logic resources  
• Available in TQFP and LQFP packages  
• Available in both Commercial and Industrial grades  
• Industrial grade operates from 2.7 to 3.6 Volts  
Table 1. PZ3128A/PZ3128D Features  
PZ3128A/PZ3128D  
Usable gates  
4000  
Maximum inputs  
Maximum I/Os  
100  
96  
Number of macrocells  
Propagation delay (ns)  
Packages  
128  
7.5  
100-pin TQFP, 128-pin LQFP  
PAL is a registered trademark of Advanced Micro Devices, Inc.  
2
1999 Jun 29  
853–2163 21884  
Philips Semiconductors  
Product specification  
128 macrocell CPLD with enhanced clocking  
PZ3128A/PZ3128D  
ORDERING INFORMATION  
I/O  
COUNT  
DRAWING  
NUMBER  
ORDER CODE  
DESCRIPTION  
100-pin TQFP, 7.5ns t , Commercial temperature range, 3.0 to 3.6 volt power supply  
PZ3128AS7BP  
PZ3128AS10BP  
PZ3128AS12BP  
PZ3128AS7BE  
PZ3128AS10BE  
PZ3128AS12BE  
PZ3128DS10BP  
PZ3128DS15BP  
PZ3128DS10BE  
PZ3128DS15BE  
80  
80  
80  
96  
96  
96  
80  
80  
96  
96  
SOT386-1  
SOT386-1  
SOT386-1  
SOT425-1  
SOT425-1  
SOT425-1  
SOT386-1  
SOT386-1  
SOT425-1  
SOT425-1  
PD  
100-pin TQFP, 10ns t , Commercial temperature range, 3.0 to 3.6 volt power supply  
PD  
100-pin TQFP, 12ns t , Commercial temperature range, 3.0 to 3.6 volt power supply  
PD  
128-pin LQFP, 7.5ns t , Commercial temperature range, 3.0 to 3.6 volt power supply  
PD  
128-pin LQFP, 10ns t , Commercial temperature range, 3.0 to 3.6 volt power supply  
PD  
128-pin LQFP, 12ns t , Commercial temperature range, 3.0 to 3.6 volt power supply  
PD  
100-pin TQFP, 10ns t , Industrial temperature range, 2.7 to 3.6 volt power supply  
PD  
100-pin TQFP, 15ns t , Industrial temperature range, 2.7 to 3.6 volt power supply  
PD  
128-pin LQFP, 10ns t , Industrial temperature range, 2.7 to 3.6 volt power supply  
PD  
128-pin LQFP, 15ns t , Industrial temperature range, 2.7 to 3.6 volt power supply  
PD  
From this point of view, this architecture looks like many other CPLD  
architectures. What makes the CoolRunner family unique is what  
is inside each logic block and the design technique used to  
implement these logic blocks. The contents of the logic block will be  
described next.  
XPLA ARCHITECTURE  
Figure 1 shows a high level block diagram of a 128 macrocell device  
implementing the XPLA architecture. The XPLA architecture  
consists of logic blocks that are interconnected by a Zero-power  
Interconnect Array (ZIA). The ZIA is a virtual crosspoint switch. Each  
logic block is essentially a 36V16 device with 36 inputs from the ZIA  
and 16 macrocells. Each logic block also provides 32 ZIA feedback  
paths from the macrocells and I/O pins.  
MC0  
MC0  
MC1  
MC1  
36  
36  
LOGIC  
BLOCK  
LOGIC  
BLOCK  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
MC15  
MC15  
16  
16  
16  
16  
MC0  
MC1  
MC0  
MC1  
36  
36  
LOGIC  
BLOCK  
LOGIC  
BLOCK  
MC15  
MC15  
16  
16  
16  
16  
ZIA  
MC0  
MC1  
MC0  
MC1  
36  
36  
LOGIC  
BLOCK  
LOGIC  
BLOCK  
MC15  
MC15  
16  
16  
16  
16  
MC0  
MC1  
MC0  
MC1  
36  
36  
LOGIC  
BLOCK  
LOGIC  
BLOCK  
I/O  
MC15  
MC15  
16  
16  
16  
16  
SP00464  
Figure 1. Philips XPLA CPLD Architecture  
3
1999 Jun 29  
Philips Semiconductors  
Product specification  
128 macrocell CPLD with enhanced clocking  
PZ3128A/PZ3128D  
Each macrocell has 5 dedicated product terms from the PAL array.  
Logic Block Architecture  
The pin-to-pin t of the PZ3128A/PZ3128D device through the PAL  
PD  
Figure 2 illustrates the logic block architecture. Each logic block  
contains control terms, a PAL array, a PLA array, and 16 macrocells.  
The 6 control terms can individually be configured as either SUM or  
PRODUCT terms, and are used to control the preset/reset and  
output enables of the 16 macrocells’ flip-flops. In addition, two of the  
control terms can be used as clock signals (see Macrocell  
Architecture section for details). The PAL array consists of a  
programmable AND array with a fixed OR array, while the PLA array  
consists of a programmable AND array with a programmable OR  
array. The PAL array provides a high speed path through the array,  
while the PLA array provides increased product term density.  
array is 7.5ns. If a macrocell needs more than 5 product terms, it  
simply gets the additional product terms from the PLA array. The  
PLA array consists of 32 product terms, which are available for use  
by all 16 macrocells. The additional propagation delay incurred by a  
macrocell using 1 or all 32 PLA product terms is just 1.5ns. So the  
total pin-to-pin t for the PZ3128A/PZ3128D using 6 to 37 product  
PD  
terms is 9ns (7.5ns for the PAL + 1.5ns for the PLA).  
36 ZIA INPUTS  
6
CONTROL  
5
PAL  
ARRAY  
PLA  
ARRAY  
(32)  
SP00435A  
Figure 2. Philips XPLA Logic Block Architecture  
4
1999 Jun 29  
Philips Semiconductors  
Product specification  
128 macrocell CPLD with enhanced clocking  
PZ3128A/PZ3128D  
are used to control the asynchronous Preset/Reset of the  
Macrocell Architecture  
macrocell’s flip-flop. Note that the Power-on Reset leaves all  
macrocells in the “zero” state when power is properly applied, and  
that the Preset/Reset feature for each macrocell can also be  
disabled. Control terms CT2 and CT3 can be used as a clock signal  
to the flip-flops of the macrocells, and as the Output Enable of the  
macrocell’s output buffer. Control terms CT4 and CT5 can be used  
to control the Output Enable of the macrocell’s output buffer. Having  
four dedicated Output Enable control terms ensures that the  
CoolRunner devices are PCI compliant. The output buffers can  
also be always enabled or always disabled. All CoolRunner  
devices also provide a Global Tri-State (GTS) pin, which, when  
enabled and pulled Low, will 3-State all the outputs of the device.  
This pin is provided to support “In-Circuit Testing” or “Bed-of-Nails  
Testing”.  
Figure 3 shows the architecture of the macrocell used in the  
CoolRunner PZ3128A/PZ3128D. The macrocell can be configured  
as either a D or T type flip-flop or a combinatorial logic function. A  
D-type flip-flop is generally more useful for implementing state  
machines and data buffering while a T-type flip-flop is generally  
more useful in implementing counters. Each of these flip-flops can  
be clocked from any one of six sources. Four of the clock sources  
(CLK0, CLK1, CLK2, CLK3) are connected to low-skew, device-wide  
clock networks designed to preserve the integrity of the clock signal  
by reducing skew between rising and falling edges. Clock 0 (CLK0)  
is designated as a “synchronous” clock and must be driven by an  
external source. Clock 1 (CLK1), Clock 2 (CLK2), and Clock 3  
(CLK3) can be used as “synchronous” clocks that are driven by an  
external source, or as “asynchronous” clocks that are driven by a  
macrocell equation. CLK0, CLK1, CLK2 and CLK3 can clock the  
macrocell flip-flops on either the rising edge or the falling edge of the  
clock signal. The other clock sources are two of the six control terms  
(CT2 and CT3) provided in each logic block. These clocks can be  
individually configured as either a PRODUCT term or SUM term  
equation created from the 36 signals available inside the logic block.  
The timing for asynchronous and control term clocks is different in  
There are two feedback paths to the ZIA: one from the macrocell,  
and one from the I/O pin. The ZIA feedback path before the output  
buffer is the macrocell feedback path, while the ZIA feedback path  
after the output buffer is the I/O pin feedback path. When the  
macrocell is used as an output, the output buffer is enabled, and the  
macrocell feedback path can be used to feedback the logic  
implemented in the macrocell. When the I/O pin is used as an input,  
the output buffer will be 3-Stated and the input signal will be fed into  
the ZIA via the I/O feedback path, and the logic implemented in the  
buried macrocell can be fed back to the ZIA via the macrocell  
feedback path. It should be noted that unused inputs or I/Os should  
be properly terminated (see the section on Terminations in this data  
sheet and the Application Note Terminating Unused CoolRunner  
I/O Pins).  
that the t time is extended by the amount of time that it takes for  
CO  
the signal to propagate through the array and reach the clock  
network, and the t time is reduced. Please see the app note titled  
SU  
“Understanding CoolRunner Clocking Options” for more detail.  
The six control terms of each logic block are used to control the  
asynchronous Preset/Reset of the flip-flops and the enable/disable  
of the output buffers in each macrocell. Control terms CT0 and CT1  
TO ZIA  
PAL  
PLA  
D/T  
Q
INIT  
(P or R)  
CLK0  
CLK0  
CLK1  
CLK1  
CLK2  
CLK2  
CLK3  
CLK3  
GTS  
GND  
CT0  
CT1  
GND  
SP00558  
Figure 3. PZ3128A/PZ3128D Macrocell Architecture  
5
1999 Jun 29  
Philips Semiconductors  
Product specification  
128 macrocell CPLD with enhanced clocking  
PZ3128A/PZ3128D  
Simple Timing Model  
Figure 4 shows the CoolRunner Timing Model. The CoolRunner  
timing model looks very much like a 22V10 timing model in that  
there are three main timing parameters, including t , t , and t  
In other competing architectures, the user may be able to fit the  
design into the CPLD, but is not sure whether system timing  
requirements can be met until after the design has been fit into the  
device. This is because the timing models of competing  
architectures are very complex and include such things as timing  
dependencies on the number of parallel expanders borrowed,  
sharable expanders, varying number of X and Y routing channels  
used, etc. In the XPLA architecture, the user knows up front  
whether the design will meet system timing requirements. This is  
due to the simplicity of the timing model.  
TotalCMOS Design Technique  
for Fast Zero Power  
Philips is the first to offer a TotalCMOS CPLD, both in process  
technology and design technique. Philips employs a cascade of  
CMOS gates to implement its Sum of Products instead of the  
traditional sense amp approach. This CMOS gate implementation  
allows Philips to offer CPLDs which are both high performance and  
low power, breaking the paradigm that to have low power, you must  
have low performance. Refer to Figure 5 and Table 2 showing the  
.
PD SU  
CO  
I
vs. Frequency of our PZ3128A/PZ3128D TotalCMOS CPLD  
DD  
(data taken w/eight up/down, loadable 16 bit counters@3.3V, 25°C).  
t
= COMBINATORIAL PAL ONLY  
= COMBINATORIAL PAL + PLA  
PD_PAL  
t
PD_PLA  
INPUT PIN  
OUTPUT PIN  
REGISTERED  
= PAL ONLY  
t
t
REGISTERED  
SU_PAL  
= PAL + PLA  
t
SU_PLA  
CO  
INPUT PIN  
D
Q
OUTPUT PIN  
SP00553  
GLOBAL CLOCK PIN  
Figure 4. CoolRunner Timing Model  
70  
60  
50  
40  
I
DD  
(mA)  
30  
20  
10  
0
1
20  
40  
60  
80  
100  
120  
FREQUENCY (MHz)  
SP00617  
Figure 5.  
I vs. Frequency @ V = 3.3V, 25°C  
DD DD  
Table 2. I vs. Frequency  
DD  
V
DD  
= 3.3V, 25_C  
FREQUENCY (MHz)  
0
1
20  
40  
60  
80  
100  
120  
Typical I (mA)  
0.03  
0.7  
12.7  
25.5  
38.1  
50.5  
62.8  
74.7  
DD  
6
1999 Jun 29  
Philips Semiconductors  
Product specification  
128 macrocell CPLD with enhanced clocking  
PZ3128A/PZ3128D  
come from the factory with these I/O pins set to perform JTAG  
functions, but through the software, the final function of these pins  
can be controlled. If the end application will require the device to be  
reprogrammed at some future time with ISP, then the pins can be  
left as dedicated JTAG functions, which means they are not  
available for use as general purpose I/O pins. However, unlike  
competing CPLDs, the Philips PZ3128A/PZ3128D allow the  
macrocells associated with these pins to be used as buried logic  
when the JTAG/ISP function is enabled. This is the default state for  
the software, and no action is required to leave these pins enabled  
for the JTAG/ISP functions. If, however, JTAG/ISP is not required in  
the end application, the software can specify that this function be  
turned off and that these pins be used as general purpose I/O.  
Because the devices initially have the JTAG/ISP functions enabled,  
the JEDEC file can be downloaded into the device once, after which  
the JTAG/ISP pins will become general purpose I/O. This feature is  
good for manufacturing because the devices can be programmed  
during test and assembly of the end product and yet still use all of  
the I/O pins after the programming is done. It eliminates the need for  
a costly, separate programming step in the manufacturing process.  
Of course, if the JTAG/ISP function is never required, this feature  
can be turned off in the software and the device can be programmed  
with an industry-standard programmer, leaving the pins available for  
I/O functions. Table 4 defines the dedicated pins used by the four  
mandatory JTAG signals for each of the PZ3128A/PZ3128D  
package types.  
JTAG Testing Capability  
JTAG is the commonly-used acronym for the Boundary Scan Test  
(BST) feature defined for integrated circuits by IEEE Standard  
1149.1. This standard defines input/output pins, logic control  
functions, and commands which facilitate both board and device  
level testing without the use of specialized test equipment. The  
Philips PZ3128A/PZ3128D devices use the JTAG Interface for  
In–System Programming/Reprogramming. Although only a subset of  
the full JTAG command set is implemented (see Table 5), the  
devices are fully capable of sitting in a JTAG scan chain.  
The Philips PZ3128A/PZ3128D’s JTAG interface includes a TAP  
Port defined by the IEEE 1149.1 JTAG Specification. As  
implemented in the Philips PZ3128A/PZ3128D, the TAP Port  
includes four of the five pins (refer to Table 3) described in the JTAG  
specification: TCK, TMS, TDI, and TDO. The fifth signal defined by  
the JTAG specification is TRST* (Test Reset). TRST* is considered  
an optional signal, since it is not actually required to perform BST or  
ISP. The Philips PZ3128A/PZ3128D saves an I/O pin for general  
purpose use by not implementing the optional TRST* signal in the  
JTAG interface. Instead, the Philips PZ3128A/PZ3128D supports the  
test reset functionality through the use of its power up reset circuit,  
which is included in all Philips CPLDs. The pins associated with the  
TAP Port should connect to an external pull-up resistor to keep the  
JTAG signals from floating when they are not being used.  
In the Philips PZ3128A/PZ3128D, the four mandatory JTAG pins  
each require a unique, dedicated pin on the device. The devices  
Table 3. JTAG Pin Description  
PIN  
TCK  
TMS  
NAME  
DESCRIPTION  
Test Clock Output  
Test Mode Select  
Clock pin to shift the serial data and instructions in and out of the TDI and TDO pins, respectively.  
Serial input pin selects the JTAG instruction mode. TMS should be driven high during user mode  
operation.  
TDI  
Test Data Input  
Serial input pin for instructions and test data. Data is shifted in on the rising edge of TCK.  
TDO  
Test Data Output  
Serial output pin for instructions and test data. Data is shifted out on the falling edge of TCK. The  
signal is tri-stated if data is not being shifted out of the device.  
Table 4. PZ3128A/PZ3128D JTAG Pinout by Package Type  
(PIN NUMBER / MACROCELL #)  
DEVICE  
TCK  
TMS  
TDI  
TDO  
PZ3128A/PZ3128D  
100-pin TQFP  
62/F15  
82/F15  
15/C15  
21/C15  
4/B15  
8/B15  
73/G15  
95/G15  
128-pin LQFP  
Table 5. PZ3128A/PZ3128D Low-Level JTAG Boundary-Scan Commands  
INSTRUCTION  
(Instruction Code)  
Register Used  
DESCRIPTION  
Bypass  
(1111)  
Bypass Register  
Places the 1 bit bypass register between the TDI and TDO pins, which allows the BST data to pass  
synchronously through the selected device to adjacent devices during normal device operation. The Bypass  
instruction can be entered by holding TDI at a constant high value and completing an Instruction-Scan cycle.  
Idcode  
(0001)  
Boundary-Scan Register  
Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE to be serially shifted  
out of TDO. The IDCODE instruction permits blind interrogation of the components assembled onto a printed  
circuit board. Thus, in circumstances where the component population may vary, it is possible to determine  
what components exist in a product.  
7
1999 Jun 29  
Philips Semiconductors  
Product specification  
128 macrocell CPLD with enhanced clocking  
PZ3128A/PZ3128D  
3.3-Volt, In-System Programming (ISP)  
Terminations  
ISP is the ability to reconfigure the logic and functionality of a  
device, printed circuit board, or complete electronic system before,  
during, and after its manufacture and shipment to the end customer.  
ISP provides substantial benefits in each of the following areas:  
The CoolRunner PZ3128A/PZ3128D CPLDs are TotalCMOS  
devices. As with other CMOS devices, it is important to consider  
how to properly terminate unused inputs and I/O pins when  
fabricating a PC board. Allowing unused inputs and I/O pins to float  
can cause the voltage to be in the linear region of the CMOS input  
structures, which can increase the power consumption of the device.  
The PZ3128A/PZ3128D CPLDs have programmable on-chip  
pull-down resistors on each I/O pin. These pull-downs are  
automatically activated by the fitter software for all unused I/O pins.  
Note that an I/O macrocell used as buried logic that does not have  
the I/O pin used for input is considered to be unused, and the  
pull-down resistors will be turned on. We recommend that any  
unused I/O pins on the PZ3128A/PZ3128D device be left  
unconnected.  
• Design  
– Faster time-to-market  
– Debug partitioning and simplified prototyping  
– Printed circuit board reconfiguration during debug  
– Better device and board level testing  
• Manufacturing  
– Multi-Functional hardware  
– Reconfigurability for Test  
– Eliminates handling of “fine lead-pitch” components for  
programming  
There are no on-chip pull-down structures associated with the  
dedicated input pins. Philips recommends that any unused  
dedicated inputs be terminated with external 10kΩ pull-up resistors.  
– Reduced Inventory and manufacturing costs  
– Improved quality and reliability  
These pins can be directly connected to V or GND, but using the  
CC  
external pull-up resistors maintains maximum design flexibility  
should one of the unused dedicated inputs be needed due to future  
design changes.  
• Field Support  
– Easy remote upgrades and repair  
– Support for field configuration, re-configuration, and  
customization  
When using the JTAG/ISP functions, it is also recommended that  
10kΩ pull-up resistors be used on each of the pins associated with  
the four mandatory JTAG signals. Letting these signals float can  
cause the voltage on TMS to come close to ground, which could  
cause the device to enter JTAG/ISP mode at unspecified times. See  
the application notes ISP Design Considerations for CoolRunner  
CPLDs and Terminating CoolRunner I/O Pins for more  
information.  
The Philips PZ3128A/PZ3128D allows for 3.3-Volt, in-system  
programming/reprogramming of its EEPROM cells via its JTAG  
interface. An on-chip charge pump eliminates the need for  
externally-provided supervoltages, so that the PZ3128A/PZ3128D  
may be easily programmed on the circuit board using only the 3-volt  
supply required by the device for normal operation. A set of low-level  
ISP basic commands implemented in the PZ3128A/PZ3128D enable  
this feature. The ISP commands implemented in the Philips  
PZ3128A/PZ3128D are specified in Table 6. Please note that an  
ENABLE command must precede all ISP commands unless an  
ENABLE command has already been given for a preceding ISP  
command.  
Table 6. Low Level ISP Commands  
INSTRUCTION  
(Register Used)  
INSTRUCTION  
CODE  
DESCRIPTION  
Enable  
(ISP Shift Register)  
1001  
Enables the Erase, Program, and Verify commands. Using the ENABLE instruction before the  
Erase, Program, and Verify instructions allows the user to specify the outputs the device using  
the JTAG Boundary-Scan SAMPLE/PRELOAD command.  
Erase  
(ISP Shift Register)  
1010  
1011  
1100  
Erases the entire EEPROM array. The outputs during this operation can be defined by user by  
using the JTAG SAMPLE/PRELOAD command.  
Program  
(ISP Shift Register)  
Programs the data in the ISP Shift Register into the addressed EEPROM row. The outputs  
during this operation can be defined by user by using the JTAG SAMPLE/PRELOAD command.  
Verify  
(ISP Shift Register)  
Transfers the data from the addressed row to the ISP Shift Register. The data can then be  
shifted out and compared with the JEDEC file. The outputs during this operation can be defined  
by the user.  
8
1999 Jun 29  
Philips Semiconductors  
Product specification  
128 macrocell CPLD with enhanced clocking  
PZ3128A/PZ3128D  
JTAG and ISP Interfacing  
• Automated Test Equipment  
• Third party Programmers  
• High-End ISP Tools  
A number of industry-established methods exist for JTAG/ISP  
interfacing with CPLD’s and other integrated circuits. The Philips  
PZ3128A/PZ3128D supports the following methods:  
• PC Parallel Port  
• Workstation or PC Serial Port  
• Embedded Processor  
For more details on JTAG and ISP for the PZ3128A/PZ3128D, refer  
to the related application note: JTAG and ISP in Philips CPLDs.  
Table 7. Programming Specifications  
SYMBOL  
PARAMETER  
MIN.  
3.0  
MAX.  
UNIT  
DC Parameters  
V
V
supply program/verify  
3.6  
V
mA  
V
CCP  
CCP  
CC  
I
I
limit program/verify  
200  
CC  
V
V
V
V
Input voltage (High)  
Input voltage (Low)  
Output voltage (Low)  
Output voltage (High)  
Output current (Low)  
Output current (High)  
2.0  
IH  
0.8  
0.5  
V
IL  
V
SOL  
SOH  
2.4  
8
V
TDO_I  
mA  
mA  
OL  
TDO_I  
–8  
OH  
AC Parameters  
f
CLK maximum frequency  
Pulse width erase  
10  
100  
10  
MHz  
ms  
ms  
µs  
MAX  
PWE  
PWP  
Pulse width program  
PWV  
Pulse width verify  
10  
INIT  
Initialization time  
100  
10  
µs  
TMS_SU  
TDI_SU  
TMS_H  
TDI_H  
TDO_CO  
TMS setup time before TCK ↑  
TDI setup time before TCK ↑  
TMS hold time after TCK ↑  
TDI hold time after TCK ↑  
TDO valid after TCK ↓  
ns  
10  
ns  
25  
ns  
25  
ns  
40  
ns  
1
ABSOLUTE MAXIMUM RATINGS  
SYMBOL  
PARAMETER  
MIN.  
–0.5  
–1.2  
–0.5  
–30  
MAX.  
4.6  
UNIT  
V
2
V
V
V
Supply voltage  
DD  
I
Input voltage  
5.75  
5.5  
V
Output voltage  
V
OUT  
I
IN  
Input current  
30  
mA  
°C  
°C  
T
J
Maximum junction temperature  
Storage temperature  
–40  
150  
150  
T
str  
–65  
NOTE:  
1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at  
these or any other condition above those indicated in the operational and programming specification is not implied.  
2. The chip supply voltage must rise monotonically.  
OPERATING RANGE  
PRODUCT GRADE  
Commercial  
TEMPERATURE  
0 to +70°C  
VOLTAGE  
3.0 to 3.6 V  
2.7 to 3.6 V  
Industrial  
–40 to +85°C  
9
1999 Jun 29  
Philips Semiconductors  
Product specification  
128 macrocell CPLD with enhanced clocking  
PZ3128A/PZ3128D  
DC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES  
Commercial: 0°C ≤ T  
≤ +70°C; 3.0V ≤ V ≤ 3.6V  
amb  
DD  
SYMBOL  
PARAMETER  
TEST CONDITIONS  
MIN.  
MAX.  
UNIT  
V
V
V
V
V
V
Input voltage low  
V
DD  
V
DD  
= 3.0V  
= 3.6V  
0.8  
IL  
Input voltage high  
2.0  
V
IH  
I
Input clamp voltage  
Output voltage low  
V
= 3.0V, I = –18mA  
–1.2  
0.5  
V
DD  
IN  
V
= 3.0V, I = 12mA  
V
OL  
OH  
DD  
OL  
Output voltage high  
Input leakage current  
3-Stated output leakage current  
Standby current  
V
= 3.0V, I = –12mA  
2.4  
–10  
–10  
V
DD  
OH  
I
I
I
V
IN  
V
IN  
= 0 to 5.5 V  
= 0 to 5.5 V  
10  
10  
µA  
µA  
µA  
mA  
mA  
mA  
pF  
pF  
pF  
I
OZ  
1
V
DD  
= 3.6V, T = 0°C  
amb  
100  
2
DDQ  
V
= 3.6V, T  
= 0°C @ 1MHz  
= 0°C @ 50MHz  
amb  
DD  
amb  
1, 2  
I
Dynamic current  
DDD  
V
DD  
= 3.6V, T  
50  
3
I
Short circuit output current  
1 pin at a time for no longer than 1 second  
–50  
5
–200  
8
OS  
3
C
C
C
Input pin capacitance  
T
= 25°C, f = 1MHz  
= 25°C, f = 1MHz  
= 25°C, f = 1MHz  
IN  
amb  
3
Clock input capacitance  
T
amb  
12  
CLK  
3
I/O pin capacitance  
T
amb  
10  
I/O  
NOTES:  
1. See Table 2 on page 6 for typical values.  
2. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled and unloaded.  
Inputs are tied to V or ground. This parameter guaranteed by design and characterization, not testing.  
DD  
3. Typical values, not tested.  
1
AC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES  
Commercial: 0°C ≤ T  
≤ +70°C; 3.0V ≤ V ≤ 3.6V  
amb  
DD  
7
10  
12  
SYMBOL  
PARAMETER  
UNIT  
MIN. MAX. MIN. MAX. MIN. MAX.  
t
t
Propagation delay time, input (or feedback node) to output through PAL  
2
3
7.5  
9
2
3
10  
11.5  
7
2
3
12  
13.5  
8
ns  
ns  
PD_PAL  
Propagation delay time, input (or feedback node) to output through PAL  
& PLA  
PD_PLA  
t
t
t
t
t
t
t
t
f
f
f
t
Clock to out (global synchronous clock from pin)  
2
3.5  
5
5.5  
2
4
2
6
ns  
ns  
CO  
Setup time (from input or feedback node) through PAL  
Setup time (from input or feedback node) through PAL + PLA  
SU_PAL  
SU_PLA  
H
5.5  
7.5  
ns  
2
Hold time  
0
0
0
ns  
2
Clock High time  
2
2
2.5  
2.5  
3
3
ns  
CH  
2
Clock Low time  
ns  
CL  
2
Input Rise time  
100  
100  
100  
100  
100  
100  
ns  
R
2
Input Fall time  
ns  
F
2
Maximum FF toggle rate  
1/(t + t )  
CL  
250  
143  
111  
200  
118  
91  
167  
91  
MHz  
MHz  
MHz  
ns  
MAX1  
MAX2  
MAX3  
BUF  
CH  
2
Maximum internal frequency  
Maximum external frequency  
1/(t  
+ t  
)
SUPAL  
CF  
2
1/(t  
+ t  
)
71  
SUPAL  
CO  
2
Output buffer delay time  
2
2
2
8
Input (or feedback node) to internal feedback node delay time through  
t
t
2
3
5.5  
2
3
7.5  
2
3
ns  
ns  
PDF_PAL  
2
PAL  
Input (or feedback node) to internal feedback node delay time through  
7
9
9.5  
PDF_PLA  
2
PAL+PLA  
2
t
t
t
t
t
t
Clock to internal feedback node delay time  
3.5  
20  
8
4.5  
20  
5
ns  
µs  
ns  
ns  
ns  
ns  
CF  
INIT  
ER  
EA  
RP  
RR  
2
Delay from valid V to valid reset  
20  
10  
10  
10  
10  
DD  
2, 3  
Input to output disable  
9.5  
9.5  
9.5  
9.5  
2
Input to output valid  
8
2
Input to register preset  
9
2
Input to register reset  
9
NOTES:  
1. Specifications measured with one output switching. See Figure 6 and Table 8 for derating.  
2. This parameter guaranteed by design and characterization, not by test.  
3. Output C = 5pF.  
L
10  
1999 Jun 29  
Philips Semiconductors  
Product specification  
128 macrocell CPLD with enhanced clocking  
PZ3128A/PZ3128D  
DC ELECTRICAL CHARACTERISTICS FOR INDUSTRIAL GRADE DEVICES  
Industrial:  
–40°C ≤ T  
≤ +85°C; 2.7V ≤ V ≤ 3.6V  
amb  
DD  
SYMBOL  
PARAMETER  
TEST CONDITIONS  
MIN.  
MAX.  
UNIT  
V
V
IL  
V
IH  
V
I
Input voltage low  
Input voltage high  
Input clamp voltage  
V
DD  
V
DD  
= 2.7V  
= 3.6V  
0.8  
2.0  
V
V
= 2.7V, I = –18mA  
–1.2  
0.5  
V
DD  
IN  
V
= 2.7V, I = 8mA  
V
DD  
DD  
DD  
OL  
V
V
Output voltage low  
Output voltage high  
OL  
V
= 3.0V, I = 12mA  
0.5  
V
OL  
V
= 2.7V, I = –8mA  
2.4  
2.4  
V
OH  
OH  
V
= 3.0V, I = –12mA  
V
DD  
OH  
I
I
I
Input leakage current  
3-Stated output leakage current  
Standby current  
V
V
= 0 to 5.5 V  
= 0 to 5.5 V  
–10  
–10  
10  
10  
µA  
µA  
µA  
mA  
mA  
mA  
pF  
pF  
pF  
I
IN  
IN  
OZ  
1
V
= 3.6V, T  
= –40°C  
100  
2
DDQ  
DD  
amb  
V
= 3.6V, T  
= –40°C @ 1MHz  
= –40°C @ 50MHz  
amb  
DD  
amb  
1, 2  
I
Dynamic current  
DDD  
V
DD  
= 3.6V, T  
50  
3
I
Short circuit output current  
1 pin at a time for no longer than 1 second  
–50  
5
–230  
8
OS  
3
C
C
C
Input pin capacitance  
T
= 25°C, f = 1MHz  
= 25°C, f = 1MHz  
= 25°C, f = 1MHz  
IN  
amb  
3
Clock input capacitance  
T
12  
CLK  
I/O  
amb  
3
I/O pin capacitance  
T
10  
amb  
NOTES:  
1. See Table 2 on page 6 for typical values.  
2. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled and unloaded.  
Inputs are tied to V or ground. This parameter guaranteed by design and characterization, not testing.  
DD  
3. Typical values, not tested.  
1
AC ELECTRICAL CHARACTERISTICS FOR INDUSTRIAL GRADE DEVICES  
Industrial:  
–40°C ≤ T ≤ +85°C; 2.7V ≤ V ≤ 3.6V  
amb DD  
10  
15  
SYMBOL  
PARAMETER  
UNIT  
MIN.  
2
MAX.  
10  
MIN.  
2
MAX.  
15  
t
t
t
t
t
t
t
t
t
t
f
f
f
t
t
t
t
t
t
t
t
t
Propagation delay time, input (or feedback node) to output through PAL  
Propagation delay time, input (or feedback node) to output through PAL & PLA  
Clock to out (global synchronous clock from pin)  
Setup time (from input or feedback node) through PAL  
Setup time (from input or feedback node) through PAL + PLA  
Hold time  
ns  
ns  
PD_PAL  
PD_PLA  
CO  
3
11.5  
7
3
16.5  
8
2
2
ns  
4
6
ns  
SU_PAL  
SU_PLA  
H
5.5  
7.5  
ns  
0
0
ns  
Clock High time  
3
3
4
4
ns  
CH  
Clock Low time  
ns  
CL  
Input Rise time  
100  
100  
100  
100  
ns  
R
Input Fall time  
ns  
F
2
Maximum FF toggle rate  
1/(t + t )  
CL  
167  
111  
91  
125  
87  
MHz  
MHz  
MHz  
ns  
MAX1  
MAX2  
MAX3  
BUF  
CH  
2
Maximum internal frequency  
Maximum external frequency  
1/(t  
+ t  
)
SUPAL  
CF  
2
1/(t  
+ t  
)
77  
SUPAL  
CO  
2
Output buffer delay time  
2
8
2
9
2
Input (or feedback node) to internal feedback node delay time through PAL  
2
3
2
3
ns  
PDF_PAL  
PDF_PLA  
CF  
2
Input (or feedback node) to internal feedback node delay time through PAL+PLA  
9.5  
5
10.5  
5.5  
20  
12  
12  
12  
12  
ns  
2
Clock to internal feedback node delay time  
ns  
2
Delay from valid V to valid reset  
20  
10  
10  
10  
10  
µs  
INIT  
DD  
2, 3  
Input to output disable  
ns  
ER  
2
Input to output valid  
ns  
EA  
2
Input to register preset  
ns  
RP  
2
Input to register reset  
ns  
RR  
NOTES:  
1. Specifications measured with one output switching. See Figure 6 and Table 8 for derating.  
2. This parameter guaranteed by design and characterization, not by test.  
3. Output C = 5pF.  
L
11  
1999 Jun 29  
Philips Semiconductors  
Product specification  
128 macrocell CPLD with enhanced clocking  
PZ3128A/PZ3128D  
SWITCHING CHARACTERISTICS  
V
DD  
COMPONENT  
VALUES  
390Ω  
S1  
R1  
R2  
C1  
390Ω  
R1  
R2  
35pF  
V
IN  
V
OUT  
MEASUREMENT  
S1  
S2  
C1  
t
Open  
Closed  
Open  
PZH  
t
Closed  
Closed  
PZL  
t
P
Closed  
S2  
NOTE: For t  
and t  
C = 5pF, and 3-State levels are  
PHZ  
PLZ  
measured 0.5V from steady state active level.  
SP00699  
VOLTAGE WAVEFORM  
V
= 3.3V, 25°C  
DD  
6.1  
6.0  
+3.0V  
90%  
5.9  
5.8  
5.7  
5.6  
5.5  
10%  
0V  
t
PD_PAL  
(ns)  
t
R
t
F
1.5ns  
1.5ns  
SP00368  
MEASUREMENTS:  
All circuit delays are measured at the +1.5V level of  
inputs and outputs, unless otherwise specified.  
5.4  
5.3  
Input Pulses  
5.2  
5.1  
1
2
4
8
12  
16  
NUMBER OF OUTPUTS SWITCHING  
SP00698  
Figure 6.  
t
vs. Outputs Switching  
PD_PAL  
Table 8. t  
DD  
vs. Number of Outputs Switching  
PD_PAL  
= 3.3V, 25°C  
V
NUMBER OF  
OUTPUTS  
1
2
4
8
12  
16  
Typical (ns)  
5.3  
5.3  
5.4  
5.6  
5.9  
6.1  
12  
1999 Jun 29  
Philips Semiconductors  
Product specification  
128 macrocell CPLD with enhanced clocking  
PZ3128A/PZ3128D  
PIN DESCRIPTIONS  
100-Pin Thin Quad Flat Package  
128-Pin Low Profile Quad Flat Package  
128  
103  
100  
76  
1
102  
75  
1
TQFP  
LQFP  
25  
51  
38  
65  
26  
Pin Function  
50  
39  
Pin Function  
64  
Pin Function  
Pin Function  
1
2
I/O-A2  
I/O-A0  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
I/O-D4  
I/O-D2  
I/O-D0/CLK2  
GND  
V
DD  
I/O-E0/CLK1  
I/O-E2  
I/O-E4  
GND  
I/O-E5  
I/O-E7  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
I/O-G8  
Pin Function  
Pin Function  
I/O-G10  
I/O-G12  
I/O-G13  
I/O-G15 (TDO)  
GND  
1
2
3
I/O-A3  
I/O-A2  
I/O-A0  
NC  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
I/O-D7  
I/O-D5  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
V
DD  
3
V
DD  
I/O-G5  
I/O-G7  
I/O-G8  
I/O-G10  
I/O-G11  
I/O-G12  
I/O-G13  
I/O-G15 (TDO)  
GND  
4
5
6
7
I/O-B15 (TDI)  
I/O-B13  
I/O-B12  
I/O-B10  
I/O-B8  
V
DD  
4
I/O-D4  
I/O-D3  
I/O-D2  
I/O-D0/CLK2  
GND  
V
DD  
I/O-E0/CLK1  
I/O-E2  
I/O-E3  
I/O-E4  
GND  
I/O-E5  
I/O-E7  
I/O-E8  
I/O-E10  
I/O-E11  
I/O-E12  
I/O-E13  
I/O-E15  
V
DD  
I/O-F0  
NC  
5
NC  
I/O-H0  
6
NC  
8
I/O-H2  
7
V
DD  
9
I/O-B7  
I/O-H4  
8
9
I/O-B15 (TDI)  
I/O-B13  
I/O-B12  
I/O-B11  
I/O-B10  
I/O-B8  
I/O-B7  
I/O-B5  
GND  
I/O-B4  
I/O-B3  
I/O-B2  
I/O-B0  
I/O-C15 (TMS)  
I/O-C13  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
I/O-B5  
GND  
I/O-B4  
I/O-B2  
I/O-H5  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
I/O-H7  
I/O-E8  
I/O-H8  
NC  
NC  
NC  
I/O-E10  
I/O-E12  
I/O-E13  
I/O-E15  
I/O-H10  
I/O-B0  
V
I/O-C15 (TMS)  
I/O-C13  
I/O-C12  
DD  
I/O-H12  
I/O-H13  
I/O-H15  
GND  
100 I/O-H0  
101 I/O-H2  
102 I/O-H3  
103 I/O-H4  
104 I/O-H5  
105 I/O-H7  
106 I/O-H8  
107 I/O-H10  
V
DD  
V
I/O-F0  
I/O-F2  
I/O-F4  
I/O-F5  
I/O-F7  
I/O-F8  
I/O-F10  
GND  
I/O-F12  
I/O-F13  
I/O-F15 (TCK)  
I/O-G0  
I/O-G2  
I/O-G4  
DD  
I/O-C10  
I/O-C8  
I/O-C7  
I/O-C5  
I/O-C4  
I/O-C2  
I/O-C0  
GND  
I/O-D15  
I/O-D13  
I/O-D12  
I/O-D10  
I/O-D8  
I/O-D7  
I/O-D5  
IN0/CLK0  
IN2-gtsn  
IN1  
IN3  
108  
V
DD  
V
DD  
I/O-C12  
I/O-C11  
109 I/O-H11  
110 I/O-H12  
111 I/O-H13  
112 I/O-H15  
113 GND  
114 IN0/CLK0  
115 IN2-gtsn  
116 IN1  
I/O-A15/CLK3  
I/O-A13  
I/O-A12  
GND  
V
DD  
I/O-C10  
I/O-C8  
I/O-C7  
I/O-C5  
I/O-C4  
I/O-C3  
I/O-C2  
NC  
NC  
NC  
I/O-C0  
GND  
I/O-D15  
I/O-D13  
I/O-D12  
I/O-D11  
I/O-D10  
I/O-D8  
NC  
NC  
I/O-F2  
I/O-F3  
I/O-F4  
I/O-F5  
I/O-F7  
I/O-F8  
I/O-F10  
GND  
I/O-F11  
I/O-F12  
I/O-F13  
I/O-F15(TCK)  
I/O-G0  
I/O-G2  
I/O-G3  
I/O-G4  
I/O-A10  
I/O-A8  
I/O-A7  
V
DD  
I/O-A5  
I/O-G5  
I/O-G7  
117 IN3  
V
100 I/O-A4  
DD  
118  
V
DD  
119 I/O-A15/CLK3  
120 I/O-A13  
121 I/O-A12  
122 I/O-A11  
123 GND  
124 I/O-A10  
125 I/O-A8  
126 I/O-A7  
127 I/O-A5  
128 I/O-A4  
SP00485  
SP00469A  
13  
1999 Jun 29  
Philips Semiconductors  
Product specification  
128 macrocell CPLD with enhanced clocking  
PZ3128A/PZ3128D  
Package Thermal Characteristics  
0
10  
20  
30  
40  
50  
Philips Semiconductors uses the Temperature Sensitive Parameter  
PERCENTAGE  
REDUCTION IN  
(%)  
(TSP) method to test thermal resistance. This method meets  
Mil-Std-883C Method 1012.1 and is described in Philips 1995 IC  
Package Databook. Thermal resistance varies slightly as a function  
of input power. As input power increases, thermal resistance  
changes approximately 5% for a 100% change in power.  
Θ
JA  
Figure 7 is a derating curve for the change in Θ with airflow based  
JA  
on wind tunnel measurements. It should be noted that the wind flow  
dynamics are more complex and turbulent in actual applications  
than in a wind tunnel. Also, the test boards used in the wind tunnel  
contribute significantly to forced convection heat transfer, and may  
not be similar to the actual circuit board, especially in size.  
PLCC/  
QFP  
Package  
100-pin TQFP  
128-pin LQFP  
Θ
JA  
0
1
2
3
4
5
AIR FLOW (m/s)  
47.4 °C/W  
45.0 °C/W  
SP00419A  
Figure 7. Average Effect of Airflow on Θ  
JA  
14  
1999 Jun 29  
Philips Semiconductors  
Preliminary specification  
128 macrocell CPLD with enhanced clocking  
PZ3128A/PZ3128D  
TQFP100: plastic thin quad flat package; 100 leads; body 14 x 14 x 1.0 mm  
SOT386-1  
15  
1999 Jun 29  
Philips Semiconductors  
Preliminary specification  
128 macrocell CPLD with enhanced clocking  
PZ3128A/PZ3128D  
LQFP128: plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm  
SOT425-1  
16  
1999 Jun 29  
Philips Semiconductors  
Preliminary specification  
128 macrocell CPLD with enhanced clocking  
PZ3128A/PZ3128D  
NOTES  
17  
1999 Jun 29  
Philips Semiconductors  
Preliminary specification  
128 macrocell CPLD with enhanced clocking  
PZ3128A/PZ3128D  
Data sheet status  
[1]  
Data sheet  
status  
Product  
status  
Definition  
Objective  
specification  
Development  
This data sheet contains the design target or goal specifications for product development.  
Specification may change in any manner without notice.  
Preliminary  
specification  
Qualification  
This data sheet contains preliminary data, and supplementary data will be published at a later date.  
Philips Semiconductors reserves the right to make changes at any time without notice in order to  
improve design and supply the best possible product.  
Product  
specification  
Production  
This data sheet contains final specifications. Philips Semiconductors reserves the right to make  
changes at any time without notice in order to improve design and supply the best possible product.  
[1] Please consult the most recently issued datasheet before initiating or completing a design.  
Definitions  
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For  
detailed information see the relevant data sheet or data handbook.  
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one  
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or  
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended  
periods may affect device reliability.  
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips  
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or  
modification.  
Disclaimers  
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications  
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.  
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard  
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no  
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these  
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless  
otherwise specified.  
Philips Semiconductors  
811 East Arques Avenue  
P.O. Box 3409  
Copyright Philips Electronics North America Corporation 1999  
All rights reserved. Printed in U.S.A.  
Sunnyvale, California 94088–3409  
Telephone 800-234-7381  
Date of release: 06-99  
Document order number:  
9397 750 06161  
Philips  
Semiconductors  
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