PRELIMINARY
CYP15G0402DX
characters makes the associated link much more robust to
Table 6. BIST Status Bits
Status Description
incorrect framing. In this mode the framer does not adjust the
character clock boundary, but instead aligns the character to
the already recovered character clock. This ensures that the
recovered clock will not contain any significant phase changes
or hops during normal operation. This allows the recovered
clock to be distributed to other external circuits. In this framing
mode the character boundaries are only adjusted if the
selected framing character is detected at least twice within a
span of 50 bits, with both instances on identical 10-bit
character boundaries.
When RFMODE is HIGH, the alternate-mode multi-character
framer is enabled. Like Cypress-mode multi-character
framing, multiple framing characters must be detected to
adjust the character boundaries. In this mode, the data stream
must contain a minimum of four of the selected framing
characters, received as consecutive characters, before
character framing is adjusted.
BIST Mode (RXBISTEN is LOW)
0
0
0
1
0
1
0
7 BIST Data Compare. Data Character
compared correctly.
0
0
7 BIST Command Compare. Command
Character compared correctly.
2 BIST Last Good. Last Character of BIST
sequence detected and valid.
0
1
1
0
1
0
5 Reserved
4 BIST Last Bad. Last Character of BIST
sequence was detected invalid.
In systems that use 8B/10B coding running disparity rules
prohibit the presence of multiple +COMMA characters as
consecutive characters, except for the K28.7 comma
character. Because of this, the combination of FRAMCHAR
LOW and RFMODE HIGH is not recommended. While framing
can still take place while following all 8B/10B coding rules, this
configuration prevents framing to the normal K28.5 character.
Framing is enabled for a channel when the associated RFENx
input is HIGH. When RFENx is LOW, the framer for the
associated channel is disabled. When a framer is disabled, no
changes are made to the recovered character boundaries on
that channel, regardless of the presence of framing characters
in the data stream.
1
0
1
1 BIST Start. RXBISTEN recognized on this
channel, but character compares have not
yet commenced. Also presented when the
receive PLL is tracking REFCLK instead of
the selected data stream.
1
1
1
1
0
1
6 BIST Error. While comparing characters, a
mismatch was found in one or more of the
decoded character bits.
3 BIST Wait. The receiver is comparing
characters. but has not yet found the start of
BIST character to enable the LFSR.
values of all BOE[x] signals are captured in the BIST Enable
Latch.These values remain in the BIST Enable Latch until
BISTLE is returned high to resample the input again. All
captured signals in the BIST Enable Latch are set HIGH and
BIST is disabled following a device reset by TRSTZ.
The LFSR is initialized by the BIST hardware once the external
enable (RXBISTENx) is recognized. The enable resets the
BIST LFSR to the BIST-loop start-code of D0.0. D0.0 is sent
only at the beginning of the BIST loop. The status of the BIST
progress and any character mismatches is appears as an
output on the RXDx[2:0] outputs.
Code rule violations or running disparity errors the BIST loop
will not cause an error indication. RXDx[2:0] indicates 01X for
one RXCLK cycle per BIST loop to indicate loop completion. This
can be used to check test pattern progress.
The specific patterns checked by each receiver are described
in detail in the Cypress application note “HOTLink Built-In
Self-Test.” The sequence compared by the CYP15G0402DX
is identical to that in the CY7B933 and CY7C924, allowing
interoperable systems to be built when used at compatible
serial signalling rates.
BIST LFSR
The output register of each Framer is normally used to pass
received characters to the associated output register. When
configured for BIST mode, this register becomes a signature
pattern generator. When in the BIST mode, a 511-character
sequence is generated that includes all Data and Special
Character codes, including the explicit violation symbols.This
provides a predictable but pseudo-random sequence that can
be matched to an identical LFSR in the attached Trans-
mitter(s). When synchronized with the received data stream,
the associated receiver checks each character received with
each character generated by the LFSR and indicates compare
errors and BIST status at the RXDx[2:0] bits of the output
register.
These generators are enabled by the associated BOE[x]
signals listed in Table 2 (when the BISTLE latch enable input
is HIGH).When the BISTLE signal is HIGH, any BOE[x] input
that is LOW enables the BIST generator/checker in the
associated receive channel. When BISTLE returns LOW, the
If a large number of errors are detected, the receive BIST state
machine aborts the compare operations and resets the LFSR
to look for the start of the BIST sequence again.
Power Control
The chip can be powered down one channel at a time. The
channel to be selected is controlled by BOE[7:0] latch. Both
the transmit and the receive channels are controlled by a
receive channel power latch and the transmit channel is
controlled by an output enable control system. Powering down
Document #: 38-02023 Rev. *B
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