CYM9288/CYM9289
Switching Characteristics Over the Operating Range[2]
60
66
Parameter
Clock
Description
Min.
Max.
Min.
Max.
Unit
tCYC
Clock Cycle Time
16.6
15.0
ns
MHz
ns
FMAX
tCH
Maximum Operating Frequency
Clock HIGH
60
66
6.0
6.0
5.0
5.0
tCL
Clock LOW
ns
Output Times
tCDV
Data Output Valid After CLK Rise
OE LOW to Output Valid[3, 5]
Data Output Hold After CLK Rise
Clock to High-Z[3, 4, 5]
12
6
10.5
6
ns
ns
ns
ns
ns
ns
ns
tEOV
tDOH
1.5
3.0
0
1.5
2.0
0
tCHZ
5.0
6.0
5.0
6.0
tCLZ
Clock to Low-Z[3, 4, 5]
tEOHZ
tEOLZ
Setup Times
tAS
OE HIGH to Output High-Z[3, 4, 5]
OE LOW to Output Low-Z[3, 4, 5]
Address Set-Up Before CLK Rise
Data Input Set-Up Before CLK Rise
WE, BWE[7:0] Set-Up Before CLK Rise
ADV/LD Set-Up Before CLK Rise
Chip Selects Set-Up
2.5
2.5
2.5
2.5
2.5
2.0
2.0
2.0
2.0
2.0
ns
ns
ns
ns
ns
tDS
tWES
tALS
tCES
Hold Times
tAH
Address Hold After CLK Rise
Data Input Hold After CLK Rise
WE, BWE[7:0] Hold After CLK Rise
ADV/LD Hold after CLK Rise
Chip Selects Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
tDH
tWEH
tALH
tCEH
Notes:
2. AC test conditions assume signal transition time of 2 ns or less, timing reference levels, input pulse levels and output loading shown in part (a) of AC Test
Load for 3.3V devices and (c) for 2.5V devices. .
3.
t
CHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with AC test conditions shown in part (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state
voltage.
4. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
5. This parameter is sampled and not 100% tested.
6
