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CYM9276APM-100C

型号：

CYM9276APM-100C

描述：

X36同步SRAM模块\n[ x36 Synchronous SRAM Module ]

品牌：

ETC[ ETC ]

页数：

13 页

PDF大小：

271 K

下载PDF手册
1CYM9277  
CYM9275  
CYM9276A  
CYM9277B  
CYM9278  
64K x 36 SRAM Module  
128K x 36 SRAM Module  
256K x 36 SRAM Module  
512K x 36 SRAM Module  
surface mount packages on an epoxy laminate board with  
pins. The modules are designed to be incorporated into large  
memory arrays.  
Features  
• Operates at 133 MHz  
• Uses64Kx18/128Kx18or256Kx18high-performance  
synchronous SRAMs  
• 144-Position Angled DIMM from Berg p/n 61178  
• 3.3V inputs/data outputs  
The modules are configured as single banks or multiple banks  
depending on the SRAM used to make the module. Separate  
clock are provided for each of the banks. Separate clocks are  
provided for each of the SRAMs.  
Multiple ground pins and on-board decoupling capacitors en-  
sure high performance with maximum noise immunity.  
Functional Description  
The CYM9275, CYM9276A, CYM9277B, and the CYM9278  
are high-performance synchronous pipelined memory mod-  
ules organized as 64K, 128K, 256K, 512K by 36 bits. These  
modules are constructed using either 128K x 18 SRAMs  
(9275, 9276A, 9277B) or 256K x 18 SRAMs (9278) in plastic  
All components on the cache modules are surface mounted on  
a multi-layer epoxy laminate (FR-4) substrate. The contact  
pins are plated with 150 micro-inches of nickel covered by  
30 micro-inches of gold flash.  
Logic Block Diagram -CYM9275  
A[15:0]  
(2) 128K x 18 SRAMs  
A
15:0  
WE  
SGW  
D[0:31]  
DQ[0:3]  
OE  
CS  
OE  
D[0:15]  
DQ[0:1]  
OE  
CS  
CS  
BW[0:3]  
BWE  
WEH  
WEL  
ADSC  
ADSP  
CLK[0:1]  
CLK  
Bank 0  
CLK[0:1]  
PD  
1
PD  
0
GND NC  
Bank0  
64Kx36  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
April 2, 2001  
CYM9275  
CYM9276A  
CYM9277B  
CYM9278  
LogicBlockDiagram- CYM9276A  
A[16:0]  
(2) 128K x 18 SRAMs  
A
16:0  
WE  
SGW  
D[0:31]  
OE0  
CS0  
OE[0:1]  
CS[0:1]  
BW[0:3]  
D[0:15]  
DQ[0:1]  
OE  
CS  
DQ[0:3]  
BWE  
WEH  
WEL  
ADSC  
ADSP  
CLK[0:3]  
CLK  
Bank0  
CLK[0:1]  
(2) 128K x 18 SRAMs  
A
16:0  
SGW  
OE  
OE1  
CS1  
D[0:15]  
DQ[0:1]  
CS  
BWE  
WEH  
WEL  
ADSC  
CLK  
Bank1  
CLK[2:3]  
9276A  
PD  
PD  
1
0
Bank0  
NC  
GND  
128Kx36  
2
CYM9275  
CYM9276A  
CYM9277B  
CYM9278  
LogicBlockDiagram- CYM9277B / CYM9278  
A[17:0]  
(2) 256K x 18 SRAMs  
A
17:0  
WE  
SGW  
D[0:31]  
DQ[0:3]  
OE0  
OE[0:1]  
CS[0:1]  
BW[0:3]  
D[0:15]  
DQ[0:1]  
OE  
CS  
CS[0]  
BWE  
WEH  
WEL  
ADSC  
ADSP  
CLK[0:3]  
CLK  
Bank0  
CLK[0:1]  
(2) 256K x 18 SRAMs  
A
17:0  
SGW  
OE1  
D[0:15]  
DQ[0:1]  
OE  
CS  
CS[1]  
BWE  
WEH  
WEL  
ADSC  
CLK  
Bank1  
CLK[2:3]  
9277B/9278  
PD  
PD  
0
1
GND GND Bank0  
Bank0 and 1  
256KX36  
512KX36  
NC  
NC  
Selection Guide  
Synchronous Cache Module  
CYM9276A CYM9277B  
133 100 133  
256 K x 72  
CYM9275  
133 100  
64 K x 72  
CYM9278  
100  
512 K x 72  
Part Number  
100  
133  
Module Size  
128 K x 72  
SRAMs Used  
4 of 128K x 18 (High  
address bit tied Off)  
8 of 128K x 18 (High  
address bit tied Off)  
8 of 128K x 18  
8 of 256K x 18  
System Clock 133  
(MHz)  
100  
133  
100  
133  
100  
133  
4.5 ns  
100  
Data tCO  
4.5 ns  
5.5 ns  
4.5 ns  
5.5 ns  
4.5 ns  
5.5 ns  
5.5 ns  
3
CYM9275  
CYM9276A  
CYM9277B  
CYM9278  
Pin Configuration  
Dual Read-Out SIMM (DIMM)  
Top View  
1
3
2
GND  
GND  
A
0
4
A
1
A
A
5
6
8
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
2
3
A
4
CC3  
NC  
A
5
7
V
9
V
CC3  
11  
13  
NC  
NC  
NC  
GND  
GND  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
35  
37  
39  
41  
43  
A
6
A
7
A
8
A
9
A
A
11  
10  
NC  
CC3  
NC  
V
V
A
13  
CC3  
A
14  
12  
A
A
15  
A
A
16  
17  
GND  
PD  
0
GND  
BW[0]  
CS[0]  
GND  
CLK1  
GND  
GND  
PD  
1
38  
40  
GND  
BW[1]  
OE[0]  
42  
44  
46  
48  
50  
52  
54  
56  
GND  
CLK0  
GND  
45  
47  
49  
51  
53  
55  
57  
59  
D
CC3  
D
CC3  
0
1
V
V
D
D
2
3
5
D
D
D
D
4
6
58  
60  
7
GND  
GND  
62  
64  
66  
68  
70  
72  
74  
76  
78  
80  
82  
84  
86  
88  
90  
92  
94  
96  
98  
100  
102  
104  
106  
108  
110  
112  
114  
116  
118  
120  
122  
124  
126  
128  
130  
61  
63  
65  
67  
69  
71  
V
V
CC3  
9
CC3  
D
D
8
D
D
10  
11  
GND  
GND  
D
D
12  
13  
15  
D
D
14  
DQ  
73  
75  
77  
79  
81  
83  
85  
87  
89  
91  
93  
95  
97  
99  
101  
103  
105  
107  
109  
DQ  
NC  
NC  
GND  
ADSP  
NC  
V
0
1
NC  
NC  
GND  
WE  
NC  
V
CC3  
CC3  
NC  
NC  
NC  
NC  
NC  
NC  
V
V
CC3  
NC  
NC  
CC3  
NC  
NC  
NC  
NC  
GND  
BW[3]  
OE[1]  
GND  
BW[2]  
CS[1]  
V
CC3  
V
CC3  
D
D
NC  
NC  
NC  
GND  
CLK2  
GND  
D
GND  
D
D
D
D
V
D
D
NC  
NC  
NC  
GND  
CLK3  
GND  
D
GND  
D
D
D
D
16  
18  
17  
19  
111  
113  
115  
117  
119  
121  
123  
125  
127  
129  
131  
133  
135  
137  
139  
141  
143  
20  
21  
22  
24  
23  
25  
27  
29  
132  
134  
26  
28  
136  
138  
140  
142  
144  
CC3  
V
CC3  
D
D
30  
31  
DQ  
GND  
DQ  
2
3
GND  
4
CYM9275  
CYM9276A  
CYM9277B  
CYM9278  
Pin Definitions  
Signal  
Description  
VCC3  
3V Supply  
GND  
Ground  
A[17:0]  
ADSP  
OE[1:0]  
BW[0:3]  
WE  
Addresses from processor  
Address strobe from the processor  
Output Enables for each of the banks  
Byte writes  
Global Write  
CS[1:0]  
PD0–PD1  
D[31:0]  
DQ[3:0]  
CLK[0:3]  
NC  
Chip Select for the two banks  
Presence Detect output pins  
Data lines from processor  
Data Parity lines from processor  
Clock lines to the module  
Signal not connected on module  
Reserved  
RSVD  
Presence Detect Pins  
PD1  
GND  
NC  
PD0  
NC  
CYM9275 – 64K x 36  
CYM9276A – 128K x 36  
CYM9277B – 256K x 36  
CYM9278 – 512K x 36  
GND  
GND  
NC  
GND  
NC  
5
CYM9275  
CYM9276A  
CYM9277B  
CYM9278  
DC Input Voltage ........................................... –0.5V to +4.6V  
Output Current into Outputs (LOW)............................. 20 mA  
Maximum Ratings  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Operating Range  
Storage Temperature ................................. –55°C to +125°C  
Range  
Ambient Temperature  
VCC  
Ambient Temperature  
with Power Applied......................................... –0°C to +70°C  
Commercial  
0°C to +70°C  
3.3V ± 5%  
3.3V Supply Voltage to Ground Potential...... –0.5V to +4.5V  
DC Voltage Applied to Outputs  
in High Z State.............................................. –0.5V to +4.6V  
Electrical Characteristics Over the Operating Range  
Parameter  
VIH  
Description  
Input HIGH Voltage  
Input LOW Voltage  
Output HIGH Voltage  
Output LOW Voltage  
Test Condition  
Min.  
2.2  
Max.  
Unit  
V
VCC + 0.3  
0.8  
VIL  
–0.3  
2.4  
V
VOH  
VCC = Min. IOH = −4 mA  
VCC = Min. IOL = 8 mA  
V
VOL  
0.4  
350  
V
ICC (9275)  
ICC (9276A)  
ICC (9277B)  
ICC (9278)  
VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC  
VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC  
VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC  
VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC  
mA  
mA  
mA  
mA  
500  
1000  
1200  
Capacitance[1]  
Parameter  
Description  
Test Conditions  
Part No.  
9275  
Max.  
12  
7
Unit  
CA  
Address Input Capacitance  
Control Input Capacitance  
Input / Output Capacitance  
Clock Capacitance  
TA = 25°C, f = 1 MHz,  
VCC = 5.0V  
pF  
9276A  
9277B  
9278  
14  
20  
12  
8
CI  
TA = 25°C, f = 1 MHz,  
VCC = 5.0V  
9275  
9276A  
9277B  
9278  
16  
20  
9
CO  
TA = 25°C, f = 1 MHz,  
VCC = 5.0V  
9275  
9276A  
9277B  
9278  
5
10  
16  
6
CCLK  
TA = 25°C, f = 1 MHz,  
VCC = 5.0V  
9275  
9276A  
9277B  
9278  
3
3
5
Note:  
1. Tested initially and after any design or process changes that may affect these parameters.  
6
CYM9275  
CYM9276A  
CYM9277B  
CYM9278  
AC Test Loads and Waveforms[3]  
R1  
V
CCQ  
OUTPUT  
ALL INPUT PULSES  
OUTPUT  
3.3V  
GND  
90%  
10%  
R = 50 Ω  
L
90%  
10%  
R2  
5 pF  
V = 1.5V  
L
INCLUDING  
JIGAND  
≤ 3 ns  
≤ 3 ns  
(a)  
(b)[2]  
SCOPE  
Switching Characteristics Over the Operating Range  
CYM9275/76A/77B/78  
133 MHz 100 MHz  
Min. Max.  
Parameter  
tCYC  
Description  
Min.  
Max.  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Clock Cycle Time  
Clock HIGH  
7.5  
1.9  
1.9  
2
10  
3.5  
3.5  
2
tCH  
tCL  
Clock LOW  
tAS  
Address Set-Up Before CLK Rise  
Address Hold After CLK Rise  
Data Output Valid After CLK Rise  
Data Output Hold After CLK Rise  
ADSP, ADSC Set-Up Before CLK Rise  
ADSP, ADSC Hold After CLK Rise  
WH, WL Set-Up Before CLK Rise  
WH, WL Hold After CLK Rise  
Data Input Set-Up Before CLK Rise  
Data Input Hold After CLK Rise  
Chip Select Set-Up  
tAH  
0.5  
0.5  
tCO  
4.5  
5.5  
tDOH  
tADS  
tADSH  
tWES  
tWEH  
tDS  
3
2
3
3.1  
0.5  
2
0. 5  
2
0.5  
2
0.5  
2
tDH  
0.5  
2
0.5  
2
tCSS  
tCSH  
tEOZ  
Chip Select Hold After CLK Rise  
OE HIGH to Output High Z[4]  
OE LOW to Output Valid  
0.5  
0.5  
7
7
tEOV  
4.5  
5.5  
Notes:  
2. Resistor values for VCCQ = 3.3V are R1 = 317Ω and R2 = 351 Ω.  
3. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output  
loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) of AC test loads. All measurements are made at room temperature.  
4. tEOZ is specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.  
7
CYM9275  
CYM9276A  
CYM9277B  
CYM9278  
Switching Waveforms  
Write  
Single Write  
tCYC  
tADH  
Burst Write  
Pipelined Write  
tCH  
Unselected  
CLK  
tADS  
tCL  
ADSP ignored with CE1 inactive  
ADSP  
ADSC  
ADV  
tADH  
tADS  
ADSC initiated write  
tADVH  
tADVS  
tAS  
ADV Must Be Inactive for ADSP Write  
WD3  
ADD  
GW  
WE  
WD1  
WD2  
tAH  
tWH  
tWH  
tWS  
tWS  
tCES  
tCEH  
CE1 masks ADSP  
CE  
1
tCEH  
tCES  
Unselected with CE2  
CE  
2
CE  
3
tCES  
tCEH  
OE  
tDH  
tDS  
High-Z  
High-Z  
Data-  
In  
3a  
2a  
1a  
2b  
2c  
2d  
= DON’T CARE  
= UNDEFINED  
8
CYM9275  
CYM9276A  
CYM9277B  
CYM9278  
Switching Waveforms (continued)  
Read [5, 6, 7]  
Burst Read  
Single Read  
Unselected  
tCYC  
tCH  
Pipelined Read  
CLK  
tADH  
tADS  
tCL  
ADSP ignored with CE1 inactive  
ADSP  
tADS  
ADSC initiated read  
ADSC  
ADV  
tADVS  
tADH  
Suspend Burst  
tADVH  
tAS  
ADD  
GW  
RD3  
RD1  
RD2  
tAH  
tWS  
tWS  
tWH  
WE  
tCES  
tCEH  
tWH  
CE1 masks ADSP  
CE1  
Unselected with CE2  
CE2  
tCES  
tCEH  
CE3  
OE  
tCES  
tEOV  
tCEH  
tOEHZ  
tDOH  
tCO  
Data Out  
2c  
1a  
3a  
2d  
2a  
2b  
tCLZ  
tCHZ  
= DON’T CARE  
= UNDEFINED  
Notes:  
5. OE is LOW throughout this operation.  
6. If ADSP is asserted while CS is HIGH, ADSP will be ignored.  
7. ADSP has no effect on ADV, WL, and WH if CS is HIGH.  
9
CYM9275  
CYM9276A  
CYM9277B  
CYM9278  
Switching Waveforms (continued)  
Read / Write  
Single Read  
tCYC  
Single Write  
tCH  
Unselected  
Burst Read  
Pipelined Read  
CLK  
tADH  
tADS  
tCL  
ADSP ignored with CE1 inactive  
ADSP  
ADSC  
ADV  
tADS  
tADVS  
tADH  
tAS  
tADVH  
WD2  
ADD  
RD1  
RD3  
tAH  
GW  
WE  
CE1  
tWS  
tWS  
tWH  
tCES  
tCEH  
tWH  
CE1 masks ADSP  
CE2  
CE3  
tCES  
tCEH  
tEOV  
tCES  
tCEH  
OE  
tEOHZ  
tDS  
tDH  
tDOH  
See Note.  
2a  
tEOLZ  
tCO  
3b  
Out  
3a  
Out  
3c  
Out  
3d  
Out  
Data In/Out  
1a  
2a  
In  
Out  
Out  
tCHZ  
= UNDEFINED  
= DON’T CARE  
10  
CYM9275  
CYM9276A  
CYM9277B  
CYM9278  
Switching Waveforms (continued)  
Pipeline Timing  
tCYC  
tCL  
tCH  
CLK  
tAS  
WD1  
WD2  
WD3  
WD4  
RD1  
RD2  
RD3  
RD4  
ADD  
tADS  
tADH  
ADSC initiated Reads  
ADSC  
ADSP initiated Reads  
ADSP  
ADV  
tCEH  
tCES  
CE1  
CE  
tWES  
tWEH  
WE  
OE  
ADSP ignored  
with CE1 HIGH  
tCLZ  
Data In/Out  
1a  
In  
1a  
2a  
3a  
4a  
2a  
In  
3a  
In  
4a  
Out Out Out Out  
In  
tCO  
tDOH  
Back to Back Reads  
tCHZ  
= UNDEFINED  
= DON’T CARE  
11  
CYM9275  
CYM9276A  
CYM9277B  
CYM9278  
Ordering Information  
Speed  
(MHz)  
Package  
Name  
Operating  
Range  
Ordering Code  
Package Type  
Description  
100  
CYM9275PM-100C  
CYM9276APM-100C  
CYM9277BPM-100C  
CYM9278PM-100C  
CYM9275PM-133C  
CYM9276APM-133C  
CYM9277BPM-133C  
CYM9278PM-133C  
PM45  
PM45  
PM46  
PM46  
PM45  
PM45  
PM46  
PM46  
144-Pin Dual-Readout SIMM (DIMM) Sync 64K x 72  
144-Pin Dual-Readout SIMM (SIMM) Sync 128K x 72  
144-Pin Dual-Readout SIMM (DIMM) Sync 256K x 72  
144-Pin Dual-Readout SIMM (DIMM) Sync 512K x 72  
144-Pin Dual-Readout SIMM (DIMM) Sync 64K x 72  
144-Pin Dual-Readout SIMM (SIMM) Sync 128K x 72  
144-Pin Dual-Readout SIMM (DIMM) Sync 256K x 72  
144-Pin Dual-Readout SIMM (DIMM) Sync 512K x 72  
Commercial  
133  
Document #: 38-M-00083-*B  
Package Diagrams  
144-Pin Single-Sided DIMM PM45  
12  
CYM9275  
CYM9276A  
CYM9277B  
CYM9278  
Package Diagrams  
144-Pin Dual-Sided DIMM PM46  
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
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MERRIMAC

 		CYM-13R-9G 定向耦合器[ DIRECTIONAL COUPLER ] 2 页

SUMIDA

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ETC

 		CYM1220HD-10C X4 SRAM模块\n[ x4 SRAM Module ] 5 页

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ETC

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CYPRESS

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CYPRESS

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