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CYM8301BV33

型号:

CYM8301BV33

描述:

内存\n[ Memory ]

品牌:

ETC[ ETC ]

页数:

9 页

PDF大小:

338 K

CYM8301BV33  
512K x 24 Static RAM Module  
Writing the data bytes into the SRAM is accomplished when  
the chip select (CSx) controlling that byte is LOW and Write  
Enable (WE) is LOW.Data on the respective input/output pins  
(I/O) is then written into the memory location specified on the  
address pins (A0 through A18). Asserting all the (CSx) LOW  
and (WE) LOW will write the entire data (I/O023) into the  
memory. Output Enable (OE) is a dont care in a write mode.  
Features  
• High-density 12-Megabit SRAM module  
• Access time: 10 ns  
• Single 3.3V power supply  
• Low active power(1000 W max.)  
• TTL-compatible inputs and outputs  
• Available in standard 119-ball BGA  
• InterfacetoMotoroladigitalsignalprocessor(DSP)and  
analog devices  
Reading a byte is accomplished when the chip select (CSx)  
controlling that byte is LOW and Write Enable (WE) is LOW  
while the Output Enable (OE) is LOW.Under these conditions  
the contents of the memory location specified on the address  
pins will all appear on the specified data input/output pins (I/O).  
Asserting all the (CSx) LOW and (WE) LOW with Output  
Enable (OE) LOW will read the entire data (I/O0-23) from the  
memory.  
Functional Description  
The CYM8301BV33 is a 3.3V high-performance 12-Megabit  
static RAM organized as a 512K words by 24 bits. This module  
is constructed from three 512K × 8 SRAM dice mounted on a  
multi layer laminate substrate combined to form a 24 bit  
SRAM. CYM8301BV33 is a ideal single-chip solution for  
Motorolas DSP5630X or a two chip solution to Analog  
Devices ADSP2106XL.  
The data input/output pins (I/O023) are placed in a  
high-impedance state when the device is deselected (CE)  
HIGH, the outputs are disabled (OE) HIGH or during a Write  
operation (CE LOW, and WE LOW).  
For further details on Read and Write conditions, please see  
the truth table on page 7 of this data sheet.  
Each data byte is separately controlled by the individual chip  
selects(CE0,CE1,CE2). CE0 controls I/O07. CE1 controls  
I/O715. CE2 controls I/O1623.  
Functional Block Diagram  
A[18:0]  
I/O07  
I/O07  
CE  
WE  
OE  
CE0  
8
A[18:0]  
A[18:0]  
I/O815  
I/O023  
I/O07  
CE1  
WE  
OE  
CE  
WE  
OE  
8
A[18:0]  
I/O1623  
I/O07  
CE  
WE  
OE  
CE2  
8
Selection Guide  
CYM8301BV33-10 CYM8301BV33-12 CYM8301BV33-15 Unit  
Maximum Access Time  
Maximum Operating Current Commercial  
Industrial  
10  
300  
330  
30  
12  
270  
300  
30  
15  
255  
285  
30  
ns  
mA  
Maximum Standby Current  
Commercial/Industrial  
mA  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-05294 Rev. **  
Revised May 13, 2002  
CYM8301BV33  
Pin Configurations  
119 BGA  
Top View  
1
2
3
4
5
6
7
A
NC  
A
A
A
A
A
NC  
NC  
B
C
D
E
F
NC  
A
A
CE0  
NC  
A
A
I/O12  
I/O13  
I/O14  
I/O15  
I/O16  
I/O17  
NC  
NC  
VDD  
VSS  
VDD  
VSS  
VDD  
VSS  
VDD  
VSS  
VDD  
VSS  
VDD  
A
CE1  
VSS  
VDD  
VSS  
VDD  
VSS  
VDD  
VSS  
VDD  
VSS  
VDD  
VSS  
NC  
A
CE2  
VSS  
VDD  
VSS  
VDD  
VSS  
VDD  
VSS  
VDD  
VSS  
VDD  
VSS  
NC  
A
NC  
VDD  
VSS  
VDD  
VSS  
VDD  
VSS  
VDD  
VSS  
VDD  
VSS  
VDD  
A
I/O0  
I/O1  
I/O2  
I/03  
I/04  
I/O5  
NC  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
NC  
G
H
J
K
L
I/O18  
I/O19  
I/O20  
I/O21  
I/O22  
I/O23  
NC  
I/O6  
I/O7  
I/O8  
I/09  
I/O10  
I/O11  
NC  
M
N
P
R
T
A
WE  
OE  
A
U
NC  
A
A
A
A
NC  
Document #: 38-05294 Rev. **  
Page 2 of 9  
CYM8301BV33  
Current into Outputs (LOW)......................................... 20 mA  
Maximum Ratings  
Static Discharge Voltage ..........................................> 2001V  
(per MIL-STD-883, Method 3015)  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Latch-up Current.....................................................> 200 mA  
Storage Temperature .................................65°C to +150°C  
Ambient Temperature with  
Power Applied.............................................55°C to +125°C  
Operating Range  
Ambient  
Supply Voltage on VCC to Relative GND[1] ...... 0.5V to 4.6V  
Range  
Commercial  
Industrial  
Temperature  
0°C to +70°C  
40°C to +85°C  
VCC  
DC Voltage Applied to Outputs  
3.3V ± 5%  
3.3V ± 5%  
in High-Z State[1]....................................0.5V to VCC + 0.5V  
DC Input Voltage[1].................................0.5V to VCC + 0.5V  
Electrical Characteristics Over the Operating Range  
CYM8301BV33-10 CYM8301BV33-12/15  
Parameter  
VOH  
Description  
Test Conditions[2]  
VCC = Min.,  
Min.  
Max.  
Min.  
Max.  
Unit  
Output HIGH Voltage  
2.4  
2.4  
V
IOH = 4.0 mA  
VOL  
VIH  
Output LOW Voltage  
Input HIGH Voltage  
VCC = Min.,  
IOL = 8.0 mA  
0.4  
0.4  
V
V
2.2  
VCC  
+ 0.3  
2.2  
VCC  
+ 0.3  
VIL  
IIX  
Input LOW Voltage[1]  
Input Load Current  
0.5  
10  
10  
0.8  
+10  
+10  
0.5  
10  
10  
0.8  
+10  
+10  
V
GND < VI < VCC  
µA  
µA  
IOZ  
Output Leakage  
Current  
GND < VI < VCC  
,
Output Disabled  
ICC  
VCC Operating  
Supply Current  
VCC = Max.,  
IOUT = 0 mA,  
f = fMAX = 1/tRC  
300  
150  
30  
300  
150  
30  
mA  
mA  
mA  
ISB1  
Automatic CE  
Power-down Current  
TTL Inputs  
Max. VCC, CE > VIH  
VIN > VIH or  
VIN < VIL, f = fMAX  
ISB2  
Automatic CE  
Max. VCC,  
Power-down Current  
CMOS Inputs  
CE > VCC 0.3V,  
VIN > VCC 0.3V,  
or VIN < 0.3V, f = 0  
Capacitance[3]  
Parameter  
CIN  
Description  
Test Conditions  
TA = 25°C, f = 1 MHz,  
Max.  
Unit  
pF  
Input Capacitance  
Output Capacitance  
8
8
VCC = 3.3V  
COUT  
pF  
Notes:  
1. VIL (min.) = 2.0V for pulse durations of less than 20 ns.  
2. CE is a combination of CE1, CE2 and CE3.  
3. Tested initially and after any design or process changes that may affect these parameters.  
Document #: 38-05294 Rev. **  
Page 3 of 9  
CYM8301BV33  
AC Test Loads and Waveforms  
R1 317Ω  
ALL INPUT PULSES  
90%  
10%  
OUTPUT  
3.3V  
OUTPUT  
3.0V  
GND  
90%  
10%  
Z = 50Ω  
0
R = 50Ω  
L
R2  
351Ω  
5 pF  
3 ns  
3 ns  
= 1.5V  
VTH  
INCLUDING  
JIG AND  
SCOPE  
(b)  
(a)  
Switching Characteristics[4] Over the Operating Range  
CYM8301BV-10  
CYM8301BV-12  
CYM8301BV-15  
Parameter  
Read Cycle  
tRC  
Description[2]  
Min.  
10  
3
Max.  
Min.  
Max.  
Min.  
15  
3
Max.  
Unit  
Read Cycle Time  
12  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
Address to Data Valid  
10  
12  
15  
tOHA  
Data Hold from Address Change  
CE active to Data Valid  
OE LOW to Data Valid  
OE LOW to Low-Z  
3
tACE  
10  
7
12  
15  
tDOE  
7.5  
8.5  
tLZOE  
tHZOE  
tLZCE  
tHZCE  
tPU  
0
3
0
0
3
0
0
3
0
OE HIGH to High-Z[5, 6]  
CE Active to Low-Z[6]  
5
5
6
6
7
7
CE Inactive to High-Z[5, 6]  
CE Active to Power-up  
CE Inactive to Power-down  
tPD  
10  
12  
15  
Write Cycle[7, 8]  
tWC  
tSCE  
tAW  
tHA  
Write Cycle Time  
10  
9
12  
9
15  
9
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CE active to Write End  
Address Set-up to Write End  
Address Hold from Write End  
Address Set-up to Write Start  
WE Pulse Width  
9
9
10  
0
0
0
tSA  
0
0
0
tPWE  
tSD  
8
10  
6
11  
7
Data Set-up to Write End  
Data Hold from Write End  
WE HIGH to Low-Z[6]  
6
tHD  
0
0
0
tLZWE  
3
3
3
tHZWE  
WE LOW to High-Z[5, 6]  
5
6
7
Notes:  
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified  
I
OL/IOH  
.
5.  
tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.  
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.  
7. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of any of  
these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.  
8. The minimum Write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD  
.
Document #: 38-05294 Rev. **  
Page 4 of 9  
CYM8301BV33  
Switching Waveforms  
Read Cycle No. 1[9, 10]  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
Read Cycle No. 2 (OE Controlled)[2, 10, 11]  
ADDRESS  
CE  
t
RC  
t
ACE  
OE  
t
HZOE  
t
DOE  
t
HZCE  
t
LZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA OUT  
DATA VALID  
t
LZCE  
t
PD  
I
t
PU  
CC  
V
CC  
50%  
50%  
SUPPLY  
CURRENT  
I
SB  
Write Cycle No. 1 (CE Controlled)[2, 12, 13]  
t
WC  
ADDRESS  
CE  
t
SCE  
t
SA  
t
SCE  
t
t
HA  
AW  
t
PWE  
WE  
t
t
HD  
SD  
DATA I/O  
DATA VALID  
Notes:  
9. Device is continuously selected. OE, CE = VIL.  
10. WE is HIGH for Read cycle.  
11. Address valid prior to or coincident with CE transition LOW.  
12. Data I/O is high impedance if OE = VIH  
.
13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.  
Document #: 38-05294 Rev. **  
Page 5 of 9  
CYM8301BV33  
Switching Waveforms (continued)  
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[12, 13]  
t
WC  
ADDRESS  
CE  
t
SCE  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
OE  
t
t
SD  
HD  
DATA VALID  
DATA I/O  
IN  
NOTE 14  
t
HZOE  
Write Cycle No. 3 (WE Controlled, OE LOW)[2, 13]  
t
WC  
ADDRESS  
CE  
t
SCE  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
t
HD  
SD  
NOTE 14  
DATA I/O  
DATA VALID  
t
t
LZWE  
HZWE  
Note:  
14. During this period the I/Os are in the output state and input signals should not be applied.  
Document #: 38-05294 Rev. **  
Page 6 of 9  
CYM8301BV33  
Truth Table  
CE1  
H
CE2  
H
CE3  
H
WE  
X
OE  
X
I/O0I/O23  
High-Z  
Mode  
Deselect/Power-down  
L
L
L
H
L
Data Out (I/O023)  
Read  
L
L
L
H
H
L
I/O High-Z  
Power-down  
Read  
L
H
H
H
Data Out (I/O07)  
I/O8-23 in High-Z  
H
H
L
H
L
H
H
L
L
Data Out (I/O815)  
I/O07 in High-Z  
I/O1623 in High-Z  
Read  
H
Data Out (I/O1623) Read  
I/O015 in High-Z  
L
L
L
H
L
L
H
H
L
L
L
L
L
X
X
X
X
Data In (I/O023)  
Data In (I/O07)  
Data In (I/O815)  
Data In (I/O1623)  
Write  
Write  
Write  
Write  
H
H
H
Ordering Information  
Package  
Name  
Speed (ns)  
Ordering Code  
CYM8301BV33 - 10BGC  
CYM8301BV33 - 10BGI  
CYM8301BV33 - 12BGC  
CYM8301BV33 - 12BGI  
CYM8301BV33 - 15BGC  
CYM8301BV33 - 15BGI  
Package Type  
Operating Range  
Commercial  
Industrial  
10  
BG119  
BG119  
BG119  
BG119  
BG119  
BG119  
119-ball BGA  
119-ball BGA  
119-ball BGA  
119-ball BGA  
119-ball BGA  
119-ball BGA  
12  
15  
Commercial  
Industrial  
Commercial  
Industrial  
Document #: 38-05294 Rev. **  
Page 7 of 9  
CYM8301BV33  
Package Diagram  
119-ball PBGA (14 x 22 x 2.4 mm) BG119  
51-85115-*A  
All product and company names mentioned in this document are the trademarks of their respective holders.  
Document #: 38-05294 Rev. **  
Page 8 of 9  
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
CYM8301BV33  
Document Title: CYM8301BV33 512K x 24 Static RAM Module  
Document Number: 38-05294  
ISSUE  
DATE  
ORIG. OF  
CHANGE  
REV.  
ECN NO.  
DESCRIPTION OF CHANGE  
**  
114945  
05/20/02  
DFP  
New Data Sheet  
Document #: 38-05294 Rev. **  
Page 9 of 9  
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