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CYM8210B

型号:

CYM8210B

描述:

内存\n[ Memory ]

品牌:

ETC[ ETC ]

页数:

8 页

PDF大小:

109 K

CYM8210BPM  
2M x 16 Static RAM Module  
structed using eight 512K x 8 SRAMs (CY62148) in SOJ pack-  
ages mounted on an epoxy laminate board with pins.  
Features  
• High-density 32-megabit SRAM module  
• Low active power  
Writing to each byte is accomplished by enabling the appropri-  
ate Chip Select (E0, E1, E2, E3) and write enable (WH or WL).  
Data on the input/output pins (I/O) is written into the mem-  
ory location specified on the address pins (A0 through A17).  
— 5.3W (max.) at 25 ns  
• SMD technology  
Reading the device is accomplished by taking the appropriate  
chip select (E0, E1, E2, E3) LOW while write enable (WE)  
remains HIGH. Under these conditions, the contents of the  
memory location specified on the address pins will appear on  
the data input/output pins (I/O).  
• TTL-compatible inputs and outputs  
• Low profile  
— Max. height of 0.725 in.  
• Available in 80 pin SIMM Package  
Functional Description  
The data input/output pins stay at the high-impedance state  
when write enable is LOW or the appropriate chip selects are  
HIGH.  
The CYM8210 is a high-performance 8-megabit static RAM  
module organized as 2M words by 16 bits. This module is con-  
The CYM8210 module is shipped as a 80 pin SIMM.  
Logic Block Diagram  
A
A  
17  
0
18  
G
WH  
WL  
E0  
512K x 8  
SRAM  
512K x 8  
SRAM  
I/O I/O  
I/O I/O  
8 15  
0
7
8
8
8
8
8
8
8
8
512K x 8  
SRAM  
512K x 8  
SRAM  
I/O I/O  
I/O I/O  
8
0
7
15  
15  
15  
E1  
E2  
E3  
512K x 8  
SRAM  
512K x 8  
SRAM  
I/O I/O  
I/O I/O  
0
7
8
512K x 8  
SRAM  
512K x 8  
SRAM  
I/O I/O  
I/O I/O  
8
0
7
8210 1  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-05008 Rev. **  
Revised April 26, 2001  
CYM8210BPM  
Selection Guide  
8210-70  
Maximum Access Time (ns)  
70  
Maximum Operating Current (mA)  
Maximum Standby Current (µA)  
158  
150  
Pin Configurations  
80-Pin  
SIMM  
Top View  
1
3
5
2
4
6
Vcc  
Vss  
NC  
G
WH  
NC  
WL  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
E2  
E0  
7
8
9
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
NC  
NC  
NC  
NC  
NC  
NC  
E3  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
E1  
Vss  
NC  
NC  
NC  
NC  
A18  
A16  
NC  
NC  
NC  
NC  
A17  
A15  
A13  
A11  
A9  
33  
35  
37  
39  
38  
40  
A14  
A12  
41  
42  
44  
46  
48  
50  
52  
54  
56  
58  
60  
62  
64  
66  
68  
70  
A10  
A 8  
A6  
A4  
A2  
43  
45  
47  
49  
51  
53  
55  
57  
59  
61  
63  
65  
67  
69  
71  
73  
75  
77  
79  
A 7  
A
5
A
3
A
1
A0  
Vss  
I/O15  
I/O13  
Vss  
I/O14  
I/O12  
I/O11  
I/O9  
I/O7  
I/O5  
I/O3  
I/O1  
I/O10  
I/O8  
I/O6  
I/O4  
I/O2  
I/O0  
Vcc  
Vss  
Vss  
NC  
72  
74  
76  
NC  
NC  
NC  
Vss  
78  
80  
NC  
Vss  
8210 2  
Document #: 38-05008 Rev. **  
Page 2 of 8  
CYM8210BPM  
DC Voltage Applied to Outputs  
in High Z State0.5V to +7.0V  
Maximum Ratings  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
DC Input Voltage0.5V to +7.0V  
Storage Temperature 55°C to +125°C  
Operating Range  
Ambient Temperature with  
Ambient  
Power Applied10°C to +85°C  
Range  
Temperature  
VCC  
Supply Voltage to Ground Potential0.5V to +7.0V  
Commercial  
0°C to +70°C  
5V ± 10%  
Electrical Characteristics Over the Operating Range  
CYM8210-70  
Parameter  
VOH  
Description  
Output HIGH Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
Test Conditions  
VCC = Min., IOH = 1.0 mA  
VCC = Min., IOL = 2.1 mA  
Min.  
Max.  
Unit  
V
2.4  
VOL  
VIH  
VIL  
IIX  
0.4  
VCC  
0.8  
V
2.2  
0.3  
10  
10  
V
V
Input Leakage Current  
GND < VI < VCC  
+10  
+10  
µA  
µA  
IOZ  
Output Leakage  
Current  
GND < VO < VCC  
,
Output Disabled  
ICC  
VCC Operating  
Supply Current  
VCC = Max., IOUT = 0 mA,  
CS < VIL  
158  
120  
150  
mA  
mA  
µA  
ISB1  
ISB2  
Automatic CS Power-  
Down Current[1]  
Max. VCC, CS > VIH,  
Min. Duty Cycle = 100%  
Automatic CS Power-  
Down Current[1]  
Max. VCC, CS > VCC - 0.2V,  
VIN > VCC 0.2V,  
or VIN < 0.2V  
Capacitance[2]  
Parameter  
CIN  
Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
Max.  
60  
Unit  
TA = 25°C, f = 1 MHz,  
VCC = 5.0V  
pF  
pF  
COUT  
50  
AC Test Loads and Waveforms  
R1481  
R1481Ω  
ALL INPUT PULSES  
90%  
5V  
5V  
OUTPUT  
3.0V  
90%  
OUTPUT  
R2  
255Ω  
R2  
255Ω  
10%  
10%  
GND  
< 5 ns  
30 pF  
5 pF  
< 5 ns  
INCLUDING  
JIG AND  
SCOPE  
INCLUDING  
JIG AND  
SCOPE  
82104  
82105  
(a)  
(b)  
Equivalent to:  
THÉVENIN EQUIVALENT  
167Ω  
OUTPUT  
1.73V  
Notes:  
1. A pull-up resistor to VCC on the E3/E2/E1/E0 input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given.  
2. Tested on a sample basis.  
Document #: 38-05008 Rev. **  
Page 3 of 8  
CYM8210BPM  
Switching Characteristics Over the Operating Range[3]  
70 ns  
Parameter  
Description  
Min.  
70  
Max.  
Unit  
READ CYCLE  
tRC  
Read Cycle Time  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
Address to Data Valid  
70  
tOHA  
tACS  
Output Hold from Address Change  
E3/E2/E1/E0 LOW to Data Valid  
G LOW to Data Valid  
10  
70  
35  
tDOE  
tLZOE  
tHZOE  
tLZCS  
tHZCS  
tPD  
G LOW to Low Z  
5
G HIGH to High Z  
25  
E3/E2/E1/E0 LOW to Low Z[4]  
E3/E2/E1/E0 HIGH to High Z[4, 5]  
E3/E2/E1/E0 HIGH to Power-Down  
10  
25  
70  
WRITE CYCLE[6]  
tWC  
Write Cycle Time  
70  
60  
60  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tSCS  
E3/E2/E1/E0 LOW to Write End  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WH/WL Pulse Width  
tAW  
tHA  
tSA  
0
tPWE  
tSD  
55  
25  
0
Data Set-Up to Write End  
Data Hold from Write End  
WH/WL HIGH to Low Z  
tHD  
tLZWE  
tHZWE  
5
WH/WL LOW to High Z[5]  
25  
Notes:  
3. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified  
OL/IOH and 30-pF load capacitance.  
4. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device. These parameters are guaranteed by design and not 100% tested.  
5. HZCS and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage.  
I
t
6. The internal write time of the memory is defined by the overlap of E3/E2/E1/E0 LOW and WH/WL LOW. Both signals must be LOW to initiate a write and either  
signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.  
Document #: 38-05008 Rev. **  
Page 4 of 8  
CYM8210BPM  
Switching Waveforms  
Read Cycle No. 1[7, 8]  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
1841A6  
Read Cycle No. 2[7, 9]  
t
RC  
E3/E2/E1/E0  
t
ACS  
G
t
HZOE  
t
DOE  
t
HZCS  
t
LZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA VALID  
DATA OUT  
t
82107  
LZCS  
Write Cycle No. 1 (WE Controlled)[6]  
t
WC  
ADDRESS  
t
SCS  
E3/E2/E1/E0  
t
t
HA  
AW  
t
SA  
t
PWE  
WH/WL  
t
t
HD  
SD  
DATA IN  
DATA VALID  
t
t
LZWE  
HZWE  
HIGH IMPEDANCE  
DATA OUT  
DATA UNDEFINED  
82108  
Notes:  
7. WH/WL is HIGH for read cycle.  
8. Device is continuously selected, E3/E2/E1/E0 = VIL and G = VIL  
.
9. Address valid prior to or coincident with E3/E2/E1/E0 transition LOW.  
Document #: 38-05008 Rev. **  
Page 5 of 8  
CYM8210BPM  
Switching Waveforms (continued)  
Write Cycle No. 2 (E3/E2/E1/E0 Controlled)[6, 10]  
t
WC  
ADDRESS  
t
SA  
t
SCS  
E3/E2/E1/E0  
t
t
HA  
AW  
t
PWE  
WH/WL  
DATA IN  
t
t
HD  
SD  
DATA VALID  
t
HZWE  
HIGH IMPEDANCE  
DATA OUT  
DATA UNDEFINED  
82109  
Note:  
10. If E3/E2/E1/E0 goes HIGH simultaneously with WH/WL HIGH, the output remains in a high-impedance state.  
Document #: 38-05008 Rev. **  
Page 6 of 8  
CYM8210BPM  
Ordering Information  
Speed  
Package  
Name  
Operating  
(ns)  
Ordering Code  
Package Type  
80-Pin Plastic SIMM Module  
Range  
70  
CYM8210BPM-70C  
PM49  
Commercial  
Package Diagrams  
80-Pin Plastic SIMM Module PM49  
Document #: 38-05008 Rev. **  
Page 7 of 8  
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
CYM8210BPM  
Document Title: CYM8210BPM 2M X 16 SRAM Module Datasheet  
Document Number: 38-05008  
REV.  
ECN NO.  
Issue Date  
Orig. of Change  
Description of Change  
New Data Sheet  
**  
106011  
05/07/01  
MEG  
Document #: 38-05008 Rev. **  
Page 8 of 8  
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