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CYM52KQT36AV25

型号：

CYM52KQT36AV25

描述：

内存\n[ Memory ]

品牌：

ETC[ ETC ]

页数：

25 页

PDF大小：

247 K

下载PDF手册
CYM52KQT36AV25  
ADVANCE INFORMATION  
TM  
18-Mb Pipelined MCM with QDR Architecture  
Features  
Functional Description  
• Separate Independent Read and Write Data Ports  
— Supports concurrent transactions  
• 167 MHz Clock for High Bandwidth  
— 2.5 ns Clock-to-Valid access time  
• Double Data Rate (DDR) interfaces on both Read &  
Write Ports (data transferred at 333 MHz) @167 MHz  
• Two input clocks (K and K) for precise DDR timing  
— SRAM uses rising edges only  
• Twooutputclocks(CandC)accountforclockskewand  
flight time mismatches  
• Single multiplexed address input bus latches address  
inputs for both READ and WRITE ports  
• Separate Port Selects for depth expansion  
• Synchronous internally self-timed writes  
• 2.5V core power supply with HSTL Inputs and Outputs  
The CYM52KQT36AV25 is a 2.5V 18M Synchronous Pipe-  
lined SRAM equipped with QDR architecture. QDR architec-  
ture consists of two separate ports to access the memory ar-  
ray. The Read port has dedicated Data Outputs to support  
Read operations and the Write Port has dedicated Data inputs  
to support Write operations. Access to each port is accom-  
plished through a common address bus. The Read address is  
latched on the rising edge of the K clock and the Write address  
is latched on the rising edge of K clock. QDR has separate  
data inputs and data outputs to completely eliminate the need  
to “turn-around” the data bus required with common I/O devic-  
es. Accesses to the CYM52KQT36AV25 Read and Write ports  
are completely independent of one another. All accesses are  
initiated synchronously on the rising edge of the positive input  
clock (K). In order to maximize data throughput, both Read and  
Write ports are equipped with Double Data Rate (DDR) inter-  
faces. Therefore, data can be transferred into the device on  
every rising edge of both input clocks (K and K) AND out of the  
device on every rising edge of the output clock (C and C) there-  
by maximizing performance while simplifying system design.  
• 13x15 mm, 1.0-mm pitch fBGA package, 165 ball (11x15  
matrix)  
• Variable drive HSTL output buffers  
• Expanded HSTL output voltage (1.4V–1.9V)  
• JTAG Interface  
Depth expansion is accomplished with a Port Select input for  
each port. Each Port Select allows each port to operate inde-  
pendently.  
• Variable Impedance HSTL  
All synchronous inputs pass through input registers controlled  
by the K or K input clocks. All data outputs pass through output  
registers controlled by the C or C input clocks. Writes are con-  
ducted with on-chip synchronous self-timed write circuitry.  
Logic Block Diagram  
D[8:0]  
BWS0  
BWS1  
D[35:0]  
18  
D[17:9]  
D[17:0]  
A
A
(17:0)  
(17:0)  
18  
Q[8:0]  
Q[17:0]  
K
K
C
C
Q[17:9]  
K
K
C
C
RPS  
TDI  
TDO  
TMS  
TCLK  
TDI  
Q[35:0]  
36  
Vref  
WPS  
TMS  
D[25:18]  
D[35:26]  
TDI  
TDO  
(17:0) TMS  
D[17:0]  
A
TDO  
TCLK  
TCLK  
Q[17:0]  
K
K
C
C
Q[25:18]  
Q[35:26]  
18  
RPS  
RPS  
BWS2  
BWS3  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-05041 Rev. **  
Revised August 15, 2001  
CYM52KQT36AV25  
ADVANCE INFORMATION  
Selection Guide  
CYM52KQT36AV25  
-167  
CYM52KQT36AV25  
CYM52KQT36AV25  
-100  
-133  
Maximum Operating Frequency (MHz)  
Maximum Operating Current (mA)  
167  
133  
100  
TBD  
TBD  
TBD  
Pin Configuration - CYM52KQT36AV25 (TOP VIEW)  
1
2
3
4
5
6
7
8
9
10  
11  
A
B
C
D
E
F
NC  
VSS  
Q18  
Q28  
D20  
D29  
Q21  
D22  
VREF  
Q31  
D32  
Q24  
Q34  
D26  
D35  
TCK  
NC  
WPS  
A
BWS2  
BWS3  
A
K
BWS1  
BWS0  
A
RPS  
NC  
VSS  
Q17  
Q7  
NC  
Q8  
D8  
D7  
Q6  
Q5  
D5  
ZQ  
D4  
Q3  
Q2  
D2  
D1  
Q0  
TDI  
Q27  
D27  
D28  
Q29  
Q30  
D30  
NC  
D18  
D19  
Q19  
Q20  
D21  
Q22  
VDDQ  
D23  
Q23  
D24  
D25  
Q25  
Q26  
A
K
A
D17  
D16  
Q16  
Q15  
D14  
Q13  
VDDQ  
D12  
Q12  
D11  
D10  
Q10  
Q9  
VSS  
VSS  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VSS  
VSS  
A
A
VSS  
VSS  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VSS  
VSS  
A
VSS  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
A
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
A
VSS  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
A
D15  
D6  
Q14  
D13  
VREF  
Q4  
G
H
J
D31  
Q32  
Q33  
D33  
D34  
Q35  
TDO  
K
L
D3  
Q11  
Q1  
M
N
P
R
D9  
A
C
A
D0  
A
A
C
A
A
A
TMS  
Document #: 38-05041 Rev. **  
Page 2 of 25  
CYM52KQT36AV25  
ADVANCE INFORMATION  
Pin Definitions  
Name  
I/O  
Description  
D[35:0]  
Input-  
Synchronous  
Data input signals, sampled on the rising edge of K and K clocks during valid write  
operations.  
WPS  
Input-  
Synchronous  
Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted  
active, a write operation is initiated. Deasserting will deselect the Write port. Deselecting  
the Write port will cause D[35:0] to be ignored.  
BWS0, BWS1,  
BWS2, BWS3  
Input-  
Synchronous  
Byte Write Select 0, 1, 2 and 3 — active LOW. Sampled on the rising edge of the K and  
K clocks during write operations. Used to select which byte is written into the device  
during the current portion of the write operations. Bytes not written remain unaltered.  
BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls  
D[35:27]. BWS0, BWS1, BWS2 and BWS3 are sampled on the same edge as D[35:0]  
.
Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored  
and not written into the device.  
A(17:0)  
Input-  
Synchronous  
Address inputs. Sampled on the rising edge of both the K and K clocks during active  
read and write operations. These address inputs are multiplexed for both Read and  
Write operations. The Read address is latched on the rising edge of the positive input  
clock (K) and the Write address is latched on the rising edge of the negative input clock  
(K). Internally, the device is organized 256K x 72. Therefore, only 18 address inputs are  
needed to access the entire memory array.These inputs are ignored when the appro-  
priate port is deselected. Therefore, on the rising edge of the positive input clock (K),  
these inputs are ignored if the Read port is deselected. These inputs are ignored on the  
rising edge of the negative input clock (K) when the Write port is deselected.  
Q[35:0]  
RPS  
Outputs  
Synchronous  
Data Output signals. These pins drive out the requested data during a Read operation.  
Valid data is driven out on the rising edge of both the C and C clocks during Read  
operations. When the Read port is deslected, Q[35:0] are automatically three-stated.  
Input-  
Synchronous  
Read Port Select, active LOW. Sampled on the rising edge of positive input clock (K).  
When active, a Read operation is initiated. Deasserting will cause the Read port to be  
deselected. When deselected, the pending access is allowed to complete and the output  
drivers are automatically three-stated following the next rising edge of the C clock. The  
device is organized internally as 256K x 72. Each read access consists of a burst of two  
sequential 36-bit transfers.  
C
C
K
Input-Clock  
Input-Clock  
Input-Clock  
Positive Output Clock, input. C is used in conjunction with C to clock out the Read data  
from the device. C and C can be used together to deskew the flight times of various  
devices on the board back to the controller. See application example for further details.  
Negative Output Clock, input. C is used in conjunction with C to clock out the Read data  
from the device. C and C can be used together to deskew the flight times of various  
devices on the board back to the controller. See application example for further details.  
Positive Input Clock, input. The rising edge of K is used to capture synchronous inputs  
to the device and to drive out data through Q[35:0] when in single clock mode. All ac-  
cesses are initiated on the rising edge of K.  
K
Input-Clock  
Input  
Negative Input Clock Input. K is used to capture synchronous inputs being presented  
to the device and to drive out data through Q[35:0] when in single clock mode.  
ZQ  
Output Impedance Matching Input. This input is used to tune the device outputs to the  
system data bus impedance. Q[35:0] output impedance are set to 0.2 x RQ, where RQ  
is a resistor connected between ZQ and ground. Alternately, this pin can be connected  
directly to VDD, which enables the minimum impedance mode. This pin cannot be con-  
nected directly to GND or left unconnected.  
TDO  
TCK  
TDI  
Output  
Input  
Input  
Input  
TDO for JTAG.  
TCK pin for JTAG.  
TDI pin for JTAG.  
TMS  
NC  
TMS pin for JTAG.  
Not Connect Pins. These are not connected to the die.  
Document #: 38-05041 Rev. **  
Page 3 of 25  
CYM52KQT36AV25  
ADVANCE INFORMATION  
Pin Definitions (continued)  
VREF  
Input-  
Reference  
Reference Voltage Input. Static input used to set the reference level for HSTL inputs and  
Outputs as well as A/C measurement points.  
VDD  
Power Supply  
Power supply inputs to the core of the device. Should be connected to 2.5V power  
supply.  
VSS  
Ground  
Ground for the device. Should be connected to ground of the system.  
VDDQ  
Power Supply  
Power supply inputs for the outputs of the device. Should be connected to 1.5V power  
supply.  
edge of the output clocks (C and C). The CYM52KQT36AV25  
will deliver the most recent data for the address location being  
accessed. This includes forwarding data when a Read and  
Write transactions to the same address location are initiated  
Introduction  
Functional Overview  
The CYM52KQT36AV25 is a synchronous pipelined Burst  
SRAM equipped with both a Read Port and a Write Port. The  
Read port is dedicated to Read operations and the Write Port  
is dedicated to Write operations. Data flows into the SRAM  
through the Write port and out through the Read Port. The  
CYM52KQT36AV25 multiplexes the address inputs in order to  
minimize the number of address pins required. The  
CYM52KQT36AV25 latches the Read address on the rising  
edge of the positive input clock (K) and latches the Write ad-  
dress on the rising edge of the negative input clock (K). By  
on the same clock rise.  
When the read port is deselected, the CYM52KQT36AV25 will  
first complete the pending read transactions. Synchronous in-  
ternal circuitry will automatically three-state the outputs follow-  
ing the next rising edge of the positive output clock (C). This  
will allow for a seamless transition between devices without the  
insertion of wait states.  
The CYM52KQT36AV25 is equipped with internal logic that  
synchronously controls the state of the output drivers. The log-  
ic inside the device determines when the output drivers need  
to be active or inactive. This advanced logic eliminates the  
need for an asynchronous output enable since the device will  
automatically enable/disable the output drivers during the  
proper cycles. The CYM52KQT36AV25 will automatically  
power-up in a deselcted state with the outputs in a three state  
condition.  
having  
separate  
Read  
and  
Write  
ports,  
the  
CYM52KQT36AV25 completely eliminates the need to “turn  
around” the data bus and avoids any possible data contention,  
thereby simplifying system design.  
Accesses for both ports are initiated by the positive input clock  
(K). All synchronous input timing is referenced from the rising  
edge of the input clocks (K and K) and all output timing is  
referenced to the output clocks (C and C) or K and K when in  
single clock mode.  
Write Operations  
Write operations are initiated by asserting WPS active at the  
rising edge of the positive input clock (K). On the same clock  
rise (K) the data presented to D[35:0] is stored into the lower  
36-bit Write Data register provided BWS[3:0] are all asserted  
active. On the subsequent rising edge of the negative input  
clock (K), the information presented to A[17:0] is latched and  
stored in the Write Address Register and the information pre-  
sented to D[35:0] is also stored into the upper 36-bit Write Data  
Register provided BWS[3:0] are all asserted active. The 72 bits  
of data are then written into the memory array at the specified  
location.  
All synchronous data inputs (D[35:0]) pass through input regis-  
ters controlled by the input clocks (K and K). All synchronous  
data outputs (Q[35:0]) pass through output registers controlled  
by the rising edge of the output clocks (C and C)  
All synchronous control inputs (RPS, WPS, BWS0, BWS1,  
BWS2, BWS3) pass through input registers controlled by the  
rising edge of the input clocks (K and K).  
Read Operations  
Read operations are initiated by asserting RPS active at the  
rising edge of the positive input clock (K). The address pre-  
sented to A[17:0] is stored in the Read address register. Be-  
cause the CYM52KQT36AV25 is a 72-bit memory, it will ac-  
cess two 36-bit data words with each read operation. Following  
the next K clock rise the data is available to be latched out of  
the device, triggered by the C clock. On the following C clock  
rise the corresponding lower order word of data is driven onto  
Q[36:0]. On the subsequent rising edge of C the higher order  
data word is driven onto Q[35:0]. The requested data will be  
valid 2.5 ns from the rising edge of the output clock (C or C,  
167 MHz device). With the separate Input and Output ports  
and the internal logic determining when the device should  
drive the data bus, the QDR architecture has eliminated the  
need for an output enable input to control the state of the out-  
put drivers.  
Write accesses can be initiated on every rising edge of the  
positive clock. Doing so will pipeline the data flow such that  
36 bits of data can be transferred into the device on every ris-  
ing edge of the input clocks (K and K).  
Byte  
Write  
operations  
are  
supported  
by  
the  
CYM52KQT36AV25. A write operation is initiated by selecting  
the write port using WPS. The bytes that are written are deter-  
mined by BWS0, BWS1, BWS2 and BWS3 which are sampled  
with each set of 36-bit data words. Asserting the appropriate  
Byte Write Select input during the data portion of a write will  
allow the data being presented to be latched and written into  
the device. Deasserting the Byte Write Select input during the  
data portion of a write will allow the data stored in the device  
for that byte to remain unaltered. This feature can be used to  
simplify READ/MODIFY/WRITE operations to a Byte Write op-  
eration.  
Read accesses can be initiated on every rising edge of the  
positive input clock (K). Doing so will pipeline the data flow  
such that data is transferred out of the device on every rising  
When deselected, the write port will ignore all inputs.  
Document #: 38-05041 Rev. **  
Page 4 of 25  
CYM52KQT36AV25  
ADVANCE INFORMATION  
Single Clock Mode  
operation. Coherency is not maintained for Write operations  
initiated in the cycle after a Read.  
The CYM52KQT36AV25 can be used with a single clock  
mode. In this mode the device will recognize only the pair of  
input clocks (K and K) that control both the input and output  
registers. This operation is identical to the operation if the de-  
vice had zero skew between the K/K and C/C clocks. All timing  
parameters remain the same in this mode. To use this mode  
of operation, the user must tie C and C to VDD. During pow-  
er-up, the device will sense the single clock input and operate  
in either single clock or double clock mode. The clock mode  
should not be changed during device operation.  
Depth Expansion  
The CYM52KQT36AV25 has a Port Select input for  
each port. This allows for easy depth expansion. Both  
Port Selects are sampled on the rising edge of the pos-  
itive input clock only (K). Each port select input can de-  
select the specified port. Deselecting a port will not af-  
fect the other port. All pending transactions (Read and  
Write) will be completed prior to the device being dese-  
lected.  
Concurrent Transactions  
The Read and Write ports on the CYM52KQT36AV25 operate  
completely independently of one another. Since each port  
latches the address inputs on different clock edges, the user  
can Read or Write to any location, regardless of the transac-  
tion on the other port. Should the Read and Write ports access  
the same location on the rising edge of the positive input clock,  
the information presented to D[35:0] will be forwarded to Q[35:0]  
such that no latency is required to access valid data. Coher-  
ency is conducted on cycle boundaries. Once the second word  
of data is latched into the device, the write operation is consid-  
ered completed. At this point, any access to that address loca-  
tion will receive that data until altered by a subsequent Write  
Programmable Impedance  
An external resistor, RQ, must be connected between  
the ZQ pin on the SRAM and VSS to allow the SRAM to  
adjust its output driver impedance. The value of RQ  
must be 5X the value of the intended line impedance  
driven by the SRAM. The allowable range of RQ to guar-  
antee impedance matching with a tolerance of ±10% is  
between 175Ω and 350Ω, with VDDQ = 1.5V. The output  
impedance is adjusted every 1024 cycles to adjust for  
drifts in supply voltage and temperature.  
[
]
Truth Table 1,2  
Address  
used  
Operation  
RPS WPS  
K
Comments  
Deselected  
-
H
H
L-H Read Port is deselected. Outputs three-state following next rising edge of  
negative input clock (K) if in single clock mode, or C if using C and C as  
the output clocks.  
Write Port is deselected. All Write Port inputs are ignored during this clock  
rise and the subsequent rising edge of the negative input clock (K).  
Begin Read  
Begin Write  
External  
L
H
L
L-H Read operation initiated. Addresses are stored in the Read Address Reg-  
ister. Following the next K clock rise the first (lower order) 36-bit word will  
be available to be driven out onto Q[35:0] gated by the rising edge of the  
output clock C. On the subsequent rising edge of the negative output clock  
(C) the second (higher order) 36-bit word is driven out onto Q[35:0]  
.
External  
on next  
rising  
H
L-H Write operation initiated. The information presented to D[35:0] is stored in  
the Write Data Register. On the subsequent rising edge of the negative  
input clock (K) the device will latch the addresses presented to A[17:0] and  
the data presented to D[35:0]]. The entire 72 bits of information will then  
be written into the memory array. See Write Description table for byte write  
information,  
edge of K  
Note:  
1. X = Don’t Care, H = Logic HIGH, L = Logic LOW.  
2. Device will power-up deselected and the outputs in a three-state condition.  
3. BWS0 and BWS1 asserted active LOW during all cycles. For byte write operations, see Write Description Table.  
4. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.  
5. It is recommended that K = K# and C = C# when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging  
symmetrically.  
Document #: 38-05041 Rev. **  
Page 5 of 25  
CYM52KQT36AV25  
ADVANCE INFORMATION  
Write Descriptions [6]  
Operation  
K
K
BWS0 BWS1 BWS2 BWS3  
Comments  
Write Initiated  
L-H  
-
L
L
L
L
All the four bytes (D[35:0]) are written into the lower  
order 36-bit write buffer device during this portion of  
a write operation.  
Write Complet-  
ed - Write initi-  
ated on previ-  
ous K clock rise  
-
L-H  
-
L
L
L
L
All the four bytes (D[35:0]) are written into the higher  
order 36-bit write buffer device during this portion of  
a write operation. The contents of the entire 72-bit  
write buffer are written into the memory array.  
Write Initiated  
L-H  
-
L
L
H
H
H
H
H
H
Only Byte 0 (D[8:0]) is written into the lower order  
36-bit write buffer of the device during this portion of  
a write operation. All the remaining data bits (D[35:9]  
)
remain unaltered.  
Write Complet-  
ed - Write initi-  
ated on previ-  
ous K clock rise  
L-H  
Only Byte 0 (D[8:0]) is written into the higher order  
36-bit write buffer of the device during this portion of  
a write operation. All the remaining data bits(D[35:9]  
)
remain unaltered. Byte 0 is then written into the  
memory array.  
Write Initiated  
L-H  
-
-
H
H
L
L
H
H
H
H
Only Byte 1 (D[17:9]) is written into the lower order  
36-bit write buffer of the device during this portion of  
a write operation. All the remaining data bits remain  
unaltered  
Write Complet-  
ed - Write initi-  
ated on previ-  
ous K clock rise  
L-H  
Only Byte 1 (D[17:9]) is written into the higher order  
36-bit write buffer of the device during this portion of  
a write operation. All the remaining data bits remain  
unaltered. Byte 1 is then written into the memory  
array.  
Write Initiated  
L-H  
-
-
H
L
H
H
L
L
H
H
Only Byte 2 (D[26:18]) is written into the lower order  
36-bit write buffer of the device during this portion of  
a write operation. All the remaining data bits remain  
unaltered.  
Write Complet-  
ed - Write initi-  
ated on previ-  
ous K clock rise  
L-H  
Only Byte 2 (D[26:18]) is written into the higher order  
36-bit write buffer of the device during this portion of  
a write operation. All the remaining data bits remain  
unaltered. Byte 2 is then written into the memory  
array.  
Write Initiated  
L-H  
-
-
H
H
H
H
H
H
L
L
Only Byte 1 (D[35:27]) is written into the lower order  
36-bit write buffer of the device during this portion of  
a write operation. All the remaining data bits remain  
unaltered  
Write Complet-  
ed - Write initi-  
ated on previ-  
ous K clock rise  
L-H  
Only Byte 1 (D[35:27]) is written into the higher order  
36-bit write buffer of the device during this portion of  
a write operation. All the remaining data bits remain  
unaltered. Byte 3 is then written into the memory  
array.  
Write - NO-OP  
L-H  
-
-
H
H
H
H
H
H
H
H
No data is written into the device during this portion  
of a write operation.  
Write - NO-OP  
L-H  
No data is written into the device during this portion  
of a write operation.  
Note:  
6. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS0, BWS1, BWS2 and BWS3 can be altered on different portions  
of a write cycle, as long as the set-up and hold requirements are achieved.  
Document #: 38-05041 Rev. **  
Page 6 of 25  
CYM52KQT36AV25  
ADVANCE INFORMATION  
instruction register. Data is serially loaded into the TDI pin on  
the rising edge of TCK. Data is output on the TDO pin on the  
falling edge of TCK.  
IEEE 1149.1 SERIAL BOUNDARY SCAN  
(JTAG—fBGA only)  
The CYM52KQT36AV25 incorporates a serial boundary scan  
test access port (TAP). This port operates in accordance with  
IEEE Standard 1149.1-1900, but does not have the set of func-  
tions required for full 1149.1 compliance. These functions from  
the IEEE specification are excluded because their inclusion  
places an added delay in the critical speed path of the SRAM.  
Note that the TAP controller functions in a manner that does  
not conflict with the operation of other devices using 1149.1  
fully compliant TAPs. The TAP operates using JEDEC stan-  
dard 2.5V I/O logic levels.  
Instruction Register  
Three-bit instructions can be serially loaded into the instruc-  
tion register. This register is loaded when it is placed between  
the TDI and TDO pins as shown in the TAP Controller Block  
Diagram. Upon power-up, the instruction register is loaded  
with the IDCODE instruction. It is also loaded with the IDCODE  
instruction if the controller is placed in a reset state as de-  
scribed in the previous section.  
When the TAP controller is in the Capture-IR state, the two  
least significant bits are loaded with a binary “01” pattern to  
allow for fault isolation of the board level serial test data path.  
Disabling the JTAP Feature  
It is possible to operate the SRAM without using the JTAG  
feature. To disable the TAP controller, TCK must be tied LOW  
(VSS) to prevent clocking of the device. TDI and TMS are inter-  
nally pulled up and may be unconnected. They may alternately  
be connected to VDD through a pull-up resistor. TDO should  
be left unconnected. Upon power-up, the device will come up  
in a reset state which will not interfere with the operation of the  
device.  
Bypass Register  
To save time when serially shifting data through registers, it is  
sometimes advantageous to skip certain chips. The bypass  
register is a single-bit register that can be placed between TDI  
and TDO pins. This allows data to be shifted through the  
SRAM with minimal delay. The bypass register is set LOW  
(VSS) when the BYPASS instruction is executed.  
Test Access Port (TAP) - Test Clock  
Boundary Scan Register  
The test clock is used only with the TAP controller. All inputs  
are captured on the rising edge of TCK. All outputs are driven  
from the falling edge of TCK.  
The boundary scan register is connected to all the input and  
output pins on the SRAM. Several no connect (NC) pins are  
also included in the scan register to reserve pins for higher  
density devices.  
Test Mode Select  
The boundary scan register is loaded with the contents of the  
RAM Input and Output ring when the TAP controller is in the  
Capture-DR state and is then placed between the TDI and  
TDO pins when the controller is moved to the Shift-DR state.  
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-  
tions can be used to capture the contents of the Input and  
Output ring.  
The TMS input is used to give commands to the TAP controller  
and is sampled on the rising edge of TCK. It is allowable to  
leave this pin unconnected if the TAP is not used. The pin is  
pulled up internally, resulting in a logic HIGH level.  
Test Data-In (TDI)  
The TDI pin is used to serially input information into the regis-  
ters and can be connected to the input of any of the registers.  
The register between TDI and TDO is chosen by the instruc-  
tion that is loaded into the TAP instruction register. For infor-  
mation on loading the instruction register, see the TAP Control-  
ler State Diagram. TDI is internally pulled up and can be  
unconnected if the TAP is unused in an application. TDI is con-  
nected to the most significant bit (MSB) on any register.  
The Boundary Scan Order tables show the order in which the  
bits are connected. Each bit corresponds to one of the bumps  
on the SRAM package. The MSB of the register is connected  
to TDI, and the LSB is connected to TDO.  
Identification (ID) Register  
The ID register is loaded with a vendor-specific, 32-bit code  
during the Capture-DR state when the IDCODE command is  
loaded in the instruction register. The IDCODE is hardwired  
into the SRAM and can be shifted out when the TAP controller  
is in the Shift-DR state. The ID register has a vendor code and  
other information described in the Identification Register Defi-  
nitions table.  
Test Data Out (TDO)  
The TDO output pin is used to serially clock data-out from the  
registers. The output is active depending upon the current  
state of the TAP state machine (See TAP Controller State Di-  
agram). The output changes on the falling edge of TCK. TDO  
is connected to the least significant bit (LSB) of any register.  
TAP Instruction Set  
Performing a TAP Reset  
Eight different instructions are possible with the three-bit in-  
struction register. All combinations are listed in the Instruction  
Codes table. Three of these instructions are listed as RE-  
SERVED and should not be used. The other five instructions  
are described in detail below.  
A RESET is performed by forcing TMS HIGH (VDD) for five  
rising edges of TCK. This RESET does not affect the operation  
of the SRAM and may be performed while the SRAM is oper-  
ating. At power-up, the TAP is reset internally to ensure that  
TDO comes up in a high-Z state.  
The TAP controller used in this SRAM is not fully compliant to  
the 1149.1 convention because some of the mandatory 1149.1  
instructions are not fully implemented. The TAP controller can-  
not be used to load address, data or control signals into the  
SRAM and cannot preload the Input or output buffers. The  
SRAM does not implement the 1149.1 commands EXTEST or  
TAP Registers  
Registers are connected between the TDI and TDO pins and  
allow data to be scanned into and out of the SRAM test circuit-  
ry. Only one register can be selected at a time through the  
Document #: 38-05041 Rev. **  
Page 7 of 25  
CYM52KQT36AV25  
ADVANCE INFORMATION  
INTEST or the PRELOAD portion of SAMPLE / PRELOAD;  
rather it performs a capture of the Inputs and Output ring when  
these instructions are executed.  
state, a snapshot of data on the inputs and output pins is cap-  
tured in the boundary scan register.  
The user must be aware that the TAP controller clock can only  
operate at a frequency up to 10 MHz, while the SRAM clock  
operates more than an order of magnitude faster. Because  
there is a large difference in the clock frequencies, it is possible  
that during the Capture-DR state, an input or output will under-  
go a transition. The TAP may then try to capture a signal while  
in transition (metastable state). This will not harm the device,  
but there is no guarantee as to the value that will be captured.  
Repeatable results may not be possible.  
Instructions are loaded into the TAP controller during the  
Shift-IR state when the instruction register is placed between  
TDI and TDO. During this state, instructions are shifted  
through the instruction register through the TDI and TDO pins.  
To execute the instruction once it is shifted in, the TAP control-  
ler needs to be moved into the Update-IR state.  
EXTEST  
EXTEST is a mandatory 1149.1 instruction which is to be ex-  
ecuted whenever the instruction register is loaded with all 0s.  
EXTEST is not implemented in the CYM52KQT36AV25 TAP  
controller, and therefore this device is not compliant to the  
1149.1 standard.  
To guarantee that the boundary scan register will capture the  
correct value of a signal, the SRAM signal must be stabilized  
long enough to meet the TAP controller’s capture setup plus  
hold times (tCS and tCH). The SRAM clock input might not be  
captured correctly if there is no way in a design to stop (or  
slow) the clock during a SAMPLE / PRELOAD instruction. If  
this is an issue, it is still possible to capture all other signals  
and simply ignore the value of the K, K, C and C captured in  
the boundary scan register.  
The TAP controller does recognize an all-0 instruction. When  
an EXTEST instruction is loaded into the instruction register,  
the SRAM responds as if a SAMPLE / PRELOAD instruction  
has been loaded.  
Once the data is captured, it is possible to shift out the data by  
putting the TAP into the Shift-DR state. This places the bound-  
ary scan register between the TDI and TDO pins.  
IDCODE  
The IDCODE instruction causes a vendor-specific, 32-bit code  
to be loaded into the instruction register. It also places the  
instruction register between the TDI and TDO pins and allows  
the IDCODE to be shifted out of the device when the TAP con-  
troller enters the Shift-DR state. The IDCODE instruction is  
loaded into the instruction register upon power-up or whenever  
the TAP controller is given a test logic reset state.  
Note that since the PRELOAD part of the command is not  
implemented, putting the TAP into the Update-DR state while  
performing a SAMPLE / PRELOAD instruction will have the  
same effect as the Pause-DR command.  
Bypass  
When the BYPASS instruction is loaded in the instruction reg-  
ister and the TAP is placed in a Shift-DR state, the bypass  
register is placed between the TDI and TDO pins. The advan-  
tage of the BYPASS instruction is that it shortens the boundary  
scan path when multiple devices are connected together on a  
board.  
SAMPLE Z  
The SAMPLE Z instruction causes the boundary scan register  
to be connected between the TDI and TDO pins when the TAP  
controller is in a Shift-DR state.  
SAMPLE / PRELOAD  
SAMPLE / PRELOAD is a 1149.1 mandatory instruction. The  
PRELOAD portion of this instruction is not implemented, so  
the CYM52KQT36AV25 TAP controller is not fully 1149.1 com-  
pliant.  
Reserved  
These instructions are not implemented but are reserved for  
future use. Do not use these instructions.  
When the SAMPLE / PRELOAD instructions is loaded into the  
instruction register and the TAP controller is in the Capture-DR  
Document #: 38-05041 Rev. **  
Page 8 of 25  
CYM52KQT36AV25  
ADVANCE INFORMATION  
TAP Controller State Diagram  
TEST-LOGIC  
1
RESET  
0
1
1
1
TEST-LOGIC/  
IDLE  
SELECT  
DR-SCAN  
SELECT  
IR-SCAN  
0
0
0
1
1
CAPTURE-DR  
CAPTURE-DR  
0
0
SHIFT-DR  
0
1
SHIFT-IR  
0
1
1
EXIT1-DR  
0
1
EXIT1-IR  
0
0
0
PAUSE-DR  
1
PAUSE-IR  
1
0
0
EXIT2-DR  
1
EXIT2-IR  
1
UPDATE-DR  
UPDATE-IR  
1
1
0
0
Note: The 0/1 next to each state represents the value at TMS at the rising edge of TCK.  
Document #: 38-05041 Rev. **  
Page 9 of 25  
CYM52KQT36AV25  
ADVANCE INFORMATION  
TAP Controller Block Diagram  
0
Bypass Register  
Selection  
Circuitry  
Selection  
Circuitry  
TDO  
2
1
0
TDI  
Instruction Register  
29  
30  
.
.
2
1
0
0
63  
Identification Register  
.
1
137  
.
.
.
2
Boundary Scan Register  
TCK  
TMS  
TAP Controller  
TAP Electrical Characteristics Over the Operating Range[7, 8]  
Parameter  
VOH1  
VOH2  
VOL1  
VOL2  
VIH  
Description  
Output HIGH Voltage  
Output HIGH Voltage  
Output LOW Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Test Conditions  
IOH = −2.0 mA  
Min.  
1.7  
Max.  
Unit  
V
IOH = −100 µA  
IOL = 2.0 mA  
IOL = 100 µA  
2.1  
V
0.7  
0.2  
V
V
1.7  
-0.3  
−5  
VDD+0.3  
0.7  
V
VIL  
Input LOW Voltage  
V
IX  
Input and Output Load Current  
GND ≤ VI ≤ VDDQ  
5
µA  
Notes:  
7. All Voltage referenced to Ground  
8. Overshoot: VIH(AC)<VDD+1.5V for t<tTCYC/2, Undershoot:VIL(AC)<0.5V for t<tTCYC/2, Power-up: VIH<2.6V and VDD<2.4V and VDDQ<1.4V for t<200ms.  
9. These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table  
Document #: 38-05041 Rev. **  
Page 10 of 25  
CYM52KQT36AV25  
ADVANCE INFORMATION  
TAP AC Switching Characteristics Over the Operating Range[10, 11]  
Param  
tTCYC  
tTF  
Description  
Min.  
Max.  
Unit  
ns  
TCK Clock Cycle Time  
TCK Clock Frequency  
TCK Clock HIGH  
100  
10  
MHz  
ns  
tTH  
40  
40  
tTL  
TCK Clock LOW  
ns  
Set-up Times  
tTMSS  
tTDIS  
tCS  
TMS Set-up to TCK Clock Rise  
10  
10  
10  
ns  
ns  
ns  
TDI Set-up to TCK Clock Rise  
Capture Set-up to TCK Rise  
Hold Times  
tTMSH  
tTDIH  
tCH  
TMS Hold after TCK Clock Rise  
10  
10  
10  
ns  
ns  
ns  
TDI Hold after Clock Rise  
Capture Hold after Clock Rise  
Output Times  
tTDOV  
TCK Clock LOW to TDO Valid  
TCK Clock LOW to TDO Invalid  
20  
ns  
ns  
tTDOX  
0
Notes:  
10. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.  
11. Test conditions are specified using the load in TAP AC test conditions. tr/tf = 1 ns.  
Document #: 38-05041 Rev. **  
Page 11 of 25  
CYM52KQT36AV25  
ADVANCE INFORMATION  
TAP Timing and Test Conditions[11]  
1.25V  
50Ω  
ALL INPUT PULSES  
TDO  
2.5V  
Z =50Ω  
0
1.25V  
C =20pF  
L
0V  
GND  
(a)  
tTL  
tTH  
Test Clock  
TCK  
tTCYC  
tTMSS  
tTMSH  
Test Mode Select  
TMS  
tTDIS  
tTDIH  
Test Data-In  
TDI  
Test Data-Out  
TDO  
tTDOX  
tTDOV  
Document #: 38-05041 Rev. **  
Page 12 of 25  
CYM52KQT36AV25  
ADVANCE INFORMATION  
Identification Register Definitions  
Value  
CYM52KQT36AV25  
000  
Instruction Field  
Revision Number  
(63:61)  
Description  
Version number.  
Cypress Device ID  
(60:44)  
01011010010010110  
Defines the type of SRAM.  
Cypress JEDEC ID  
(43:33)  
00000110100  
Allows unique identification of  
SRAM vendor.  
ID Register Presence  
(32)  
1
Indicate the presence of an ID  
register.  
Revision Number  
(31:29)  
000  
01011010010010110  
00000110100  
1
Version number.  
Cypress Device ID  
(28:12)  
Defines the type of SRAM.  
Cypress JEDEC ID  
(11:1)  
Allows unique identification of  
SRAM vendor.  
ID Register Presence  
(0)  
Indicate the presence of an ID  
register.  
Scan Register sizes  
Register Name  
Instruction  
Bit Size  
3
Bypass  
1
ID  
64  
138  
Boundary Scan  
Document #: 38-05041 Rev. **  
Page 13 of 25  
CYM52KQT36AV25  
ADVANCE INFORMATION  
Instruction Codes  
Instruction  
Code  
Description  
EXTEST  
000  
Captures the Input/Output ring contents. Places the boundary scan  
register between the TDI and TDO. This instruction is not 1149.1 com-  
pliant. The EXTEST command implemented by the  
CCYM52KQT36AV25 devicewill NOT placethe output buffersinto  
a High-Z condition. If the output buffers need to be HIGH-Z con-  
dition, this can be accomplished by deselcting the Read port.  
IDCODE  
001  
010  
Loads the ID register with the vendor ID code and places the register  
between TDI and TDO. This operation does not affect SRAM opera-  
tion.  
SAMPLE Z  
CapturestheInput/Outputcontents. Placestheboundaryscanregister  
between TDI and TDO. The SAMPLEZ command implemented by  
the CCYM52KQT36AV25 device will place the output buffers into  
a High-Z condition.  
RESERVED  
011  
100  
Do Not Use: This instruction is reserved for future use.  
SAMPLE/PRELOAD  
Captures the Input/Output ring contents. Places the boundary scan  
register between TDI and TDO. Does not affect the SRAM operation.  
This instruction does not implement 1149.1 preload function and is  
therefore not 1149.1 compliant.  
RESERVED  
RESERVED  
BYPASS  
101  
110  
111  
Do Not Use: This instruction is reserved for future use.  
Do Not Use: This instruction is reserved for future use.  
Places the bypass register between TDI andTDO. This operation does  
not affect SRAM operation.  
Boundary Scan Order (#1 exits device first)  
Bit # Signal Name Bump ID  
Boundary Scan Order (#1 exits device first) (continued)  
Bit # Signal Name Bump ID  
18 D4  
1
2
3
4
5
6
7
8
9
C
6R  
11J  
C
6P  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
ZQ  
11H  
10J  
11G  
11F  
10E  
11E  
11D  
10C  
11C  
11B  
A
6N  
Q4  
A
7P  
D5  
A
7N  
Q5  
A
7R  
D6  
A
8R  
Q6  
A
8P  
D7  
A
9R  
Q7  
10  
11  
12  
13  
14  
15  
16  
17  
D0  
Q0  
D1  
Q1  
D2  
Q2  
D3  
Q3  
10P  
11P  
11N  
10M  
11M  
11L  
10K  
11K  
D8  
Q8  
Reserved  
12A (Don’t Care)  
GND/72M  
10A  
NC/18M(1)  
9A (Read as 1, 18Mb)  
A
A
A
8B  
7C  
6C  
Document #: 38-05041 Rev. **  
Page 14 of 25  
CYM52KQT36AV25  
ADVANCE INFORMATION  
Boundary Scan Order (#1 exits device first) (continued)  
Boundary Scan Order (#1 exits device first) (continued)  
Bit # Signal Name Bump ID  
69  
Bit #  
35  
Signal Name  
Bump ID  
RPS  
BWS0  
K
8A  
7B  
6B  
6A  
5A  
4A  
5C  
4B  
3A  
2A  
A
5R  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
101  
102  
103  
104  
C
6R  
C
6P  
K
A
6N  
BWS1  
WPS  
A
A
7P  
A
7N  
A
7R  
A
A
8R  
NC/36M(1)  
GND/144M  
Reserved  
D9  
A
8P  
A
9R  
1A (Don’t Care)  
D0  
10P  
11P  
11N  
10M  
11M  
11L  
10K  
11K  
11J  
11H  
10J  
11G  
11F  
10E  
11E  
11D  
10C  
11C  
11B  
3B  
2B  
3C  
3D  
2D  
3E  
3F  
2F  
2G  
3G  
3J  
Q0  
Q9  
D1  
D10  
Q10  
D11  
Q11  
D12  
Q12  
D13  
Q13  
D14  
Q14  
D15  
Q15  
D16  
Q16  
D17  
Q17  
A
Q1  
D2  
Q2  
D3  
Q3  
D4  
ZQ  
Q4  
D5  
3K  
3L  
Q5  
D6  
2L  
Q6  
3M  
3N  
2N  
3P  
3R  
4R  
4P  
5P  
5N  
D7  
Q7  
D8  
Q8  
Reserved  
12A (Don’t Care)  
A
GND/72M  
10A  
A
NC/18M(1)  
9A (Read as 1, 18Mb)  
A
A
8B  
7C  
6C  
8A  
A
A
A
RPS  
Document #: 38-05041 Rev. **  
Page 15 of 25  
CYM52KQT36AV25  
ADVANCE INFORMATION  
Boundary Scan Order (#1 exits device first) (continued)  
Bit # Signal Name Bump ID  
105 Q2  
Boundary Scan Order (#1 exits device first) (continued)  
Bit # Signal Name Bump ID  
123  
11L  
10K  
11K  
11J  
A
7C  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
D3  
124  
125  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
A
6C  
Q3  
RPS  
8A  
D4  
Q4  
10J  
11G  
11F  
10E  
11E  
11D  
10C  
11C  
11B  
ZQ  
11H  
10J  
11G  
11F  
10E  
11E  
11D  
10C  
11C  
11B  
D5  
Q4  
Q5  
D5  
D6  
Q5  
Q6  
D6  
D7  
Q6  
Q7  
D7  
D8  
Q7  
Q8  
D8  
Reserved  
GND/72M  
NC/18M(1)  
A
12A (Don’t Care)  
Q8  
10A  
Reserved  
GND/72M  
NC/18M(1)  
A
12A (Don’t Care)  
9A (Read as 1, 18Mb)  
8B  
10A  
9A (Read as 1, 18Mb)  
8B  
Document #: 38-05041 Rev. **  
Page 16 of 25  
CYM52KQT36AV25  
ADVANCE INFORMATION  
Current into Outputs (LOW) ........................................ 20 mA  
Maximum Ratings  
Static Discharge Voltage .......................................... >2001V  
(per MIL-STD-883, Method 3015)  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Latch-Up Current.................................................... >200 mA  
Storage Temperature .................................–65°C to +150°C  
Ambient Temperature with  
Power Applied.............................................–55°C to +125°C  
Operating Range  
Ambient  
Supply Voltage on VDD Relative to GND ....... –0.5V to +3.6V  
Range Temperature[13]  
VDD  
VDDQ  
DC Voltage Applied to Outputs  
in High Z State[12] ............................... –0.5V to VDDQ + 0.5V  
Com’l  
0°C to +70°C  
2.5V±100mV  
1.4V to 1.9V  
DC Input Voltage[12]............................ –0.5V to VDDQ + 0.5V  
Electrical Characteristics Over the Operating Range  
Parameter  
VDD  
VDDQ  
VOH  
VOL  
Description  
Test Conditions  
Min.  
Max.  
Unit  
V
Power Supply Voltage  
I/O Supply Voltage  
Output HIGH Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage[12]  
Input Load Current  
2.4  
1.4  
2.6  
1.9  
V
IOH = −2.0 mA, nominal impedance  
VDDQ/2 + 0.3  
VDDQ  
V
IOL = 2.0 mA, nominal impedance  
VSS  
VREF + 0.1  
–0.3  
VDDQ/2 –0.3  
VDDQ+0.3  
VREF–0.1  
5
V
VIH  
V
VIL  
V
IX  
GND ≤ VI ≤ VDDQ  
−5  
µA  
µA  
IOZ  
Output Leakage  
Current  
GND ≤ VI ≤ VDDQ, Output Disabled  
−5  
5
VREF  
IDD  
Input Reference Volt-  
age  
Typical value = 0.75V  
0.68  
0.9  
V
VDD Operating Supply VDD = Max., IOUT = 0 mA, 6.0-ns cycle, 167 MHz  
800  
600  
500  
100  
80  
mA  
mA  
mA  
mA  
mA  
mA  
f = fMAX = 1/tCYC  
7.5-ns cycle, 133 MHz  
10-ns cycle, 100 MHz  
ISB1  
Automatic  
Power-Down  
Current  
Max. VDD, Both Ports De- 6.0-ns cycle, 167 MHz  
selected, VIN ≥ VIH or VIN  
≤ VIL f = fMAX = 1/tCYC, In-  
puts Static  
7.5-ns cycle, 133 MHz  
10-ns cycle, 100 MHz  
60  
Note:  
12. Minimum voltage equals –2.0V for pulse duration less than 20 ns.  
13. A is the “instant on” case temperature.  
T
Document #: 38-05041 Rev. **  
Page 17 of 25  
CYM52KQT36AV25  
ADVANCE INFORMATION  
Switching Characteristics Over the Operating Range[14,15,16]  
-167  
-133  
-100  
Parameter  
tCYC  
Description  
K Clock and C Clock Cycle Time  
Min. Max. Min. Max. Min. Max. Unit  
6.0  
2.4  
2.4  
2.7  
7.5  
3.2  
3.2  
3.4  
10.0  
3.5  
3.5  
4.4  
ns  
ns  
ns  
ns  
tKH  
Input Clock (K/K and C/C) HIGH  
Input Clock (K/K and C/C) LOW  
tKL  
tKHKH  
K/K Clock Rise to K/K Clock Rise and C/C to C/C Rise  
(rising edge to rising edge)  
3.3  
4.1  
5.4  
tKHCH  
K/K Clock Rise to C/C Clock Rise (rising edge to rising edge)  
C/C Clock Rise (or K/K in single clock mode) to Data Valid[15]  
0.0  
2.0  
2.5  
0.0  
1.2  
2.5  
3.0  
0.0  
1.2  
3.0  
3.0  
ns  
ns  
ns  
tCO  
tDOH  
Data Output Hold After Output C/C Clock Rise (Active to Active) 1.2  
Set-up Times  
tSA  
tSC  
Address Set-up to Clock (K and K) Rise  
0.7  
0.7  
0.8  
0.8  
1.0  
1.0  
ns  
ns  
Control Set-up to Clock (K and K) Rise (RPS, WPS, BWS0,  
BWS1)  
tSD  
D[17:0] Set-up to Clock (K and K) Rise  
0.7  
0.8  
1.0  
ns  
Hold Times  
tHA  
tHC  
Address Hold after Clock (K and K) Rise  
0.7  
0.7  
0.8  
0.8  
1.0  
1.0  
ns  
ns  
Control Hold after Clock (K and K) Rise (RPS, WPS, BWS0,  
BWS1)  
tHD  
D[17:0] Hold after Clock (K and K) Rise  
0.7  
0.8  
1.0  
ns  
Output Times  
tCHZ  
Clock (C and C) Rise to High-Z (Active to High-Z)[15, 16]  
Clock (C and C) Rise to Low-Z[15, 16]  
2.5  
3.0  
3.0  
ns  
ns  
tCLZ  
1.2  
1.2  
1.2  
Notes:  
14. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V,Vref = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input  
pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads.  
15.  
tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.  
16. At any given voltage and temperature tCHZ is less than tCLZ and, tCHZ less than tCO  
.
Document #: 38-05041 Rev. **  
Page 18 of 25  
CYM52KQT36AV25  
ADVANCE INFORMATION  
Capacitance[17]  
Parameter  
Description  
Input Capacitance  
Test Conditions  
Max.  
TBD  
TBD  
TBD  
Unit  
pF  
CIN  
TA = 25°C, f = 1 MHz,  
VDD = 2.5V.  
VDDQ = 1.5V  
CCLK  
CO  
Clock Input Capacitance  
Output Capacitance  
pF  
pF  
AC Test Loads and Waveforms  
V
/2  
DDQ  
V
/2  
DDQ  
V
REF  
V
V
/2  
REF  
R=50Ω  
DDQ  
OUTPUT  
[14]  
ALL INPUT PULSES  
1.25V  
Z =50Ω  
0
OUTPUT  
Device  
Under  
Test  
R =50Ω  
L
0.75V  
Device  
Under  
0.25V  
5 pF  
V
=0.75V  
REF  
ZQ  
Test  
RQ=  
250Ω  
ZQ  
RQ=  
250Ω  
(a)  
INCLUDING  
JIG AND  
SCOPE  
(b)  
Note:  
17. Tested initially and after any design or process change that may affect these parameters.  
Document #: 38-05041 Rev. **  
Page 19 of 25  
CYM52KQT36AV25  
ADVANCE INFORMATION  
Switching Waveforms  
Read/Deselect Sequence  
tCYC  
tKHKH  
tKL  
tKHKH  
K
tKH  
tKL  
K
tKH  
tSA  
A[17:0]  
A
B
C
tSC  
tHA  
tHC  
RPS  
Q(A+1)  
Q(B+1)  
Q(C+1)  
Q(A)  
Q(B)  
Q(C)  
Data Out  
tCO  
tCLZ  
tCHZ  
tKHCH  
C
C
tDOH  
tCO  
tDOH  
Device originally deselected.  
Activity on the Write Port is unknown.  
= UNDEFINED  
= DON’T CARE  
Document #: 38-05041 Rev. **  
Page 20 of 25  
CYM52KQT36AV25  
ADVANCE INFORMATION  
Switching Waveforms (continued)  
Write/Deselect Sequence  
tCYC  
TKL  
K
tKH  
TKL  
K
tSA  
A[17:0]  
A
B
C
tSC  
tHA  
tHC  
WPS  
tSC  
tHC  
BWSx  
D(B+1)  
D(C)  
D(C+1)  
D(A)  
D(B)  
D(A+1)  
Data In  
tHD  
tSD  
BWSx is both BWS0 and BWS1  
C and C reference to Data Outputs and do not affect Writes. Activity on the  
Read Port is unknown.  
BWSx LOW=Valid, Byte writes allowed, see Byte write table for details.  
= UNDEFINED  
= DON’T CARE  
Document #: 38-05041 Rev. **  
Page 21 of 25  
CYM52KQT36AV25  
ADVANCE INFORMATION  
Switching Waveforms (continued)  
Read/Write/Deselect Sequence  
K
K
A[17:0]  
E
A
B
B
G
C
D
WPS  
RPS  
BWSx  
D[35:0]  
D(A+1)  
D(B+1)  
Q(E)  
D(A)  
D(B)  
D(C)  
D(C+1)  
Q(B)  
D(D)  
D(D+1)  
Q(G)  
Write Data Forwarded  
Q(E+1)  
Q(B+1)  
Q[35:0]  
Q(G+1)  
C
C
Read Port previously deselected.  
Any port select can deselect the port.  
BWS[1:0] both assumed active.  
= UNDEFINED  
= DON’T CARE  
Document #: 38-05041 Rev. **  
Page 22 of 25  
CYM52KQT36AV25  
ADVANCE INFORMATION  
I
Ordering Information  
Speed  
(MHz)  
Package  
Name  
Operating  
Range  
Ordering Code  
Package Type  
167  
CYM52KQT36AV25-16BBC  
CYM52KQT36AV25-13BBC  
CYM52KQT36AV25-10BBC  
BB165B  
BB165B  
BB165B  
13 x 15 mm FBGA  
13 x 15 mm FBGA  
13 x 15 mm FBGA  
Commercial  
Commercial  
Commercial  
133  
100  
Part Numbering Scheme  
CY  
M
Depth  
Architecture Width Revision Voltage  
Speed  
Package Temperature  
C - Commercial  
BB - 165FBGA  
Frequency (100–133 Mhz)  
Core/IO Voltage (CD – 2.5V/1.5HSTL)  
Module Revision (A-First Revision)  
Bus Width (36 Bits)  
Architecture (QT - QDR, Burst of 2)  
Module Depth (1M)  
Module  
Cypress  
Document #: 38-05041 Rev. **  
Page 23 of 25  
CYM52KQT36AV25  
ADVANCE INFORMATION  
Package Diagram  
165-Ball FBGA (13 x 15 x 1.62 mm) BB165B  
51-49026-**  
Document #: 38-05041 Rev. **  
Page 24 of 25  
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
CYM52KQT36AV25  
ADVANCE INFORMATION  
Document Title: CYM52KQT36AV25 18-Mb Pipelined MCM with QDR Architecture  
Document Number: 38-05041  
Issue  
ECN NO. Date  
Orig. of  
Change  
REV.  
Description of Change  
**  
106920  
08/20/01  
MEG  
New Data Sheet  
Document #: 38-05041 Rev. **  
Page 25 of 25  
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