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CYM1846PM-20C

型号:

CYM1846PM-20C

品牌:

ETC[ ETC ]

页数:

8 页

PDF大小:

303 K

46  
CYM1846  
512K x 32 Static RAM Module  
constructed from four 512K x 8 SRAMs in SOJ packages  
mounted on an epoxy laminate substrate. Four chip selects are  
used to independently enable the four bytes. Reading or writ-  
ing can be executed on individual bytes or any combination of  
multiple bytes through proper use of the chip selects.  
Features  
• High-density 16-megabit SRAM module  
• 32-bitstandardfootprintsupportsfrom16Kx32through  
1Mx32  
• High-speed SRAMs  
— Access time of 12 ns  
• Low active power  
The CYM1846 is designed for use with standard 72-pin SIMM  
socket and ZIP footprint. The pinout is compatible with the  
64-pin JEDEC ZIP/SIMM module family (CYM1821,  
CYM1831, CYM1836, and CYM1841) and the 72-pin  
CYM1851. Thus, a single motherboard design can be used to  
accommodate memory depth ranging from 16K words  
(CYM1821) to 1024K words (CYM1851). The standard SIMM  
can be used in Angled SIMM sockets and is available with  
either tin-lead or 10 micro-inches of gold flash on the edge  
contacts.  
— 4.4W (max.) at 12 ns  
• Compatible with CYM1821, CYM1831, CYM1836,  
CYM1841, and CYM1851 JEDEC modules  
• Available in 72-pin ZIP or SIMM/Angled SIMM  
Functional Description  
Presence detect pins (PD0 PD3) are used to identify module  
memory density in applications where modules with alternate  
word depths can be interchanged.  
The CYM1846 is a high-performance 16-megabit static RAM  
module organized as 512K words by 32 bits. This module is  
Logic Block Diagram  
Pin Configuration  
ZIP/SIMM  
Top View  
PD OPEN  
0
PD OPEN  
1
NC  
PD  
1
3
5
7
9
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
PD GND  
NC  
2
2
4
6
8
2
PD  
PD OPEN  
3
3
GND  
PD  
0
PD  
1
I/O  
0
A A  
I/O  
0
18  
OE  
WE  
8
I/O  
1
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
19  
I/O  
9
I/O  
2
I/O  
10  
I/O  
3
I/O  
11  
V
CC  
A
0
A
7
A
1
A
8
A
512Kx8  
SRAM  
2
I/O I/O  
0
7
A
9
I/O  
8
8
8
8
12  
I/O  
4
I/O  
13  
I/O  
5
I/O  
14  
CS  
1
I/O  
6
I/O  
15  
I/O  
7
GND  
WE  
33  
35  
A
512Kx8  
SRAM  
15  
A
I/O I/O  
14  
8
15  
34  
36  
CS  
2
CS  
1
CS  
17  
37  
39  
41  
43  
45  
47  
49  
51  
53  
55  
57  
59  
61  
63  
65  
67  
69  
71  
4
CS  
CS  
2
3
38  
40  
42  
44  
46  
48  
50  
52  
54  
56  
58  
60  
62  
64  
66  
68  
70  
72  
A
A
16  
OE  
GND  
I/O  
512Kx8  
SRAM  
24  
I/O I/O  
I/O  
16  
23  
16  
I/O  
25  
I/O  
17  
I/O  
26  
I/O  
18  
I/O  
27  
I/O  
19  
CS  
3
A
3
A
10  
A
4
A
11  
A
5
512Kx8  
SRAM  
A
I/O I/O  
12  
24  
31  
V
CC  
A
13  
A
6
I/O  
20  
I/O  
28  
I/O  
21  
I/O  
CS  
4
I/O  
29  
22  
I/O  
I/O  
30  
23  
I/O  
31  
GND  
A
18  
NC  
NC  
NC  
Cypress Semiconductor Corporation  
Document #: 38-05276 Rev. **  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Revised March 15, 2002  
CYM1846  
Selection Guide  
1846-12  
12  
1846-15  
15  
1846-20  
20  
1846-25  
25  
1846-35  
35  
Maximum Access Time (ns)  
Maximum Operating Current (mA)  
800  
800  
800  
800  
800  
Maximum Standby Current (mA)  
240  
240  
240  
240  
240  
Shaded area contains preliminary information.  
Maximum Ratings  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
DC Input Voltage ............................................0.5V to +7.0V  
Operating Range  
Storage Temperature .................................55°C to +125°C  
Ambient Temperature with  
Power Applied...............................................10°C to +85°C  
Ambient  
Temperature  
Range  
VCC  
Supply Voltage to Ground Potential............... 0.5V to +7.0V  
Commercial  
0°C to +70°C  
5V ± 10%  
DC Voltage Applied to Outputs  
in High Z State................................................ 0.5V to +VCC  
Electrical Characteristics Over the Operating Range  
Parameter  
Description  
Output HIGH Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
Input Load Current  
Test Conditions  
VCC = Min., IOH = 4.0 mA  
VCC = Min., IOL = 8.0 mA  
Min.  
Max.  
Unit  
V
VOH  
VOL  
VIH  
VIL  
IIX  
2.4  
0.4  
VCC + 0.3  
0.8  
V
2.2  
0.5  
10  
10  
V
V
GND VI VCC  
+10  
µA  
µA  
mA  
IOZ  
ICC  
Output Leakage Current  
GND VO VCC, Output Disabled  
+10  
VCC Operating Supply  
Current  
VCC = Max., IOUT = 0 mA,  
CSN VIL  
800  
ISB1  
ISB2  
Automatic CS Power-Down  
Current[1]  
Max. VCC, CS VIH,  
Min. Duty Cycle = 100%  
240  
mA  
Automatic CS Power-Down  
Current[1]  
Max. VCC, CS VCC 0.2V, 20, 25, 35  
IN VCC 0.2V, or VIN  
0.2V  
40  
mA  
mA  
V
12, 15  
120  
Capacitance[2]  
Parameter  
CINA  
Description  
Test Conditions  
Max.  
40  
Unit  
Input Capacitance (WE, OE, A018  
)
TA = 25°C, f = 1 MHz,  
VCC = 5.0V  
pF  
pF  
pF  
CINB  
Input Capacitance (CS)  
20  
COUT  
Output Capacitance  
20  
Notes:  
1. A pull-up resistor to VCC on the CS input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given.  
2. Tested on a sample basis.  
Document #: 38-05276 Rev. **  
Page 2 of 8  
CYM1846  
AC Test Loads and Waveforms  
ALL INPUT PULSES  
90%  
10%  
R1 481Ω  
R1 481 Ω  
3.0V  
GND  
5V  
5V  
OUTPUT  
90%  
10%  
OUTPUT  
R2  
255  
R2  
255  
30 pF  
5 pF  
5 ns  
5 ns  
INCLUDING  
JIG AND  
SCOPE  
INCLUDING  
JIG AND  
SCOPE  
(a)  
(b)  
Equivalent to:  
THÉVENIN EQUIVALENT  
167 Ω  
1.73V  
OUTPUT  
Switching Characteristics Over the Operating Range[3]  
1846-12  
1846-15  
Parameter  
Description  
Min.  
Max.  
Min.  
Max.  
Unit  
READ CYCLE  
tRC  
Read Cycle Time  
12  
3
15  
3
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
Address to Data Valid  
Data Hold from Address Change  
CS LOW to Data Valid  
OE LOW to Data Valid  
OE LOW to Low Z  
12  
15  
tOHA  
tACS  
12  
7
15  
8
tDOE  
tLZOE  
tHZOE  
tLZCS  
tHZCS  
tPD  
0
3
0
3
OE HIGH to High Z  
7
8
CS LOW to Low Z[4]  
CS HIGH to High Z[4, 5]  
7
8
CS HIGH to Power-Down  
12  
15  
WRITE CYCLE[6]  
tWC  
Write Cycle Time  
12  
9
15  
10  
10  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tSCS  
CS LOW to Write End  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
tAW  
9
tHA  
0
tSA  
1
1
tPWE  
tSD  
10  
7
12  
8
Data Set-Up to Write End  
Data Hold from Write End  
WE HIGH to Low Z  
tHD  
1
1
tLZWE  
tHZWE  
3
3
WE LOW to High Z[5]  
0
7
0
8
Shaded area contains preliminary information.  
Document #: 38-05276 Rev. **  
Page 3 of 8  
CYM1846  
Switching Characteristics Over the Operating Range[3] (continued)  
1846-20  
1846-25  
1846-35  
Parameter  
Description  
Min.  
20  
3
Max.  
Min.  
Max.  
Min.  
Max.  
Unit  
READ CYCLE  
tRC  
Read Cycle Time  
25  
3
35  
3
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
Address to Data Valid  
Data Hold from Address Change  
CS LOW to Data Valid  
OE LOW to Data Valid  
OE LOW to Low Z  
20  
25  
35  
tOHA  
tACS  
20  
10  
25  
15  
35  
25  
tDOE  
tLZOE  
tHZOE  
tLZCS  
tHZCS  
tPD  
0
3
0
3
0
3
OE HIGH to High Z  
10  
12  
12  
CS LOW to Low Z[4]  
CS HIGH to High Z[4, 5]  
10  
20  
12  
25  
12  
35  
CS HIGH to Power-Down  
WRITE CYCLE[6]  
tWC  
Write Cycle Time  
20  
15  
15  
0
25  
20  
20  
0
35  
30  
30  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tSCS  
CS LOW to Write End  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
tAW  
tHA  
tSA  
1
2
2
tPWE  
tSD  
15  
10  
1
20  
15  
2
30  
20  
2
Data Set-Up to Write End  
Data Hold from Write End  
WE HIGH to Low Z  
tHD  
tLZWE  
3
4
5
tHZWE  
WE LOW to High Z[6]  
0
10  
0
12  
0
12  
Notes:  
3. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified  
OL/IOH and 30-pF load capacitance.  
4. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device. These parameters are guaranteed and not 100% tested.  
5. HZCS and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage.  
I
t
6. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can  
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.  
Document #: 38-05276 Rev. **  
Page 4 of 8  
CYM1846  
Switching Waveforms  
Read Cycle No. 1 [7, 8]  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
Read Cycle No. 2 [7, 9]  
t
RC  
CS  
OE  
t
ACS  
t
HZOE  
t
DOE  
t
HZCS  
t
LZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA VALID  
DATA OUT  
t
LZCS  
t
PD  
t
PU  
ICC  
V
CC  
50%  
50%  
SUPPLY  
CURRENT  
ISB  
Write Cycle No. 1 (WE Controlled)[6]  
t
WC  
ADDRESS  
CS  
t
SCS  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
t
HD  
SD  
DATA IN  
DATA VALID  
t
t
LZWE  
HZWE  
HIGH IMPEDANCE  
DATA OUT  
DATA UNDEFINED  
Notes:  
7. WE is HIGH for read cycle.  
8. Device is continuously selected, CS = VIL, and OE= VIL  
.
9. Address valid prior to or coincident with CS transition LOW.  
Document #: 38-05276 Rev. **  
Page 5 of 8  
CYM1846  
Switching Waveforms (continued)  
Write Cycle No. 2 (CS Controlled) [6, 10]  
t
WC  
ADDRESS  
CS  
t
SCS  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
t
HD  
SD  
DATAIN  
DATA VALID  
t
t
LZWE  
HZWE  
HIGH IMPEDANCE  
DATAOUT  
DATA UNDEFINED  
Note:  
10. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.  
Truth Table  
CS WE OE Inputs/Output  
Mode  
Deselect/Power-Down  
Read  
H
L
L
L
X
H
L
X
L
High Z  
Data Out  
Data In  
High Z  
X
H
Write  
H
Deselect  
Ordering Information  
Speed  
Package  
Type  
Operating  
(ns)  
Ordering Code  
CYM1846PM12C  
CYM1846P812C  
CYM1846PZ12C  
CYM1846PM15C  
CYM1846P815C  
CYM1846PZ15C  
CYM1846PM20C  
CYM1846P820C  
CYM1846PZ20C  
CYM1846PM25C  
CYM1846P825C  
CYM1846PZ25C  
CYM1846PM35C  
CYM1846P835C  
CYM1846PZ35C  
Package Type  
Range  
12  
PM21  
PM21  
PZ11  
PM21  
PM21  
PZ11  
PM21  
PM21  
PZ11  
PM21  
PM21  
PZ11  
PM21  
PM21  
PZ11  
72-Pin Plastic SIMM Module  
Commercial  
72-Pin Plastic SIMM Module (gold contacts)  
72-Pin Plastic ZIP Module  
15  
20  
25  
35  
72-Pin Plastic SIMM Module  
Commercial  
Commercial  
Commercial  
Commercial  
72-Pin Plastic SIMM Module (gold contacts)  
72-Pin Plastic ZIP Module  
72-Pin Plastic SIMM Module  
72-Pin Plastic SIMM Module (gold contacts)  
72-Pin Plastic ZIP Module  
72-Pin Plastic SIMM Module  
72-Pin Plastic SIMM Module (gold contacts)  
72-Pin Plastic ZIP Module  
72-Pin Plastic SIMM Module  
72-Pin Plastic SIMM Module (gold contacts)  
72-Pin Plastic ZIP Module  
Shaded area contains preliminary information.  
Document #: 38-05276 Rev. **  
Page 6 of 8  
CYM1846  
Package Diagrams  
72-Pin Plastic SIMM Module PM21  
72-Pin Plastic ZIP Module PZ11  
Document #: 38-05276 Rev. **  
Page 7 of 8  
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
CYM1846  
Document Title: CYM1846 512K x 32 Static RAM Module  
Document Number: 38-05276  
Issue  
Date  
Orig. of  
Change  
REV.  
ECN NO.  
Description of Change  
**  
114177  
3/19/02  
DSG  
Change from Spec number: 38-M-00073 to 38-05276  
Document #: 38-05276 Rev. **  
Page 8 of 8  
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