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CYM1481ALPS-120C

型号:

CYM1481ALPS-120C

描述:

X8 SRAM模块\n[ x8 SRAM Module ]

品牌:

ETC[ ETC ]

页数:

8 页

PDF大小:

179 K

1CYM1481A  
CYM1481A  
2048K x 8 SRAM Module  
are constructed from four 512K x 8 SRAMs in plastic sur-  
face-mount packages on an epoxy laminate board with pins.  
On-board decoding selects one of the SRAMs from the  
high-order address lines, keeping the remaining devices in  
standby mode for minimum power consumption.  
Features  
• High-density 16-megabit SRAM modules  
• High-speed CMOS SRAMs  
— Access time of 70 ns  
• Low active power  
An active LOW write enable signal (WE) controls the writ-  
ing/reading operation of the memory. When MS and WE inputs  
are both LOW, data on the eight data input/output pins is writ-  
ten into the memory location specified on the address pins.  
Reading the device is accomplished by selecting the device  
and enabling the outputs MS and OE active LOW while WE  
remains inactive or HIGH. Under these conditions, the content  
of the location addressed by the information on the address  
pins is present on the eight data input/output pins.  
— 605 mW (max.), 2M x 8  
• Double-sided SMD technology  
• TTL-compatible inputs and outputs  
• Small footprint SIP  
— PCB layout area of 0.72 sq. in.  
• 2V data retention (L version)  
Functional Description  
The input/output pins remain in a high-impedance state unless  
the module is selected, outputs are enabled, and write enable  
(WE) is HIGH.  
The CYM1481A is a high-performance 16-megabit static RAM  
module organized as 2048K words by 8 bits. These modules  
Logic Block Diagram  
Pin Configuration  
SIP  
Top View  
A
1
2
3
4
5
6
19  
A –A  
0
18  
V
CC  
512K x 8  
SRAM  
19  
WE  
I/O  
2
I/O  
3
OE  
WE  
I/O  
0
A
A
A
A
7
8
9
10  
11  
12  
13  
14  
1
2
3
A
–A  
19 20  
4
2
GND  
I/O  
5
512K x 8  
SRAM  
1 of 4  
DECODER  
A
10  
A
11  
A
5
15  
16  
17  
18  
MS  
A
A
13  
14  
A
20  
MS  
19  
20  
21  
22  
23  
24  
25  
26  
27  
A
A
15  
16  
512K x 8  
SRAM  
A
A
12  
18  
A
6
I/O  
1
GND  
A
0
A
7
A
8
28  
29  
512K x 8  
SRAM  
A
9
30  
31  
32  
I/O  
7
I/O  
4
I/O  
33  
34  
35  
36  
6
A
17  
V
CC  
I/O –I/O  
0
7
8
OE  
1481-1  
/
Selection Guide  
CYM1481A  
Maximum Access Time (ns)  
70  
110  
64  
85  
110  
64  
100  
110  
64  
120  
110  
64  
Maximum Operating Current (mA)  
Maximum Standby Current (mA)  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
October 1990 - Revised April 16, 2001  
CYM1481A  
Maximum Ratings  
(Above which the useful life may be impaired.)  
Storage Temperature –55°C to +125°C  
DC Input Voltage–0.3V to +7.0V  
Output Current into Outputs (LOW)20 mA  
Ambient Temperature with  
Power Applied0°C to +70°C  
Operating Range  
Supply Voltage to Ground Potential–0.3V to +7.0V  
Ambient  
Range  
Temperature  
VCC  
DC Voltage Applied to Outputs  
in High Z State–0.3V to +7.0V  
Commercial  
0°C to +70°C  
5V ± 10%  
Electrical Characteristics Over the Operating Range  
1481A  
Parameter  
VOH  
Description  
Output HIGH Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
Input Load Current  
Output Leakage Current  
Test Conditions  
Min.  
Max.  
Unit  
V
VCC = Min., IOH = –1.0 mA  
2.4  
VOL  
VIH  
VIL  
IIX  
VCC = Min., IOL = 2.0 mA  
0.4  
VCC + 0.3  
0.8  
V
2.2  
–0.3  
–20  
–20  
V
V
GND < VI < VCC  
+20  
µA  
µA  
mA  
mA  
IOZ  
ICC  
ISB1  
GND < VO < VCC, Output Disabled  
+20  
VCC Operating Supply Current VCC = Max., MS < VIL, IOUT = 0 mA  
110  
Automatic MS  
Max. VCC, MS > VIH,  
64  
Power-Down Current  
Min. Duty Cycle = 100%  
ISB2  
Automatic MS  
Power-Down Current  
Max. VCC, MS > VCC – 0.2V, Standard  
32  
mA  
VIN > VCC – 0.2V, or VIN  
0.2V  
<
L Version  
–100, –120  
500  
µA  
L Version  
–85  
1600  
µA  
Capacitance[1]  
CYM1481AM  
ax.  
Parameter  
CINA  
Description  
Test Conditions  
Unit  
pF  
Input Capacitance (A0–16, OE, WE)  
Input Capacitance (A17–20, MS)  
Output Capacitance  
TA = 25°C, f = 1 MHz,  
VCC = 5.0V  
125  
25  
CINB  
pF  
COUT  
165  
pF  
Note:  
1. Tested on a sample basis.  
2
CYM1481A  
AC Test Loads and Waveforms  
R1 2530  
R1 2530Ω  
ALL INPUT PULSES  
90%  
10%  
5V  
5V  
OUTPUT  
3.0V  
GND  
90%  
10%  
OUTPUT  
R2  
R2  
2830Ω  
100 pF  
2830Ω  
5 pF  
< 10 ns  
< 10 ns  
INCLUDING  
JIG AND  
SCOPE  
INCLUDING  
JIG AND  
SCOPE  
1481-3  
1481-4  
(a)  
(b)  
1481-2  
Equivalent to:  
OUTPUT  
THÉVENIN EQUIVALENT  
1340Ω  
2.64V  
Switching Characteristics Over the Operating Range[2]  
1481A-70  
1481A–85  
1481A–100  
1481A–120  
Parameter  
READ CYCLE  
tRC  
Description  
Min. Max. Min. Max. Min. Max. Min. Max. Unit  
Read Cycle Time  
70  
5
85  
10  
100  
10  
120  
10  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
Address to Data Valid  
Data Hold from Address Change  
MS LOW to Data Valid  
OE LOW to Data Valid  
OE LOW to Low Z  
OE HIGH to High Z[3]  
MS LOW to Low Z[4]  
70  
85  
100  
120  
tOHA  
tAMS  
70  
40  
85  
45  
100  
50  
120  
60  
tDOE  
tLZOE  
5
5
5
5
5
tHZOE  
30  
30  
30  
30  
35  
35  
45  
45  
tLZMS  
10  
10  
10  
tHZMS  
MS HIGH to High Z[3, 4]  
WRITE CYCLE[5]  
tWC  
tSMS  
tAW  
Write Cycle Time  
70  
65  
65  
5
85  
75  
75  
7
100  
90  
90  
7
120  
100  
100  
7
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
MS LOW to Write End  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
tHA  
tSA  
0
5
5
5
tPWE  
tSD  
65  
30  
0
65  
35  
5
75  
40  
5
85  
45  
5
Data Set-Up to Write End  
Data Hold from Write End  
WE LOW to High Z[3]  
tHD  
tHZWE  
30  
30  
35  
40  
tLZWE  
WE HIGH to Low Z  
5
5
5
5
Notes:  
2. Test conditions assume signal transition time of 10 µs or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, output loading of 1 TTL load, and  
100-pF load capacitance.  
3. tHZOE, tHZMS, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage.  
4. At any given temperature and voltage condition, tHZMS is less than tLZMS for any given device. These parameters are guaranteed and not 100% tested.  
5. The internal write time of the memory is defined by the overlap of MS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can  
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.  
3
CYM1481A  
Data Retention Characteristics (L Version Only)  
1481A–100  
148A1–120  
1481A-70  
1481A–85  
Parameter  
VDR  
ICCDR  
Description  
Test Conditions  
Min. Max. Min. Max.  
Min.  
Max.  
Unit  
V
VCC for Retention Data  
2
2
2
Data Retention Current VDR = 3.0V,  
800  
800  
250  
µA  
ns  
MS > VCC – 0.2V,  
VIN > VCC – 0.2V or VIN  
< 0.2V  
[6]  
tCDR  
Chip Deselect to Data  
Retention Time  
0
5
0
5
0
5
tR  
Operation Recovery  
Time  
ns  
Data Retention Waveform  
DATA RETENTION MODE  
> 2V  
V
CC  
4.5V  
4.5V  
V
DR  
t
t
R
CDR  
V
DR  
V
IH  
V
IH  
CS  
1481-6  
Switching Waveforms  
Read Cycle No. 1[7, 8]  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATAOUT  
PREVIOUS DATA VALID  
DATA VALID  
1481-7  
Notes:  
6. Guaranteed, not tested.  
7. Device is continuously selected. OE, MS = VIL.  
8. Address valid prior to or coincident with MS transition LOW.  
4
CYM1481A  
Switching Waveforms (continued)  
Read Cycle No. 2[8, 9]  
t
RC  
MS  
t
AMS  
OE  
t
HZOE  
t
DOE  
t
HZMS  
t
LZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA VALID  
DATA OUT  
t
LZMS  
1481-8  
Write Cycle No. 1[5, 10]  
t
WC  
ADDRESS  
MS  
t
SMS  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
t
HD  
SD  
DATA IN  
DATA VALID  
t
t
LZWE  
HZWE  
HIGH IMPEDANCE  
DATA I/O  
DATA UNDEFINED  
1481-9  
Notes:  
9. WE is HIGH for read cycle.  
10. Data I/O is high impedance if OE = VIH  
.
5
CYM1481A  
Switching Waveforms (continued)  
Write Cycle No. 2[5, 10, 11]  
t
WC  
ADDRESS  
t
SA  
t
SMS  
MS  
WE  
t
t
HA  
AW  
t
PWE  
t
t
HD  
SD  
DATA IN  
DATA I/O  
DATA VALID  
t
HZWE  
HIGH IMPEDANCE  
DATA UNDEFINED  
1481-10  
Note:  
11. If MS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.  
6
CYM1481A  
Truth Table  
MS WE OE Input/Outputs  
Mode  
Deselect/Power-Down  
Read  
H
L
L
L
X
H
L
X
L
High Z  
Data Out  
Data In  
High Z  
X
H
Write  
H
Deselect  
Ordering Information  
Speed  
(ns)  
Package  
Type  
Package  
Type  
Operating  
Range  
Ordering Code  
70  
CYM1481APS-70C  
CYM1481ALPS-70C  
CYM1481APS–85C  
CYM1481ALPS–85C  
CYM1481APS–100C  
CYM1481ALPS–100C  
CYM1481APS–120C  
CYM1481ALPS–120C  
PS10  
36-Pin SIP Module  
Commercial  
Commercial  
Commercial  
Commercial  
85  
PS10  
PS10  
PS10  
36-Pin SIP Module  
36-Pin SIP Module  
36-Pin SIP Module  
100  
120  
Document #: 38-M-00041-*D  
7
CYM1481A  
Package Diagram  
36-Pin SIP Module PS10  
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
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