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CYK512K16SCCAU

型号：

CYK512K16SCCAU

描述：

内存\n[ Memory ]

品牌：

ETC[ ETC ]

页数：

10 页

PDF大小：

175 K

下载PDF手册
ADVANCE  
INFORMATION  
CYK512K16SCCAU  
MoBL3™  
8-Mb (512K x 16) Pseudo Static RAM  
current. This is ideal for providing More Battery Life(MoBL®)  
in portable applications such as cellular telephones. The  
device can be put into standby mode reducing power  
consumption by more than 99% when deselected using CE  
LOW, CE2 HIGH or both BHE and BLE are HIGH. The  
input/output pins (I/O0 through I/O15) are placed in a  
high-impedance state when: deselected (CE HIGH, CE2 LOW  
OE is deasserted HIGH), or during a write operation (Chip  
Enabled and Write Enable WE LOW). The device also has an  
automatic power-down feature that significantly reduces  
power consumption by 99% when addresses are not toggling  
even when the chip is selected (Chip Enable CE LOW, CE2  
HIGH and both BHE and BLE are LOW). Reading from the  
device is accomplished by asserting the Chip Enables (CE  
LOW and CE2 HIGH) and Output Enable (OE) LOW while  
forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE)  
is LOW, then data from the memory location specified by the  
address pins will appear on I/O0 to I/O7. If Byte High Enable  
(BHE) is LOW, then data from memory will appear on I/O8 to  
I/O15. See the Truth Table for a complete description of read  
and write modes.  
Features  
• Wide voltage range: 2.70V–3.30V  
• Access Time: 70 ns  
• Ultra-low active power  
— Typical active current: 2.0 mA @ f = 1 MHz  
— Typical active current: 11 mA @ f = fmax  
• Ultra low standby power  
• Easy memory expansion with CE, CE2, and OE features  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Offered in a 48-ball BGA Package  
Functional Description[1]  
The CYK512K16SCCAU is a high-performance CMOS  
pseudo static RAM organized as 512K words by 16 bits that  
supports an asynchronous memory interface. This device  
features advanced circuit design to provide ultra-low active  
Logic Block Diagram  
DATA IN DRIVERS  
A
10  
A
9
8
7
6
5
4
3
2
1
0
A
A
A
A
A
512K x 16  
RAM Array  
I/O –I/O  
0
7
A
A
A
1T  
I/O –I/O  
8
15  
A
COLUMN DECODER  
BHE  
WE  
CE  
2
CE  
OE  
BLE  
Power -Down  
Circuit  
Note:  
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05425 Rev. **  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised January 8, 2004  
ADVANCE  
INFORMATION  
CYK512K16SCCAU  
MoBL3™  
Pin Configuration[2, 3, 4]  
FBGA  
Top View  
1
2
4
3
5
6
A
A
2
A
CE  
OE  
BLE  
2
0
1
A
B
C
A
A
I/O BHE  
8
CE  
I/O  
I/O  
0
4
3
A
A
6
I/O I/O  
I/O  
2
5
9
10  
1
Vcc  
Vss  
A
V
I/O  
I/O  
3
A
D
E
F
SS  
7
11  
17  
GND  
A
16  
V
CC  
I/O  
I/O  
12  
4
A
A
15  
I/O  
I/O  
5
I/O  
I/O  
14  
13  
14  
6
NC/  
A
A
G
H
I/O  
WE I/O  
13  
12  
15  
7
NC/  
A
A
9
A
11  
A
8
A
10  
18  
Note:  
2. DNU pins have to be left floating or tied to Vss.  
3. Ball G2, H6 are expansion pins to 16-Mbit and 32-Mbit densities, respectively.  
4. NC “no connect” - not connected internally to the die.  
Document #: 38-05425 Rev. **  
Page 2 of 10  
ADVANCE  
INFORMATION  
CYK512K16SCCAU  
MoBL3™  
DC Voltage Applied to Outputs  
Maximum Ratings  
in High Z State[5, 6, 7] ........................................–0.2V to 3.3V  
DC Input Voltage[5, 6, 7].................................... –0.2V to 3.3V  
Output Current into Outputs (LOW)............................ 20 mA  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Storage Temperature ................................–65°C to + 150°C  
Static Discharge Voltage.......................................... > 2001V  
(per MIL-STD-883, Method 3015)  
Ambient Temperature with  
Power Applied ...........................................–55°C to + 125°C  
Latch-up Current.................................................... > 200 mA  
Supply Voltage to Ground Potential ................ –0.4V to 4.6V  
Operating Range  
Device  
Range  
Ambient Temperature  
VCC  
CYK512K16SCCAU  
Industrial  
–25°C to +85°C  
2.70V to 3.30V  
Product Portfolio  
Power Dissipation  
Operating ICC(mA)  
f = 1MHz f = fmax  
Typ.[8] Max. Typ.[8] Max.  
3.5 11 17  
Speed  
(ns)  
Product  
VCC Range (V)  
Standby ISB2(µA)  
Min.  
2.70  
Typ.[8]  
Max.  
Typ.[8]  
Max.  
CYK512K16SCCAU-70BAI  
3.0  
3.30  
70  
2
55  
80  
Electrical Characteristics Over the Operating Range  
CYK512K16SCCAU-70  
Parameter  
VCC  
Description  
Test Conditions  
Min.  
2.7  
Typ.[8]  
Max.  
Unit  
Supply Voltage  
3.3  
V
V
VOH  
VOL  
Output HIGH Voltage IOH = –1.0 mA  
Output LOW Voltage IOL = 2.0 mA  
Input HIGH Voltage VCC= 2.7V to 3.3V  
2.4  
0.4  
VCC + 0.3V  
0.4  
V
VIH  
0.8*Vcc  
–0.3  
V
VIL  
Input LOW Voltage  
VCC= 2.7V to 3.3V (F = 0)  
GND < VI < VCC  
V
IIX  
Input Leakage  
Current  
–1  
+1  
µA  
IOZ  
ICC  
Output Leakage  
Current  
GND < VO < VCC, Output Disabled  
–1  
+1  
µA  
VCC OperatingSupply f = fMAX = 1/tRC  
Current  
VCC = VCCmax  
IOUT = 0 mA  
CMOS levels  
11  
17  
mA  
mA  
f = 1 MHz  
2.0  
3.5  
ISB1  
Automatic CE  
Power-down  
Current — CMOS  
Inputs  
CE > VCC−0.2V or CE2< 0.2V  
Vcc = 3.3V  
400  
µA  
VIN>VCC–0.2V, VIN<0.2V)  
f = fMAX (Address and Data Only),  
f = 0 (OE, WE, BHE and BLE),  
VCC=3.30V  
ISB2  
Automatic CE  
Power-down  
Current — CMOS  
Inputs  
CE > VCC – 0.2V or CE2 < 0.2V,  
VIN > VCC – 0.2V or VIN < 0.2V,  
f = 0, VCC = 3.30V  
Vcc = 3.3V  
Vcc = 3.0V  
Vcc = 2.8V  
55  
50  
45  
80  
70  
60  
µA  
µA  
µA  
Notes:  
5. VIH(MAX) = VCC + 0.5V for pulse durations less than 20 ns.  
6. VIL(MIN) = –0.5V for pulse durations less than 20 ns.  
7. Overshoot and undershoot specifications are characterized and are not 100% tested.  
8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC (typ) and TA = 25C.  
9. Vcc and Vcc must be at minimal operational levels before inputs are turned ON.  
Document #: 38-05425 Rev. **  
Page 3 of 10  
ADVANCE  
INFORMATION  
CYK512K16SCCAU  
MoBL3™  
Capacitance[10]  
Parameter  
Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
Max.  
Unit  
pF  
CIN  
TA = 25°C, f = 1 MHz,  
VCC = VCC(typ)  
6
8
COUT  
pF  
Thermal Resistance[10]  
Parameter  
Description  
Test Conditions  
BGA  
Unit  
ΘJA  
Thermal Resistance  
(Junction to Ambient)  
Still Air, soldered on a 3 × 4.5 inch, two-layer printed  
circuit board  
55  
°C/W  
ΘJC  
Thermal Resistance  
(Junction to Case)  
16  
°C/W  
AC Test Loads and Waveforms  
R1  
ALL INPUT PULSES  
VCC  
90%  
90%  
VCC  
OUTPUT  
10%  
10%  
Fall Time = 1 V/ns  
GND  
Rise Time = 1 V/ns  
R2  
50 pF  
INCLUDING  
JIG AND  
SCOPE  
Equivalent to:  
THÉVENIN EQUIVALENT  
RTH  
OUTPUT  
V
Parameters  
3.0V VCC  
1179  
Unit  
Ω
R1  
R2  
1941  
733  
Ω
Ω
RTH  
VTH  
1.87  
V
Switching Characteristics Over the Operating Range [11]  
70 ns  
Parameter  
Read Cycle  
Description  
Min.  
Max.  
Unit  
tRC  
Read Cycle Time  
70  
10  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
Address to Data Valid  
70  
tOHA  
tACE  
tDOE  
tLZOE  
tHZOE  
tLZCE  
tHZCE  
tDBE  
tLZBE  
Data Hold from Address Change  
CE LOW and CE2 HIGH to Data Valid  
OE LOW to Data Valid  
OE LOW to LOW Z[12, 13]  
OE HIGH to High Z[12, 13]  
CE LOW and CE2 HIGH to Low Z[12, 13]  
CE HIGH and CE2 LOW to High Z[12, 13]  
BLE / BHE LOW to Data Valid  
BLE / BHE LOW to Low Z[12, 13]  
BLE / BHE HIGH to HIGH Z[12, 13]  
70  
35  
5
5
25  
25  
70  
5
tHZBE  
25  
Notes:  
10. Tested initially and after any design or process changes that may affect these parameters.  
11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of VCC(typ)/2, input pulse levels  
of 0V to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.  
12. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state—100 mV from the steady state.  
13. High-Z and Low-Z parameters are characterized and are not 100% tested.  
Document #: 38-05425 Rev. **  
Page 4 of 10  
ADVANCE  
INFORMATION  
CYK512K16SCCAU  
MoBL3™  
Switching Characteristics Over the Operating Range (continued)[11]  
70 ns  
Parameter  
Description  
Min.  
Max.  
Unit  
tSK  
Address Skew  
10  
ns  
Write Cycle[14]  
tWC  
tSCE  
tAW  
Write Cycle Time  
70  
60  
60  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CE LOW and CE2 HIGH to Write End  
Address Set-up to Write End  
Address Hold from Write End  
Address Set-up to Write Start  
WE Pulse Width  
tHA  
tSA  
0
tPWE  
tBW  
tSD  
45  
60  
45  
0
BLE / BHE LOW to Write End  
Data Set-up to Write End  
Data Hold from Write End  
WE LOW to High-Z[12, 13]  
WE HIGH to Low-Z[12, 13]  
tHD  
tHZWE  
tLZWE  
25  
5
Switching Waveforms  
[15]  
Read Cycle 1 (Address Transition Controlled)  
tRC  
ADDRESS  
t
AA  
tSK  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
Notes:  
14. Internal memory write time is defined by overlap of WE, CE = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any  
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to edge of signal that terminates the write.  
15. WE is HIGH for read cycle.  
Document #: 38-05425 Rev. **  
Page 5 of 10  
ADVANCE  
INFORMATION  
CYK512K16SCCAU  
MoBL3™  
Switching Waveforms (continued)  
[15]  
Read Cycle 2 (OE Controlled)  
ADDRESS  
t
RC  
CE  
tSK  
t
PD  
t
HZCE  
CE  
2
t
ACE  
BHE/BLE  
t
DBE  
t
HZBE  
t
LZBE  
OE  
t
HZOE  
t
DOE  
LZOE  
HIGH IMPEDANCE  
t
HIGH  
IMPEDANCE  
DATA OUT  
DATA VALID  
t
LZCE  
50%  
50%  
Write Cycle 1 (WE Controlled) [14, 13, 16, 17, 18]  
t
WC  
ADDRESS  
t
SCE  
CE  
CE  
2
t
t
HA  
AW  
t
t
PWE  
SA  
WE  
t
BW  
BHE/BLE  
OE  
t
t
SD  
HD  
VALID DATA  
DATA I/O  
Don’t Care  
t
HZOE  
Notes:  
16. Data I/O is high impedance if OE = VIH  
.
17. If Chip Enable goes INACTIVE and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high-impedance state.  
18. During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.  
19. H = VIH, L = VIL, X = Don’t Care.  
Document #: 38-05425 Rev. **  
Page 6 of 10  
ADVANCE  
INFORMATION  
CYK512K16SCCAU  
MoBL3™  
Switching Waveforms (continued)  
[14, 13, 16, 17, 18]  
Write Cycle 2 (CE or CE Controlled)  
2
t
WC  
ADDRESS  
CE  
t
SCE  
CE  
2
tSA  
t
t
HA  
AW  
tPWE  
WE  
t
BW  
BHE/BLE  
OE  
t
t
SD  
HD  
VALID DATA  
DATA I/O  
Don’t Care [18]  
t
HZOE  
Write Cycle 3 (WE Controlled, OE LOW)[17, 18]  
t
WC  
ADDRESS  
CE  
t
SCE  
CE  
2
t
BW  
BHE/BLE  
t
t
HA  
AW  
t
t
PWE  
SA  
WE  
t
t
HD  
SD  
Don’t Care  
DATAI/O  
VALID DATA  
t
LZWE  
t
HZWE  
Document #: 38-05425 Rev. **  
Page 7 of 10  
ADVANCE  
INFORMATION  
CYK512K16SCCAU  
MoBL3™  
Switching Waveforms (continued)  
Write Cycle 4 (BHE/BLE Controlled, OE LOW)[17, 18]  
t
WC  
ADDRESS  
CE  
CE  
2
t
SCE  
t
t
HA  
AW  
tBW  
BHE/BLE  
WE  
t
SA  
tPWE  
t
t
HD  
SD  
Don’t Care  
DATA I/O  
VALID DATA  
Truth Table[19]  
CE  
H
X
CE2  
X
WE  
X
OE  
X
BHE  
BLE  
X
Inputs/Outputs  
Mode  
Power  
Standby (ISB  
Standby (ISB  
Standby (ISB  
Active (ICC  
Active (ICC  
X
X
H
L
High Z  
Deselect/Power-down  
Deselect/Power-down  
Deselect/Power-down  
Read  
)
L
X
X
X
High Z  
)
X
X
X
X
H
High Z  
)
L
H
H
L
L
Data Out (I/O0 – I/O15)  
)
L
H
H
L
H
L
Data Out (I/O0 – I/O7);  
High Z (I/O8 – I/O15)  
Read  
)
L
H
H
L
L
H
High Z (I/O0 – I/O7);  
Read  
Active (ICC)  
Data Out (I/O8 – I/O15)  
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
X
X
L
H
L
H
L
L
L
L
High Z  
Output Disabled  
Output Disabled  
Output Disabled  
Write  
Active (ICC  
Active (ICC  
Active (ICC  
Active (ICC  
Active (ICC  
)
High Z  
)
High Z  
)
L
Data In (I/O0 – I/O15)  
)
L
H
Data In (I/O0 – I/O7);  
High Z (I/O8 – I/O15)  
Write  
)
L
H
L
X
L
H
High Z (I/O0 – I/O7);  
Data In (I/O8 – I/O15)  
Write  
Active (ICC)  
Ordering Information  
Speed  
Package  
Name  
Operating  
Range  
(ns)  
Ordering Code  
CYK512K16SCCAU-70BAI  
Package Type  
48-ball Fine Pitch BGA (6 mm × 8mm × 1.2 mm)  
70  
BA48K  
Industrial  
Document #: 38-05425 Rev. **  
Page 8 of 10  
ADVANCE  
INFORMATION  
CYK512K16SCCAU  
MoBL3™  
Package Diagram  
48-Ball (6 mm x 8 mm x 1.2 mm) FBGA BA48K  
BOTTOM VIEW  
A1 CORNER  
TOP VIEW  
Ø0.05 M C  
Ø0.25 M C A B  
Ø0.30 0.05ꢀ(48X  
A1 CORNER  
1
2
3
5
6
6
5
3
2
1
(
(
A
B
A
B
C
C
D
D
E
F
E
F
G
H
G
H
1.475  
A
A
0.75  
3.75  
6.00 0.10  
B
6.00 0.10  
B
0.15ꢀ(8X  
REFERENCE JEDEC MO-207  
SEATING PLANE  
C
51-85193-*A  
MoBL is a registered trademark, and MoBL3 and More Battery Life are trademarks, of Cypress Semiconductor. All product and  
company names mentioned in this document are trademarks of their respective holders.  
Document #: 38-05425 Rev. **  
Page 9 of 10  
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
ADVANCE  
INFORMATION  
CYK512K16SCCAU  
MoBL3™  
Document History Page  
Document Title: CYK512K16SCCAU 8-Mb (512K x 16) Pseudo Static RAM  
Document Number: 38-05425  
Orig. of  
REV.  
ECN NO. Issue Date Change  
Description of Change  
**  
130538 01/27/2004  
AWK  
New Data Sheet  
Document #: 38-05425 Rev. **  
Page 10 of 10  
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