SOT223 N-CHANNEL ENHANCEMENT MODE
LOW THRESHOLD VERTICAL DMOS FET
ZVNL110G
ISSUE 2 - FEBRUARY 1996
✪
FEATURES
D
*
LOW RDS(ON) - 3Ω
PARTMARKING DETAIL - ZVNL110
S
D
G
ABSOLUTE MAXIMUM RATINGS.
PARAMETER
S YMBOL
VDS
VALUE
UNIT
V
Dra in -S o u rce Vo lta g e
100
Co n tin u o u s Drain Cu rren t at Ta m b=25°C
Pu ls ed Dra in Cu rre n t
ID
600
m A
A
IDM
6
Ga te-S o u rce Vo lta g e
VGS
V
± 20
2
Po w er Dis s ip a tio n a t Ta m b=25°C
Op e ratin g a n d S to ra g e Te m p e ratu re Ra n g e
Pto t
W
Tj:Ts tg
-55 to +150
°C
ELECTRICAL CHARACTERISTICS (at T
= 25°C unless otherw ise stated).
am b
PARAMETER
S YMBOL MIN. MAX. UNIT CONDITIONS .
Dra in -S o u rce Bre akd o w n
Vo lta g e
BVDS S
100
V
ID=1m A, VGS=0V
Gate-Sou rce Threshold Voltage VGS (th )
0.75
1.5
V
ID=1m A, VDS= VGS
Ga te-Bo d y Lea ka g e
IGS S
IDS S
100
n A
V
GS=± 20V, VDS=0V
Ze ro Ga te Vo lta g e Dra in
Cu rre n t
10
100
VDS=100V, VGS=0V
VDS=80V, VGS=0V, T=125°C(2)
µA
µA
On -S ta te Dra in Cu rre n t(1)
ID(o n )
750
225
m A
VDS=25V, VGS=5V
VGS=5V, ID=250m A
S tatic Drain -S o u rce On -S ta te
Res ista n ce (1)
RDS (o n )
4.5
3.0
Ω
Ω
VGS=10V, ID=500m A
Forward Transconductance(1)(2) g fs
m S
p F
p F
VDS=25V, ID=500m A
In p u t Ca p a cita n ce (2)
Cis s
Co s s
75
25
Co m m o n S o u rce Ou tp u t
Cap acita n ce (2)
VDS=25V, VGS=0V, f=1MHz
Reverse Transfer Capacitance (2) Crs s
8
p F
n s
n s
n s
n s
Tu rn -On De la y Tim e (2)(3)
Ris e Tim e (2)(3)
td (o n )
7
tr
12
15
13
VDD≈25V, ID=1A, VGS =10V
Tu rn -Off De la y Tim e (2)(3)
Fa ll Tim e (2)(3)
td (o ff)
tf
(1) Measured under pulsed conditions. Width=300µs. Duty cycle ≤2% (2) Sam ple test.
(3) Switching tim es m easured with 50Ω source im pedance and <5ns rise tim e on a pulse generator
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