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RX-8025SA:AA0:PURESN

型号：

RX-8025SA:AA0:PURESN

品牌：

SEIKO[ SEIKO EPSON CORPORATION ]

页数：

34 页

PDF大小：

740 K

下载PDF手册
ETM10E-04  
Application Manua  
l
Real Time Clock Module  
RX-8025SA/NB  
Preliminary  
Model  
Product Number  
Q41802551xxxx00  
Q41802591xxxx00  
RX-8025SA  
RX-8025NB  
NOTICE  
•
•
This material is subject to change without notice.  
Any part of this material may not be reproduced or duplicated in any form or any means without the  
written permission of Seiko Epson.  
•
The information about applied circuitry, software, usage, etc. written in this material is intended for  
reference only. Seiko Epson does not assume any liability for the occurrence of infringing on any  
patent or copyright of a third party. This material does not authorize the licensing for any patent or  
intellectual copyrights.  
•
•
When exporting the products or technology described in this material, you should comply with the  
applicable export control laws and regulations and follow the procedures required by such laws and  
regulations.  
You are requested not to use the products (and any technical information furnished, if any) for the  
development and/or manufacture of weapon of mass destruction or for other military purposes. You  
are also requested that you would not make the products available to any third party who may use the  
products for such prohibited purposes.  
•
These products are intended for general use in electronic equipment. When using them in specific  
applications that require extremely high reliability, such as the applications stated below, you must  
obtain permission from Seiko Epson in advance.  
/ Space equipment (artificial satellites, rockets, etc.) / Transportation vehicles and related  
(automobiles, aircraft, trains, vessels, etc.) / Medical instruments to sustain life /  
Submarine transmitters / Power stations and related / Fire work equipment and security  
equipment / traffic control equipment / and others requiring equivalent reliability.  
•
All brands or product names mentioned herein are trademarks and/or registered trademarks of their  
respective.  
RX - 8025 SA NB  
/
Contents  
1. Overview........................................................................................................................1  
2. Block Diagram ...............................................................................................................1  
3. Description of Pins.........................................................................................................2  
3.1. Pin Layout ........................................................................................................................................2  
3.2. Pin Functions....................................................................................................................................2  
4. Absolute Maximum Ratings ...........................................................................................3  
5. Recommended Operating Conditions............................................................................3  
6. Frequency Characteristics .............................................................................................3  
7. Electrical Characteristics................................................................................................3  
7.1. DC Electrical Characteristics............................................................................................................3  
7.2. AC Electrical Characteristics............................................................................................................4  
8.1. Functional descriptions ...............................................................................................5  
8.1. Overview of Functions......................................................................................................................5  
8.2. Description of Registers ...................................................................................................................6  
8.3. Clock Precision Adjustment Function.............................................................................................13  
8.4. Periodic Interrupt Function .............................................................................................................15  
8.5. Alarm W function............................................................................................................................17  
8.6. Alarm D function.............................................................................................................................19  
8.7. The various detection Functions ....................................................................................................20  
2
8.8. Reading/Writing Data via the I C Bus Interface.............................................................................23  
8.9. External Connection Example ........................................................................................................27  
9. External Dimensions / Marking Layout.........................................................................28  
9.1. External Dimensions.......................................................................................................................28  
9.2. Marking Layout...............................................................................................................................28  
10. Reference Data .........................................................................................................29  
11. Application notes .......................................................................................................30  
RX - 8025 SA  
/
NB  
I2C-Bus Interface Real-time Clock Module  
RX - 8025 SA NB  
/
• Features built-in 32.768-kHz quartz oscillator, frequency adjusted for high precision  
( ± 5 × 10−6 when Ta = +25°C )  
• Supports I2C-Bus's high speed mode (400 kHz)  
• Includes time (H/M/S) and calendar (YR/MO/DATE/DAY) counter functions (BCD code)  
• Select between 12-hr and 24-hr clock mode.  
• Auto calculation of leap years until 2099  
• Built-in high-precision clock precision control logic  
• CPU interrupt generation function (cycle time range: 1 month to 0.5 seconds, includes interrupt flags  
and interrupt stop function)  
• Dual alarm functions (Alarm_W: Day/Hour/Min, Alarm_D: Hour/Min)  
• 32.768-kHz clock output (CMOS output with control pin)  
• Oscillation stop detection function (used to determine presence of internal data)  
• Power supply voltage monitoring function (with selectable detection threshold)  
• Wide clock (retention) voltage range: 1.15 V to 5.5 V  
• Wide interface voltage range: 1.7 V to 5.5 V  
• Low current consumption: 0.48 µA/3.0 V (Typ.)  
1. Overview  
This module is an I2C bus interface-compliant real-time clock which includes a 32.768-kHz quartz oscillator  
that has been adjusted for high precision. In addition to providing a function for generating six types of  
interrupts, a dual alarm function, an oscillation stop detection function (used to determine presence of valid  
internal data at power-on), and a power supply voltage monitoring function, this module includes a digital clock  
precision adjustment function that can be used to set various levels of precision.  
Since the internal oscillation circuit is driven at a constant voltage, 32.768-kHz clock output is stable and free  
of voltage fluctuation effects.  
This implementation of multiple functions in one SMT package is ideal for applications ranging from cellular  
phones to PDAs and other small electronic devices.  
2. Block Diagram  
Alarm_W Register  
( Min,Hour,Day)  
Comparator_W  
Comparator_D  
FOUT  
FOE  
32 kHz  
Output  
Control  
Voltage  
Detect  
V
DD  
Alarm_D Register  
( Min,Hour )  
Divider  
Correc  
-tion  
Time Counter  
( Sec,Min,Hour,Day,Date,Month,Year )  
Div.  
OSC  
Address  
Decoder  
Address  
Register  
SCL  
SDA  
GND  
OSC  
Detect  
I/O  
Control  
/ INTA  
/ INTB  
Interrupt Control  
Shift Register  
Page - 1  
ETM10E-04  
RX - 8025 SA NB  
/
3. Description of Pins  
3.1. Pin Layout  
RX - 8025 SA  
RX - 8025 NB  
1. FOE  
2. VDD  
22. N.C.  
21. N.C.  
20. N.C.  
19. N.C.  
18. N.C.  
17. N.C.  
16. N.C.  
15. N.C.  
14. N.C.  
1. N.C.  
2. SCL  
3. FOUT  
4. N.C.  
5. TEST  
6. VDD  
14. N.C.  
13. SDA  
12. / INTB  
11. GND  
10. / INTA  
9. N.C.  
# 1  
# 22  
(GND)  
3.  
4. TEST  
5. FOUT  
6. SCL  
7. SDA  
8. / INTB  
9. GND  
# 11  
(#12)  
10. / INTA  
11. N.C.  
(13)  
(12)  
−
−
7. FOE  
8. N.C.  
SOP - 14pin  
SON - 22pin  
3.2. Pin Functions  
Signal  
I / O  
Function  
name  
This is the serial clock input pin for I2C communications. Data input and output across the  
SDA pin is synchronized with this pin's clock signal.  
SCL  
I
Up to 5.5 V can be used for this input, regardless of the power supply voltage.  
This pin's signal is used for input and output of address, data, and ACK bits, synchronized  
with the serial clock used for I2C communications.  
SDA  
I/O  
The SDA pin is an N-ch open drain pin during output. Be sure to connect a suitable pull-up  
resistance relative to the signal line capacity.  
FOUT terminal is 32.768 kHz clock output terminal (C-MOS) that output control is possible.  
FOE terminal is the input terminal controlling the output of FOUT pin with /CLEN1 and  
/CLEN2 bit.  
FOUT  
O
The output of FOUT terminal stops when /CLEN1bit and /CLEN2 bit both sets to "1".  
FOUT output stops when FOE is Low or OPEN. Status of FOUT output stopped is " L ".  
The logic table.  
FOE  
input  
/CLEN1  
bit  
/CLEN2  
bit  
FOUT  
output  
L
Χ
0
0
1
1
Χ
0
1
0
1
OFF ( " L " )  
32.768 kHz  
32.768 kHz  
32.768 kHz  
OFF ( " L " )  
H
FOE  
I
' Χ ' Don't care.  
FOE terminal had pull-down resistor built-in and input voltage is possible regardless of  
power supply voltage to 5.5 V.  
This interrupt output A pin is an N-ch open drain output.  
It outputs alarm interrupts (Alarm_D) and periodic interrupts.  
This interrupt output B pin is an N-ch open drain output.  
It outputs alarm interrupts (Alarm_W).  
/INTA  
/INTB  
TEST  
VDD  
O
O
−
This pin is used by the manufacturer for testing. Do not connect externally.  
This pin is connected to a positive power supply.  
−
GND  
This pin is connected to a ground.  
−
(GND)  
This pin has the same voltage level as GND. Do not connect externally.  
−
This pin is not connected to the internal IC.  
However, note with caution that the RX-8025NB's N.C. pins (pins 14 to 22) are interconnected  
via the internal frame.  
N.C.  
−
Leave N.C. pins open or connect them to GND or VDD  
.
Note: Be sure to connect a bypass capacitor rated at least 0.1 ꢀF between VDD and GND.  
Page - 2  
ETM10E-04  
RX - 8025 SA  
/
NB  
4. Absolute Maximum Ratings  
GND = 0 V  
Item  
Supply voltage  
Input voltage  
Symbol  
Condition  
Between VDD and GND  
SCL, SDA, FOE pins  
SDA, /INTA, /INTB pins  
FOUT pin  
Rating  
Unit  
V
V
V
DD  
to +6.5  
−0.3  
GND−0.3  
GND−0.3  
GND−0.3  
V
I
to +6.5  
V
V
O1  
O2  
to +6.5  
V
Output voltage  
to VDD+0.3  
V
When stored separately, without  
packaging  
Storage temperature  
TSTG  
to +125  
−55  
°C  
5. Recommended Operating Conditions  
GND = 0 V  
Item  
Symbol  
Condition  
Min.  
Typ.  
Max.  
Unit  
Operating supply voltage  
Clock supply voltage  
Applied voltage when OFF  
Pull-up resistance  
V
DD  
3.0  
3.0  
5.5  
5.5  
5.5  
10  
V
V
°C  
kΩ  
°C  
−
−
1.7  
1.15  
GND−0.3  
V
CLK  
V
PUP  
SCL, SDA, /INTA, /INTB pins  
FOE pin  
R
PUP  
Operating temperature  
TOPR  
No condensation  
+25  
+85  
−40  
6. Frequency Characteristics  
GND = 0 V  
Item  
Symbol  
Condition  
Rating  
Unit  
AA ; 5 ± 5 ( 1)  
AC ; 0 ± 5 ( 1)  
Ta = +25°C  
DD = 3.0 V  
Ta = +25°C  
DD = 2 V to 5 V  
Ta = −20 °C to +70 °C,  
DD = 3.0 V; +25 °C reference  
Ta = +25 °C  
DD = 2.0 V  
Ta = +25 °C  
DD=3.0 V; first year  
∆ f / f  
× 10−6  
Frequency precision  
V
Frequency/voltage  
characteristics  
Frequency/temperature  
characteristics  
± 1 Max.  
+10 / −120  
1 Max.  
× 10−6 / V  
× 10−6  
f / V  
Top  
V
V
Oscillation start time  
Aging  
t
STA  
s
V
± 5 Max.  
× 10−6 / year  
fa  
V
1) AC rank. Precision gap per month: 13 seconds (excluding offset value)  
7. Electrical Characteristics  
7.1. DC Electrical Characteristics  
7.1.1. DC electrical characteristics (1)  
* Unless otherwise specified, GND = 0 V, VDD = 3 V, Ta = −40 °C to +85 °C  
Item  
Symbol  
Condition  
Min.  
Typ.  
Max.  
Unit  
f
SCL = 0Hz, FOE = GND  
VDD=5 V  
VDD=3 V  
0.60  
1.80  
Current  
consumption (1)  
/INTA, /INTB = VDD  
FOUT; output OFF  
I
DD1  
DD2  
µA  
0.48  
3.0  
1.20  
6.5  
( Output = OPEN )  
SCL = 0Hz  
DD, /INTA, /INTB, FOE = 5.5 V  
f
V
Current  
consumption (2)  
I
µA  
FOUT;32.768 kHz output ON  
( Output = OPEN ; CL= 0 pF )  
High-level  
input voltage  
Low-level  
input voltage  
High-level input  
current  
V
IH  
IL  
OH  
5.5  
0.2 × VDD  
−0.5  
V
V
0.8 × VDD  
GND − 0.3  
SCL, SDA, FOE pins  
DD = 1.7 5.5 V  
V
V
I
mA  
FOUT pin, VOH = VDD − 0.5 V  
I
I
I
OL1  
OL2  
OL3  
0.5  
1.0  
4.0  
mA  
mA  
mA  
FOUT pin, VOL = 0.4 V  
/INTA and /INTB pins, VOL = 0.4 V  
SDA pin, VOL = 0.4 V  
Low-level input  
current  
Input leakage  
current  
I
IL  
1
SCL pin, V  
I
= 5.5 V or GND, VDD = 5.5 V  
−1  
µA  
Page - 3  
ETM10E-04  
RX - 8025 SA NB  
/
7.1.2. DC electrical characteristics (2)  
* Unless otherwise specified, GND = 0 V, VDD = 3 V, Ta = −40 °C to +85 °C  
Item  
Symbol  
Condition  
Min.  
Typ.  
Max.  
Unit  
Input current with pull-down  
resistance  
Output current when OFF  
I
FOE  
OZ  
DETH  
0.3  
1.0  
FOE pin, V  
I
= 5.5 V  
µA  
SDA, /INTA, and /INTB pins  
I
1
−1  
µA  
V
V
O = 5.5 V or GND, VDD = 5.5 V  
High-voltage  
mode  
Power  
supply  
V
1.90  
1.15  
2.10  
1.30  
2.30  
1.45  
V
DD pin, Ta = −30 to +70 °C  
DD pin, Ta = −30 to +70 °C  
detection  
voltage  
Low-voltage  
mode  
V
DETL  
V
V
7.2. AC Electrical Characteristics  
Unless otherwise specified: GND = 0 V, VDD = 1.7 V to 5.5 V, Ta = −40 °C to +85 °C  
Input conditions: VIH = 0.8 × VDD, VIL = 0.2 × VDD, VOH = 0.8 × VDD, VOL = 0.2 ×VDD, CL = 50 pF  
Item  
Symbol Condition  
Min.  
Typ.  
Max.  
Unit  
SCL clock frequency  
SCL clock low time  
SCL clock higt time  
Start condition hold time  
Stop condition setup time  
Start condition setup time  
Recovery time from stop condition  
to start condition  
f
t
t
SCL  
LOW  
HIGH  
400  
kHz  
µs  
µs  
µs  
µs  
µs  
1.3  
0.6  
0.6  
0.6  
0.6  
t
t
t
HD;STA  
SU;STO  
SU;STA  
t
RCV  
62  
µs  
tSU:DAT  
tHD;DAT  
tPL;DAT  
tPZ;DAT  
tR  
Data setup time  
Data hold time  
SDA “L” stable time after falling of SCL  
SDA off stable time after falling of SCL  
Rising time of SCL and SDA (input)  
Falling time of SCL and SDA (input)  
Spike width that can be removed  
with input filter  
200  
0
ns  
ns  
µs  
µs  
ns  
ns  
0.9  
0.9  
300  
300  
tF  
tSP  
50  
ns  
S
Sr  
P
S
SCL  
tSP  
tLOW  
tHIGH  
tHD;STA  
SDA(IN)  
tHD;STA  
tSU;DAT  
tHD;DAT  
tRCV  
tSU;STA  
tSU;STO  
S
START Condition  
STOP condition  
SDA(OUT)  
tPL;DAT  
tPZ;DAT  
P
Sr Re-start condition  
Caution: When accessing this device, all communication from transmitting the start condition to transmitting the stop  
condition after access should be completed within 0.5 seconds.  
If such communication requires 0.5 to 1.0 second or longer, the I2C bus interface is reset by the internal bus  
timeout function. Please see also 8.8.3. Starting and stopping I2C bus communications.  
Page - 4  
ETM10E-04  
RX - 8025 SA NB  
/
8.1. Functional descriptions  
8.1. Overview of Functions  
1) Clock functions  
This function is used to set and read out month, date, day, hour, minute, and second.  
Any (two-digit) year that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year  
2099.  
For details, see "8.2. Description of Registers".  
2) Clock precision adjustment function  
The clock precision can be adjusted forward or back in units of ± 3.05 × 10−6. This function can be used to implement  
a higher-precision clock function, such as by:  
• enabling higher clock precision throughout the year by taking seasonal clock precision adjustments into account in  
advance, or  
• enabling correction of temperature-related clock precision variation in systems that include a temperature detection  
function.  
Note: Only the clock precision can be adjusted. The adjustments have no effect on the 32.768-kHz output from the  
FOUT pin.  
For details, see "8.3. Clock Precision Adjustment Function".  
3) Periodic interrupt function  
In addition to the alarm function, Periodic interrupts can be output via the /INTA pin.  
Select among five Periodic frequency settings: 2 Hz, 1 Hz, 1/60 Hz, hourly, or monthly.  
Select among two output waveforms for periodic interrupts: an ordinary pulse waveform (2 Hz or 1 Hz) or a waveform  
(every second, minute, hour, or month) for CPU-level interrupts that can support CPU interrupts.  
A polling function is also provided to enable monitoring of pin states via registers.  
For details, see "8.4. Periodic Interrupt Function".  
4) Alarm functions  
This module is equipped with two alarm functions (Alarm W and Alarm D) that output interrupt signals to the host at  
preset times. The Alarm W function can be used for day, hour, and minute-based alarm settings, and it outputs  
interrupt signals via the /INTB pin. Multiple day settings can be selected (such as Monday, Wednesday, Friday,  
Saturday, and Sunday). The Alarm D function can be used only for hour or minute-based settings, and it outputs  
interrupt signals via the /INTA pin.  
A polling function is also provided to enable checking of each alarm mode by the host.  
For details on the Alarm W function, see "8.5. Alarm W function" and for the Alarm D function, see "8.6. Alarm D Function".  
5) Oscillation stop detection function, power drop detection function (voltage monitoring function), and  
power-on reset detection function  
The oscillation stop detection function uses registers to record when oscillation has stopped.  
The power drop detection function (supply voltage monitoring function) uses registers to record when the supply  
voltage drops below a specified voltage threshold value. Use registers to specify either of two voltage threshold  
values: 2.1 V or 1.3 V. Voltage sampling is performed once per second in consideration of the module's low current  
consumption.  
While the oscillation stop detection function is useful for determining when clock data has become invalid, the supply  
voltage monitoring function is useful for determining whether or not the clock data is able to become invalid. The  
supply voltage monitoring function can also be used to monitor a battery's supply voltage.  
When these functions are utilized in combination with the power-on reset detection function, they are useful for  
determining whether clock data is valid or invalid when checking for power-on from 0 V or for back-up.  
For details, see "8.7. Detection Functions".  
6) Interface with CPU  
Data is read and written via the I2C bus interface using two signal lines: SCL (clock) and SDA (data).  
Since neither SCL nor SDA includes a protective diode on the VDD side, a data interface between hosts with differing  
supply voltages can still be implemented by adding pull-up resistors to the circuit board.  
The SCL's maximum clock frequency is 400 kHz (when VDD ≥ 1.7 V), which supports the I2C bus's high-speed mode.  
For further description of data read/write operations, see "8.8. Reading/Writing Data via the I2C Bus Interface".  
7) 32.768-kHz clock output  
The 32.768-kHz clock (with precision equal to that of the built-in quartz oscillator) can be output via the FOUT pin.  
Note: The precision of this 32.768-kHz clock output via the FOUT pin cannot be adjusted (even when using the clock  
precision adjustment function).  
Page - 5  
ETM10E-04  
RX - 8025 SA NB  
/
8.2. Description of Registers  
8.2.1. Register table  
note  
Address  
Function  
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0  
ꢀ
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Seconds  
Minutes  
S40  
M40  
ꢀ
S20  
M20  
S10  
M10  
H10  
ꢀ
S8  
M8  
H8  
ꢀ
S4  
M4  
S2  
M2  
S1  
M1  
5
5
5
5
5
ꢀ
ꢀ
H20  
P , /A  
H4  
H2  
H1  
Hours  
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
W4  
D4  
W2  
D2  
W1  
D1  
Weekdays  
Days  
D20  
D10  
MO10  
Y10  
F4  
D8  
MO8  
Y8  
ꢀ
MO4  
Y4  
MO2  
Y2  
MO1  
Y1  
Months  
C
Y80  
TEST  
ꢀ
4, 5  
Y20  
F5  
Years  
Y40  
F6  
−
F3  
F2  
F1  
F0  
Digital Offset  
Alarm_W ; Minute  
Alarm_W ; Hour  
Alarm_W ; Weekday  
Alarm_D ; Minute  
Alarm_D ; Hour  
Reserved  
4
WM40 WM20 WM10 WM8  
WH20  
WM4  
WH4  
WM2  
WH2  
WM1  
WH1  
5
ꢀ
ꢀ
ꢀ
ꢀ
WH10 WH8  
5
WP,/A  
WW6 WW5 WW4 WW3 WW2 WW1 WW0  
5
DM40 DM20 DM10  
DH20  
DM8  
DH8  
DM4  
DH4  
DM2  
DH2  
DM1  
DH1  
5
ꢀ
ꢀ
DH10  
5
DP , /A  
Reserved  
/CLEN2 TEST  
3
WALE DALE  
VDSL VDET  
CT2  
CT1  
CT0  
Control 1  
/12 , 24  
/XST  
1, 2, 6  
1, 6  
PON /CLEN1 CTFG WAFG DAFG  
Control 2  
Caution points:  
The PON bit is a power-on reset flag bit.  
1.  
The PON bit is set to "1" when a reset occurs, such as during the initial power-up or when recovering from a  
supply voltage drop. At the same time, all bits in the Control 1 and Control 2 registers except for the PON and /  
XST bits are reset to "0".  
Note: At this point, all other register values are undefined, so be sure to perform a reset before using the module.  
Also, be sure to avoid entering incorrect date and time data, as clock operations are not guaranteed when  
the time data is incorrect.  
The TEST bit is used by the manufacturer for testing. Be sure to set "0" for this bit.  
2.  
3.  
Read data from address-D are always "00", and The write access to address-D are invalid.  
4. All bits marked with a " 0 " in the above table should be set as "0". Their value when read will be "0".  
5. All bits marked with " " are read-only bits. Their value when read is always "0".  
ꢀ
When PON bit became 1 because power-on reset function worked, /CLEN1 and /CLEN2 bit become 0.  
When /CLEN1 and /CLEN2 bit become 1 even if FOE input is "H", FOUT output stops.  
6.  
FOE  
input  
/CLEN1  
bit  
/CLEN2  
bit  
FOUT  
output  
L
Χ
0
0
1
1
Χ
0
1
0
1
OFF ( " L " )  
32.768 kHz  
32.768 kHz  
32.768 kHz  
OFF ( " L " )  
H
' Χ ' Don't care.  
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8.2.2. Time counter (Reg 0 to 2)  
Address  
0
Function  
bit 7  
bit 6  
S40  
bit 5  
S20  
bit 4  
S10  
bit 3  
S8  
bit 2  
S4  
bit 1  
S2  
bit 0  
S1  
ꢀ
Seconds  
Minutes  
Hours  
ꢀ
ꢀ
1
2
M40  
M20  
M10  
H10  
M8  
H8  
M4  
H4  
M2  
H2  
M1  
H1  
H20  
P, /A  
ꢀ
• The time counter counts seconds, minutes, and hours.  
• The data format is BCD format (except during 12-hour mode)  
"0101 1001" it indicates 59 seconds.  
.
For example, when the "seconds" register value is  
Note with caution that writing non-existent time data may interfere with normal operation of the time counter.  
1) Second counter  
Address  
0
Function  
Seconds  
bit 7  
bit 6  
S40  
bit 5  
S20  
bit 4  
S10  
bit 3  
S8  
bit 2  
S4  
bit 1  
S2  
bit 0  
S1  
ꢀ
• This second counter counts from "00" to "01," "02," and up to 59 seconds, after which it starts again from  
00 seconds.  
• When a value is written to the second counter, the internal counter is also reset to zero in less than one  
second.  
2) Minute counter  
Address  
Function  
Minutes  
bit 7  
bit 6  
M40  
bit 5  
M20  
bit 4  
M10  
bit 3  
M8  
bit 2  
M4  
bit 1  
M2  
bit 0  
M1  
ꢀ
1
• This minute counter counts from "00" to "01," "02," and up to 59 minutes, after which it starts again from 00  
minutes.  
3) Hour counter  
Address  
Function  
Hours  
bit 7  
bit 6  
bit 5  
bit 4  
H10  
bit 3  
H8  
bit 2  
H4  
bit 1  
H2  
bit 0  
H1  
H20  
P , /A  
ꢀ
ꢀ
2
• The hour counter counts hours, and its clock mode differs according to the value of its /12,24 bit.  
• During 24-hour clock operation, bit 5 functions as H20 (two-digit hour display). During 12-hour clock  
operation, bit 5 functions as an AM/PM indicator ("0" indicates AM and "1" indicates PM).  
Address 2 (Hours register) data [h] during 24-hour and  
12-hour clock operation modes  
/12,24 bit  
Description  
24-hour clock 12-hour clock  
24-hour clock 12-hour clock  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12 ( AM 12 )  
01 ( AM 01 )  
02 ( AM 02 )  
03 ( AM 03 )  
04 ( AM 04 )  
05 ( AM 05 )  
06 ( AM 06 )  
07 ( AM 07 )  
08 ( AM 08 )  
09 ( AM 09 )  
10 ( AM 10 )  
11 ( AM 11 )  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
32 ( PM 12 )  
21 ( PM 01 )  
22 ( PM 02 )  
23 ( PM 03 )  
24 ( PM 04 )  
25 ( PM 05 )  
26 ( PM 06 )  
27 ( PM 07 )  
28 ( PM 08 )  
29 ( PM 09 )  
30 ( PM 10 )  
31 ( PM 11 )  
12-hour  
clock  
0
24-hour  
clock  
1
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8.2.3. Day counter (Reg 3)  
Address  
3
Function  
Days  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
W4  
bit 1  
W2  
bit 0  
W1  
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
• The day counter is a divide-by-7 counter that counts from 00 to 01 and up 06 before starting again from 01.  
• The correspondence between days and count values is shown below.  
Days  
W4  
W2  
W1  
Day  
Remark  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Sunday  
Monday  
Tuesday  
00 h  
01 h  
02 h  
Write / Read  
Wednesday 03 h  
Thursday  
Friday  
Saturday  
−
04 h  
05 h  
06 h  
Write prohibit  
Do not enter a setting for this bit.  
8.2.4. Calendar counter (Reg 4 to 6)  
Address  
4
Function  
Days  
bit 7  
bit 6  
bit 5  
bit 4  
D10  
bit 3  
D8  
bit 2  
D4  
bit 1  
D2  
bit 0  
D1  
ꢀ
ꢀ
D20  
ꢀ
ꢀ
5
6
Months  
Years  
C
MO10  
Y10  
MO8  
Y8  
MO4  
Y4  
MO2  
Y2  
MO1  
Y1  
Y80  
Y40  
Y20  
• The auto calendar function updates all dates, months, and years from January 1, 2001 to December 31, 2099.  
• The data format is BCD format. For example, a date register value of "0011 0001" indicates the 31st.  
Note with caution that writing non-existent date data may interfere with normal operation of the calendar counter.  
1) Date counter  
Address  
4
Function  
Days  
bit 7  
bit 6  
bit 5  
D20  
bit 4  
D10  
bit 3  
D8  
bit 2  
D4  
bit 1  
D2  
bit 0  
D1  
ꢀ
ꢀ
• The updating of dates by the date counter varies according to the month setting.  
A leap year is set whenever the year value is a multiple of four (such as 04, 08, 12, 88, 92, or 96).  
Days  
Month  
Date update pattern  
1, 3, 5, 7, 8, 10, or 12  
4, 6, 9, or 11  
February in leap year  
February in normal year  
01, 02, 03 to 30, 31, 01…  
01, 02, 03 to 30, 01, 02…  
01, 02, 03 to 28, 29, 01…  
01, 02, 03 to 28, 01, 02…  
Write / Read  
2) Month counter  
Address  
5
Function  
Months  
bit 7  
C
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
ꢀ
ꢀ
MO10  
MO8  
MO4  
MO2  
MO1  
• The month counter counts from 01 (January), 02 (February), and up to 12 (December), then starts again at  
01 (January).  
Be sure to set a "0" for any bit whose value is shown above as "0". A zero is returned when any of these  
bits is read.  
When an years counter is updated to 00 from 99, a C bit is updated to 1 from 0.  
C is not updated in 0 from 1.  
3) Year counter  
Address  
Function  
Years  
bit 7  
Y80  
bit 6  
Y40  
bit 5  
Y20  
bit 4  
Y10  
bit 3  
Y8  
bit 2  
Y4  
bit 1  
Y2  
bit 0  
Y1  
6
• The year counter counts from 00, 01, 02 and up to 99, then starts again at 00.  
In any year that is a multiple of four (04, 08, 12, 88, 92, 96, etc.), the dates in February are counted from  
01, 02, 03 and up to 29 before starting again at 01.  
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8.2.5. Clock precision adjustment register (Reg 7)  
Address  
7
Function  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
Digital Offset  
(Default)  
TEST  
(0)  
F6  
(0)  
F5  
(0)  
F4  
(0)  
F3  
(0)  
F2  
(0)  
F1  
(0)  
F0  
(0)  
• The binary encoded settings in the seven bits from F6 to F0 are used to set the precision of the clock generated  
from the 32768-Hz internal oscillator up to ±189 × 10−6 in the forward (ahead) or reverse (behind) direction, in  
units of ± 3.05 × 10−6. (Only the clock precision can be adjusted. The 32.768-kHz output from the FOUT pin is  
not affected.)  
• When not using this function, be sure to set "0" for bits F6 to F0.  
TEST is used by the manufacturer for testing. Be sure to write "0" to this bit.  
For details, see "8.3. Clock Precision Adjustment Function".  
8.2.6. Alarm_W register (Reg 8 to A)  
Address  
8
Function  
bit 7  
bit 6  
WM40  
ꢀ
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
ꢀ
Alarm_W ; Minute  
WM20  
WM10  
WM8  
WM4  
WM2  
WM1  
WH20  
WP , /A  
ꢀ
ꢀ
9
Alarm_W ; Hour  
Alarm_W ; Day  
WH10  
WW4  
WH8  
WH4  
WH2  
WH1  
A
WW6  
WW5  
WW3  
WW2  
WW1  
WW0  
• The Alarm W function is used, along with the WALE and WAFG bits, to set alarms for specified day, hour, and  
minute values.  
• When the Alarm_W setting matches the current time, /INTB pin is set to "L" and the WALE bit is set to "1".  
Note: If the current date/time is used as the Alarm_W setting, the alarm will not occur until the counter counts up  
to the current date/time (i.e., an alarm will occur next time, not immediately).  
• During 24-hour clock operation, the "Alarm_W ; Hours" register's bit 5 (WH20, WP, /A) functions as WH20  
(two-digit hour display), and during 12-hour clock operation it functions as an AM/PM indicator.  
• When the Alarm_W function's day values (WW6 to WW0) are all "0" Alarm W does not occur.  
For details, see "8.5. Alarm W Function".  
8.2.7. Alarm_ D register (Reg B and C)  
Address  
B
Function  
bit 7  
bit 6  
DM40  
ꢀ
bit 5  
bit 4  
bit 3  
DM8  
bit 2  
DM4  
bit 1  
DM2  
bit 0  
DM1  
ꢀ
Alarm_D ; Minute  
DM20  
DM10  
DH20  
DP , /A  
ꢀ
C
Alarm_D ; Hour  
DH10  
DH8  
DH4  
DH2  
DH1  
• The Alarm D function is used, along with the DALE and DAFG bits, to set alarms for specified hour and minute  
values.  
• When the Alarm_D setting matches the current time, /INTA pin is set to "L" and the DALE bit is set to "1".  
Note: If the current time is used as the Alarm_D setting, the alarm will not occur until the counter counts up to the  
current time (i.e., an alarm will occur next time, not immediately).  
• During 24-hour clock operation, the "Alarm_D ; Hours" register's bit 5 (DH20, DP, /A) functions as DH20 (two-digit  
hour display), and during 12-hour clock operation it functions as an AM/PM indicator.  
For details, see "8.6. Alarm D Function".  
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8.2.8. Control register 1 (Reg E)  
Address  
E
Function  
bit 7  
bit 6  
DALE /12 , 24  
(0) (0)  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
/CLEN2  
(0)  
Control 1  
(Default)  
WALE  
(0)  
TEST  
(0)  
CT2  
(0)  
CT1  
(0)  
CT0  
(0)  
) The default value is the value that is read (or is set internally) after the PON bit has been set to "1," such as after powering up from 0 V or  
recovering from a supply voltage drop.  
1) WALE bit  
This bit is used to set up the Alarm W function (to generate alarms matching day, hour, or minute settings).  
WALE  
Data  
Description  
Default  
Default  
Default  
0
1
Alarm_W, match comparison operation invalid  
Alarm_W, match comparison operation valid (/INTB = "L" when  
match occurs)  
Write / Read  
For details, see "8.5. Alarm W Function".  
2) DALE bit  
This bit is used to set up the Alarm D function (to generate alarms matching hour or minute settings).  
DALE  
Data  
Description  
0
1
Alarm_D, match comparison operation invalid  
Alarm_D, match comparison operation valid (/INTA = "L" when  
match occurs)  
Write / Read  
For details, see "8.6. Alarm D Function".  
3) /12,24 bit  
This bit is used to select between 12-hour clock operation and 24-hour clock operation.  
/12,24  
Data  
Description  
0
1
12-hour clock  
24-hour clock  
Write / Read  
Be sure to select between 12-hour and 24-hour clock operation before writing the time data.  
See also "3) Hour counter" in section 8.2.4.  
4) /CLEN2 bit  
It combines /CLEN1 bit, and is bit controlling FOUT output.  
When /CLEN1 and /CLEN2 bit become 1 even if FOE input is "H", FOUT output stops.  
If FOUT output is unnecessary, it functions as RAM-bit and is ( FOE="L" )  
When PON bit became 1 because power-on reset function worked, /CLEN1 and /CLEN2 bit become 0.  
5) TEST bit  
This bit is used by the manufacturer for testing. Be sure to write "0" to this bit.  
Be careful to avoid writing a "1" to this bit when writing to other bits.  
TEST  
Data  
Description  
Default  
0
1
Normal operation mode  
Setting prohibited (manufacturer's test mode)  
Write / Read  
6) CT2, CT1, and CT0 bits  
These bits are used to set up the operation of the periodic interrupt function that uses the /INTA pin.  
/INTA pin's output setting  
CT2  
CT1  
CT0  
Waveform mode  
Cycle/Fall timing  
Default  
0
0
0
0
0
0
1
1
0
1
0
1
/INTA = Hi-Z (= OFF)  
/INTA = Fixed low  
2 Hz  
−
−
1)  
(50% duty)  
(50% duty)  
Pulse mode  
Pulse mode  
1)  
1 Hz  
(Synchronous with per-second  
count-up)  
(Occurs when seconds reach ":00")  
(Occurs when minutes and seconds  
reach "00:00")  
2)  
1
1
1
0
0
1
0
1
0
Once per second  
Once per minute  
Once per hour  
Level mode  
2)  
Level mode  
2)  
Level mode  
(Occurs at 00:00:00 on first day of  
month)  
2)  
1
1
1
Once per month  
Level mode  
For details, see "8.4. Periodic Interrupt".  
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8.2.9. Control register 2 (Reg F)  
Address  
F
Function  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
/CLEN1 CTFG  
(0) (0)  
bit 2  
bit 1  
bit 0  
Control 2  
(Default)  
VDSL  
(0)  
VDET  
(0)  
/ XST  
(−)  
PON  
(1)  
WAFG  
(0)  
DAFG  
(0)  
1) The default value is the value that is read (or is set internally) after the PON bit has been set to "1," such as after powering up from 0 V or  
recovering from a supply voltage drop.  
2) '"−" indicates undefined status.  
1) VDSL bit  
This bit is used to set the power drop detection function's threshold voltage value.  
VDSL  
Data  
Description  
Sets 2.1 V as the power drop detection function's threshold  
voltage value  
Sets 1.3 V as the power drop detection function's threshold  
voltage value  
Default  
0
Write / Read  
1
For details, see "8.7. Detection Functions".  
2) VDET bit  
This bit indicates the power drop detection function's detection results.  
VDET = "1" once a power voltage drop has occurred.  
VDET  
Data  
Description  
Default  
Default  
Clears the VDET bit to zero, restarts the power drop detection  
operation and sets up for next power drop detection operation  
0
Write  
1
0
1
The writes "1" are invalid.  
Power drop was not detected  
Read  
Power drop was detected  
(result is that bit value is held until cleared to zero)  
For details, see "8.7. Detection Functions".  
3) / XST bit  
This bit indicates the oscillation stop detection function's detection results.  
If a "1" has already been written to this bit, it is cleared to zero when stopping of internal oscillation is detected.  
/ XST  
Data  
Description  
0
The writes "0" are invalid.  
Write  
Sets the oscillation stop detection function as use-enabled and  
sets up for next detection operation  
Oscillation stop was detected  
1
0
1
(result is that bit value is held until a "1" is written)  
Read  
Oscillation stop was not detected  
For details, see "8.7. Detection Functions".  
4) PON bit  
This bit indicates the power-on reset detection function's detection results.  
The PON bit is set (= 1) when the internal power-on reset function operates.  
PON  
Data  
Description  
0
Clears the PON bit to zero and sets up next detection operation  
Write  
1
0
1
The writes "1" are invalid.  
Power-on reset was not detected  
Read  
Default  
Power-on reset was detected  
(result is that bit value is held until cleared to zero)  
When PON = "1" all bits in the Clock Precision Adjustment register and in the Control 1 and Control 2  
registers (except for the PON and / XST bits) are reset to "0". This also causes output from /INTA and  
/INTB pin to be stopped (= Hi-Z).  
For details, see "8.7. Detection Functions".  
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5) /CLEN1 bit  
This bit is controlling FOUT output with /CLEN2 bit.  
When /CLEN1 and /CLEN2 bit set to 1 even if FOE input is "H", FOUT output stops.  
If FOUT output is unnecessary, it functions as RAM-bit and is ( FOE="L" )  
When PON bit became 1 because power-on reset function worked, /CLEN1 and /CLEN2 bit become 0.  
6) CTFG bit  
During a read operation, this bit indicates the /INTA pin's priodic interrupt output status.  
This status can be set as OFF by writing a "0" to this bit when /INTA = " L".  
CTFG  
Data  
Description  
Default  
A "0" can be written only when the periodic interrupt is in level  
mode, at which time the /INTA pin is set to OFF (Hi-z) status.  
(Only when Alarm_D does not match)  
0
Write  
After a "0" is written, the value still becomes "1" again at the  
next cycle.  
1
0
1
The writes "1" are invalid.  
Default  
Periodic interrupt output OFF status; /INTA = OFF (Hi-z)  
Read  
Periodic interrupt output ON status; /INTA = "L"  
For details, see "8.4. Periodic Interrupt Function".  
7) WAFG bit  
This bit is valid only when the WALE bit value is "1". The WAFG bit value becomes "1" when Alarm W has  
occurred.  
The /INTB = "L" status that is set at this time can be set to OFF by writing a "0" to this bit.  
WAFG  
Data  
Description  
Default  
Default  
0
/INTB pin = OFF (Hi-z)  
Write  
1
0
1
The writes "1" are invalid.  
Alarm_W time setting does not match current time  
(This bit's value is always "0" when the WALE bit's setting is "0")  
Alarm_W setting matches current time  
Read  
(Result is that bit value is held until cleared to zero)  
For details, see "8.5. Alarm W Function".  
8) DAFG bit  
This bit is valid only when the DALE bit value is "1". The DAFG bit value becomes "1" when Alarm D has  
occurred.  
The /INTA = "L" status that is set at this time can be set to OFF by writing a "0" to this bit.  
DAFG  
Data  
Description  
Default  
Default  
/INTA pin = OFF (Hi-z) (but only when the periodic interrupt  
output status is OFF)  
0
Write  
1
0
1
The writes "1" are invalid.  
Alarm_D time setting does not match current time  
(This bit's value is always "0" when the DALE bit's setting is "0")  
Alarm_D time setting matches current time  
Read  
(result is that bit value is held until cleared to zero)  
For details, see "8.6. Alarm D function".  
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8.3. Clock Precision Adjustment Function  
The clock precision can be set ahead or behind.  
This function can be used to implement a higher-precision clock function, such as by:  
• enabling higher clock precision throughout the year by taking seasonal clock precision adjustments into  
account in advance, or  
• enabling correction of temperature-related clock precision variation in systems that include a temperature  
detection function.  
Note: Only the clock precision can be adjusted. The adjustments have no effect on the 32.768-kHz output from  
the FOUT pin.  
8.3.1. Related register  
Address  
7
Function  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
Digital Offset  
(Default)  
0
(0)  
F6  
(0)  
F5  
(0)  
F4  
(0)  
F3  
(0)  
F2  
(0)  
F1  
(0)  
F0  
(0)  
) Be sure to set a "0" for any bit whose value is shown above as "0". A zero is returned when any of these bits is read.  
• The binary encoded settings in the seven bits from F6 to F0 are used to set the precision of the clock generated  
from the 32768-Hz internal oscillator up to ±189.1 × 10−6 in the forward (ahead) or reverse (behind) direction, in  
units of ± 3.05 × 10−6.  
1) When not using this function, be sure to set "0" for bits F6 to F0.  
2) This function operates every twenty seconds (at 00 seconds, 20 seconds, and 40 seconds within each  
minute), which changes the cycle of the periodic interrupts that occur via this timing. (See "8.4. Periodic Interrupt  
Function".)  
8.3.2. Adjustment capacity  
1) Adjustment range and resolution  
Adjustment range  
Adjustment resolution  
Internal timing of adjustment  
Once every 20 seconds  
(at "00", "20" and "40" seconds)  
−189.1 x 10−6 to +189.1 x 10−6  
± 3.05 x 10−6  
2) Adjustment amount and adjustment value  
Adjustment amount  
Adjustment data  
bit 7  
0
bit 6  
F6  
bit 5  
F5  
bit 4  
F4  
bit 3  
F3  
bit 2  
F2  
bit 1  
F1  
bit 0  
F0  
(× 10−6  
)
Decimal / Hexadecimal  
+63 / 3F h  
+62 / 3E h  
+61 / 3D h  
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
−189.10  
−186.05  
−183.00  
•
•
•
•
•
•
•
•
•
+4 / 04  
+3 / 03  
+2 / 02 h  
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
−9.15  
−6.10  
−3.05  
OFF  
1
0
/ 01 h  
/ 00 h  
/ 7F h  
/ 7E h  
/ 7D h  
OFF  
+3.05  
+6.10  
+9.15  
−1  
−2  
−3  
•
•
•
•
•
•
•
•
•
+183.00  
+186.05  
+189.10  
OFF  
/ 44 h  
/ 43 h  
/ 42 h  
/ 41 h  
/ 40 h  
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
1
0
1
0
−60  
−61  
−62  
−63  
−64  
OFF  
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/
8.3.3. Adjustment examples  
Example 1) Setting time forward  
Objective) To adjust (advance) the clock precision when FOUT clock output is 32767.7 Hz  
(1) Determine the current amount of variance  
32767.7 Hz → (32767.7 − 32768) / 32768 [ 32768 ] = Reference values  
6
→ −9.16 × 10−  
(2) Calculate the optimum adjustment data (decimal value) relative to the current variance.  
Adjustment data = variance / adjustment resolution  
= −9.16 / 3.05  
≈ −3 (decimal values are rounded down from 4 and up from 5)  
For adjusting forward from a retarded variance, this formula can be corrected using reciprocal numbers, but since this  
product inverts the +/- attributes, this formula can be used as it is.  
(3) Calculate the setting adjustment data (hexadecimal)  
To calculate the setting adjustment data while taking 7-bit binary encoding into account,  
subtract the adjustment data (decimal) from 128 (80h).  
Setting adjustment data = 128 − 3 = 125 (decimal)  
= 80h − 03h = 7Dh (hexadecimal)  
Example 2) Setting time backward  
Objective) To adjust (set back) the clock precision when FOUT clock output is 32768.3 Hz  
(1) Determine the current amount of variance  
32768.3 Hz → (32768.3 − 32768) / 32768 [ 32768 ] = reference values  
6
→ +9.16 × 10−  
(2) Calculate the optimum adjustment data (decimal value) relative to the current variance.  
Adjustment data = (variance / adjustment resolution) + 1  
= (+9.16 / 3.05) + 1  
Add 1 since reference value is 01h  
≈ +4 (decimal values are rounded down from 4 and up from 5)  
For adjusting backward from an advanced variance, this formula can be corrected using reciprocal numbers, but  
since this product inverts the +/- attributes, this formula can be used as it is.  
(3) Calculate the setting adjustment data (hexadecimal)  
The value "4" can be used in hexadecimal as it is (04h).  
Setting adjustment data = 04 h (hexadecimal)  
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/
8.4. Periodic Interrupt Function  
Periodic interrupt output can be obtained via the /INTA pin.  
Select among five periodic-cycle settings: 2 Hz (once per 0.5 seconds), 1 Hz (once per second), 1/60 Hz (once  
per minute), 1/3600 Hz (once per hour), or monthly (on the 1st of each month).  
Select among two output waveforms for periodic interrupts: an ordinary pulse waveform (2 Hz or 1 Hz) or a  
waveform (every second, minute, hour, or month) for CPU-level interrupts that can support CPU interrupts.  
A polling function is also provided to enable monitoring of pin states via registers.  
8.4.1. Related registers  
Address  
E
Function  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
WALE  
(0)  
DALE  
(0)  
/12 , 24  
(0)  
/CLEN2  
(0)  
TEST  
(0)  
Control 1  
(Default)  
Control 2  
(Default)  
CT2  
(0)  
CTFG  
(0)  
CT1  
(0)  
CT0  
(0)  
VDSL  
(0)  
VDET  
(0)  
/ XST  
(−)  
PON  
(1)  
/CLEN1  
(0)  
WAFG  
DAFG  
F
(0)  
(0)  
1) The default value is the value that is read (or is set internally) after the PON bit has been set to "1," such as after powering up from 0 V or  
recovering from a supply voltage drop.  
2) "−" indicates undefined status.  
1) CTFG bit  
During a read operation, this bit indicates the /INTA pin's periodic interrupt output status.  
This status can be set as OFF by writing a "0" to this bit when /INTA = " L". .  
CTFG  
Data  
Description  
Default  
A "0" can be written only when the periodic interrupt is in level  
mode, at which time the /INTA pin is set to OFF (Hi-z) status.  
(Only when Alarm_D does not match)  
0
Write  
After a "0" is written, the value still becomes "1" again at the  
next cycle.  
1
0
1
The writes "1" are invalid.  
Default  
periodic interrupt output OFF status; /INTA = OFF (Hi-z)  
Periodic interrupt output ON status; /INTA = "L"  
Read  
2) CT2, CT1, CT0 bit  
Combinations of these three bits are used to change the /INTA pin's output status.  
/INTA pin's output setting  
CT2  
CT1  
CT0  
Waveform mode  
Cycle / Fall timing  
Default  
0
0
0
0
0
0
1
1
0
1
0
1
/INTA = Hi-z (= OFF)  
/INTA = Fixed low  
−
−
1)  
2 Hz  
(50% duty)  
Pulse mode  
Pulse mode  
1)  
1 Hz  
(50% duty)  
Once per  
second  
Once per  
minute  
(Synchronous with per-second  
count-up)  
2)  
1
1
1
1
0
0
1
1
0
1
0
1
Level mode  
2)  
(Occurs when seconds reach ":00")  
Level mode  
(Occurs when minutes and seconds  
reach "00:00")  
(Occurs at 00:00:00 on first day of  
month)  
2)  
Once per hour  
Level mode  
Once per  
month  
2)  
Level mode  
The /INTA pin goes low ("L") when the Alarm_D function operates, but you can prevent that effect by  
setting "0" for CT2, CT1, and CT0 to stop this function.  
See the next page's description of pulse mode/level mode waveforms.  
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/
8.4.2. Mode-specific output waveforms  
1) Pulse mode  
A 2-Hz or 1-Hz clock pulse is output.  
The relation between the clock pulse and the count operation is shown below.  
CTFG bit  
/INTA pin  
92ꢀs (approx)  
(Count up seconds)  
Overwrite seconds counter  
Note 1: As is shown in the above diagram, the seconds register's count up operation occurs approximately  
92 ꢀs after the falling edge of the /INTA output. Therefore, if the clock's value is read immediately  
after the output's falling edge, the read clock value may appear to be about one second slower than  
the RTC module's clock value.  
Note 2: When the seconds counter is overwritten, the counter for time values under one second is also  
reset, which causes the /INTA level to go low ("L") again.  
Note 3: When using the clock precision adjustment function, the periodic interrupt's cycle changes once  
every 20 seconds.  
During pulse mode:  
The period during which the output pulse is low can be adjusted backward or forward up to  
±3.784 msec.  
(For example, the duty for the 1-Hz setting can be adjusted  
±0.3784% from 50%.)  
2) Level mode  
Select among four interrupt cycles: one second, one minute, one hour, or one month.  
Counting up of seconds occurs in sync with the falling edge of the interrupt output. The following is a timing  
chart when a one-second interrupt cycle has been set.  
CTFG bit  
/INTA pin  
Write 0 to CTFG  
(Count up seconds)  
Write 0 to CTFG  
(Count up seconds) (Count up seconds)  
Note: When using the clock precision adjustment function, the periodic interrupt's cycle changes once every  
20 seconds.  
During level mode  
A one-second period can be adjusted backward or forward up to ±3.784 msec.  
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/
8.5. Alarm W function  
The Alarm W function generates interrupt signals (output via the /INTB pin) that correspond to specified days,  
hours, and minutes.  
For description of the Alarm D function, which supports only hour and minute data, see "8.6. Alarm D Function".  
Multiple day settings can be selected (such as Monday, Wednesday, Friday, Saturday, and Sunday).  
A polling function is also provided to enable checking of each alarm mode by the host.  
8.5.1. Related registers  
Address  
Function  
Minutes  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
ꢀ
1
2
M40  
M20  
M10  
M8  
M4  
M2  
M1  
H20  
P, /A  
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Hours  
Days  
H10  
H8  
H4  
H2  
H1  
ꢀ
ꢀ
ꢀ
3
8
9
A
E
F
W4  
W2  
W1  
Alarm_W ; Minute  
Alarm_W ; Hour  
Alarm_W ; Day  
WM40  
WM20  
WM10  
WH10  
WW4  
WM8  
WH8  
WW3  
WM4  
WH4  
WW2  
WM2  
WH2  
WW1  
WM1  
WH1  
WW0  
WH20  
WP, /A  
ꢀ
WW6  
WW5  
DALE  
(0)  
/CLEN2  
( 0 )  
TEST  
( 0 )  
CT2  
(0)  
CT1  
(0)  
CT0  
(0)  
Control 1  
(Default)  
WALE  
(0)  
/12, 24  
(0)  
VDSL  
VDET  
(0)  
/ XST  
PON  
( 1 )  
/CLEN1  
( 0 )  
CTFG  
(0)  
DAFG  
(0)  
Control 2  
(Default)  
WAFG  
(0)  
(0)  
(−)  
1) The default value is the value that is read (or is set internally) after the PON bit has been set to "1," such as after powering up from 0 V or  
recovering from a supply voltage drop.  
2) " " indicates write-protected bits. A zero is always read from these bits.  
○
3) "−" indicates undefined status.  
• When the Alarm_W setting matches the current time, /INTB pin is set to "L" and the WALE bit is set to "1".  
Note: If the current date/time is used as the Alarm_W setting, the alarm will not occur until the counter counts up  
to the current date/time (i.e., an alarm will occur next time, not immediately).  
• During 24-hour clock operation, the "Alarm_W ; Hours" register's bit 5 (WH20, WP, /A) functions as WH20  
(two-digit hour display), and during 12-hour clock operation it functions as an AM/PM indicator.  
• When the Alarm_W function's day values (WW6 to WW0) are all "0" Alarm W does not occur.  
1) WALE bit  
This bit is used to set up the Alarm W function (to generate alarms matching day, hour, or minute settings).  
WALE  
Data  
Description  
Default  
0
1
Alarm_W, match comparison operation invalid  
Alarm_W, match comparison operation valid (/INTB = "L" when  
match occurs)  
Write / Read  
When using the Alarm W function, first set this WALE bit value as "0," then stop the function. Next, set  
the day, hour, minute, and the WAFG bit. Finally, set "1" to the WALE bit to set the Alarm W function as  
valid. The reason for first setting the WALE bit value as "0" is to prevent /INTB = "L" output in the event  
that a match between the current time and alarm setting occurs while the alarm setting is still being made.  
2) WAFG bit  
This bit is valid only when the WALE bit value is "1". When a match occurs between the Alarm_W setting and  
the current time, the WAFG bit value becomes "1" approximately 61 µs afterward. (There is no effect when the  
WALE bit becomes "0".)  
The /INTB = "L" status that is set at this time can be set to OFF by writing a "0" to this bit.  
WAFG  
Data  
Description  
Default  
Default  
0
/INTB pin = OFF (Hi-z)  
Write  
Setting prohibited (do not set this bit value, even though it has no  
effect)  
Alarm_W time setting does not match current time  
(This bit's value is always "0" when the WALE bit's setting is "0")  
Alarm_W setting matches current time  
1
0
1
Read  
(Result is that bit value is held until cleared to zero)  
When a "0" is written to the WAFG bit, provisionally the WAFG bit value is "0" and the /INTB pin status is  
OFF (Hi-z). However, as long as the WALE bit value is "1" the Alarm W function continues to operate, and  
Alarm W occurs again the next time the same specified time arrives. You can stop Alarm W from  
occurring by writing "0" to the WALE bit to set this function as invalid.  
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/
3) /12, 24 bit  
This bit is used to select between 12-hour clock operation and 24-hour clock operation.  
Address 2 (Hours register) data [h] during 24-hour and  
12-hour clock operation modes  
/12,24  
Data  
Description  
24-hour clock 12-hour clock  
24-hour clock 12-hour clock  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12 ( AM 12 )  
01 ( AM 01 )  
02 ( AM 02 )  
03 ( AM 03 )  
04 ( AM 04 )  
05 ( AM 05 )  
06 ( AM 06 )  
07 ( AM 07 )  
08 ( AM 08 )  
09 ( AM 09 )  
10 ( AM 10 )  
11 ( AM 11 )  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
32 ( PM 12 )  
21 ( PM 01 )  
22 ( PM 02 )  
23 ( PM 03 )  
24 ( PM 04 )  
25 ( PM 05 )  
26 ( PM 06 )  
27 ( PM 07 )  
28 ( PM 08 )  
29 ( PM 09 )  
30 ( PM 10 )  
31 ( PM 11 )  
12-hour  
clock  
0
Write / Read  
24-hour  
clock  
1
Be sure to select between 12-hour and 24-hour clock operation before writing the time data.  
4) Day setting  
The following table shows the correspondence between the current day (W4, W2, W1) and the Alarm_W day  
(WW6 to WW0). Be sure to set a "1" to the Alarm_W day when the alarm will occur. (An alarm will not occur for  
any day that has a "0" setting.)  
It is possible to enter settings for several days at the same time, in which case be sure to set a "1" for each day  
(among WW6 to WW0) in which an alarm will occur.  
Function  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
□
Alarm_W ; Day  
WW6  
WW5  
WW4  
WW3  
WW2  
WW1  
WW0  
Wednesday  
Thursday  
(1, 0, 0)  
Target day(s)  
(W4,W2,W1)  
Saturday Friday  
(1, 1, 0) (1, 0, 1)  
Tuesday Monday Sunday  
(0, 1, 0) (0, 0, 1) (0, 0, 0)  
−
(0, 1, 1)  
8.5.2. Alarm setting examples  
Examples of settings for alarm usage are shown below.  
Alarm_W  
; Minute  
Alarm_W  
; Day  
Alarm_W  
; Hour  
Minute  
(hexadecimal)  
Day setting  
Hour (hexadecimal)  
Alarm setting (example)  
WW WW WW WW WW WW WW  
24-hour  
clock  
12-hour  
clock  
12- & 24-hour  
clock  
6
5
4
3
2
1
0
Sat Fri Thu Wed Tue Mon Sun  
Every day  
Every day  
Every day  
Mon to Fri  
Sunday  
at 00:00 AM  
at 01:30 AM  
at 11:59 AM  
at 12:00 PM  
at 01:30 PM  
at 11:59 PM  
1
1
1
0
0
0
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
1
0
1
1
1
1
0
1
0
00h hours 12h hours  
01h hours 01h hours  
11h hours 11h hours  
12h hours 32h hours  
13h hours 21h hours  
23h hours 31h hours  
00h min  
30h min  
59h min  
00h min  
30h min  
59h min  
Mon/Wed/Fri  
8.5.3. WAFG, DAFG and /INTA, /INTB output  
61ꢀs (approx)  
61ꢀs (approx)  
WAFG (DAFG) bit  
/INTA, /INTB pins  
Write "0" to WAFG  
(DAFG)  
Write "0" to WAFG  
(DAFG)  
(Alarm/time match)  
(Alarm/time match)  
(Alarm/time match)  
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/
8.6. Alarm D function  
The Alarm D function generates interrupt signals (output via the /INTA pin) that correspond to specified hours and  
minutes.  
For description of the Alarm W function, which supports only day, hour, and minute data, see "8.5. Alarm W Function".  
A polling function is also provided to enable checking of each alarm mode by the host.  
8.6.1. Related registers  
Address  
Function  
Minutes  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
ꢀ
1
2
M40  
M20  
M10  
M8  
M4  
M2  
M1  
H20  
P , /A  
ꢀ
ꢀ
Hours  
H10  
H8  
H4  
H2  
H1  
ꢀ
ꢀ
B
C
Alarm_D ; Minute  
Alarm_D ; Hour  
DM40  
DM20  
DM10  
DH10  
DM8  
DH8  
DM4  
DH4  
DM2  
DH2  
DM1  
DH1  
DH20  
DP , /A  
ꢀ
WALE  
(0)  
/CLEN2  
( 0 )  
TEST  
( 0 )  
CT2  
(0)  
CT1  
(0)  
CT0  
(0)  
Control 1  
(Default)  
DALE /12 , 24  
E
F
(0)  
VDET  
(0)  
(0)  
/ XST  
(−)  
VDSL  
(0)  
PON  
( 1 )  
/CLEN1  
( 0 )  
CTFG  
(0)  
WAFG  
(0)  
Control 2  
(Default)  
DAFG  
(0)  
1) The default value is the value that is read (or is set internally) after the PON bit has been set to "1," such as after powering up from 0 V or  
recovering from a supply voltage drop.  
2) " " indicates write-protected bits. A zero is always read from these bits.  
○
3) "−" indicates undefined status.  
• When the Alarm_D setting matches the current time, /INTA pin is set to "L" and the DALE bit is set to "1".  
Note: If the current date/time is used as the Alarm_D setting, the alarm will not occur until the counter counts up to  
the current date/time (i.e., an alarm will occur next time, not immediately).  
• During 24-hour clock operation, the "Alarm_D ; Hours" register's bit 5 (DH20, DP, /A) functions as DH20 (two-digit  
hour display), and during 12-hour clock operation it functions as an AM/PM indicator.  
1) DALE bit  
This bit is used to set up the Alarm D function (to generate alarms matching hour or minute settings).  
DALE  
Data  
Description  
Default  
0
1
Alarm_D, match comparison operation invalid  
Alarm_D, match comparison operation valid (/INTA = "L" when  
match occurs)  
Write / Read  
When using the Alarm D function, first set this DALE bit value as "0," then stop the function. Next, set the  
hour, minute, and the DAFG bit. Finally, set "1" to the DALE bit to set the Alarm D function as valid.  
The reason for first setting the DALE bit value as "0" is to prevent /INTA = "L" output in the event that a  
match between the current time and alarm setting occurs while the alarm setting is still being made.  
2) DAFG bit  
This bit is valid only when the DALE bit value is "1". When a match occurs between the Alarm_D setting and the  
current time, the DAFG bit value becomes "1" approximately 61 µs afterward. (There is no effect when the DALE  
bit becomes "0".)  
The /INTA = "L" status that is set at this time can be set to OFF by writing a "0" to this bit.  
DAFG  
Data  
Description  
Default  
Default  
/INTA pin = OFF (Hi-z) (only when periodic interrupt output is  
OFF)  
0
Write  
1
0
1
The writes "1" are invalid.  
Alarm_D time setting does not match current time  
(This bit's value is always "0" when the DALE bit's setting is "0")  
Alarm_D time setting matches current time  
Read  
(result is that bit value is held until cleared to zero)  
When a "0" is written to the DAFG bit, provisionally the DAFG bit value is "0" and the /INTA pin status is  
OFF (Hi-z). However, as long as the DALE bit value is "1" the Alarm D function continues to operate, and  
Alarm D occurs again the next time the same specified time arrives.  
You can stop Alarm D from occurring by writing "0" to the DALE bit to set this function as invalid.  
3) /12,24 bit  
See "/12, 24 bit" in section 8.5.1. 3.  
8.6.2. WAFG, DAFG and /INTA, /INTB output  
See "WAFG, DAFG and /INTA, /INTB output" in section 8.5.3.  
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/
8.7. The various detection Functions  
The detection functions include detection of power-on resets, oscillation stops, and supply voltage drops, as well as  
reporting of detection results in corresponding bits of the address Fh (Control 2) register.  
The status of the power supply, oscillation circuit, and clock can be confirmed by checking these results.  
Note with caution that detection functions may not operate correctly when power flickers occur.  
8.6.1. Related register  
Address  
F
Function  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
/CLEN1  
( 0 )  
CTFG  
(0)  
WAFG  
(0)  
DAFG  
(0)  
Control 2  
(Default)  
VDSL  
(0)  
VDET  
(0)  
/ XST  
(−)  
PON  
(1)  
1) The default value is the value that is read (or is set internally) after the PON bit has been set to "1," such as after powering up from 0 V or  
recovering from a supply voltage drop.  
2) '"−" indicates undefined status.  
8.7.1. Power-on reset detection  
This function detects when a power-on reset occurs. When a power-on reset is detected, the PON bit value becomes  
"1".  
A reset is detected when a power-on from 0 V has occurred, including when the power-on reset from 0 V occurred  
due to a supply voltage drop.  
1) PON bit  
This bit indicates the detection results when a power-on reset has occurred.  
The power-on reset function operates when a power-on from 0 V has occurred, including when a power-on reset  
from 0 V occurred due to a supply voltage drop. When this function operates, the PON bit value becomes "1".  
The /XST and VDET bits can be used in combination to determine the valid/invalid status of the clock and  
calendar data.  
PON  
Data  
Description  
0
Clears PON bit to zero and sets up for next detection operation  
Write  
1
0
1
The writes "1" are invalid.  
Power-on reset was not detected  
Read  
Default  
Power-on reset was detected  
(result is that bit value is held until cleared to zero)  
When PON = "1" the clock precision adjustment register, Control register 1, and Control register 2 (except  
for PON and /XST) are reset and cleared to "0". This stops (sets Hi-Z for) output from the /INTA and  
/INTB pins.  
2) Status of other bits when power-on reset is detected  
• Internal initialization status during a power-on reset  
Address  
7
Function  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
Digital Offset  
(Default)  
0
(0)  
F6  
(0)  
F5  
(0)  
F4  
(0)  
F3  
(0)  
F2  
(0)  
F1  
(0)  
F0  
(0)  
E
F
Control 1  
(Default)  
Control 2  
(Default)  
WALE  
(0)  
VDSL  
(0)  
DALE  
(0)  
VDET  
(0)  
/12, 24 /CLEN2 TEST  
CT2  
(0)  
CT1  
(0)  
WAFG  
(0)  
CT0  
(0)  
DAFG  
(0)  
( 0 )  
( 0 )  
(0)  
/ XST  
(−)  
PON  
( 1 )  
/CLEN1 CTFG  
( 0 )  
(0)  
1) The default value is the value that is read (or is set internally) after the PON bit has been set to "1," such  
as after powering up from 0 V or recovering from a supply voltage drop.  
2) " −" indicates undefined status.  
3) At this point, all other register bits are undefined, so be sure to perform a reset before using the module.  
Also, be sure to avoid entering incorrect date and time data, as clock operations are not guaranteed  
when the time data is incorrect.  
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/
8.7.2. Oscillation stop detection  
This function detects when internal oscillation has stopped. When an oscillation stop is detected, the /XST bit value  
becomes "0".  
If a "1" has already been written to the /XST bit, the /XST bit is cleared to zero when stopping of  
internal oscillation is detected, so this function can be used to determine whether or not an oscillation stop has  
occurred previously, such as after recovery from a backup.  
1) / XST bit  
This bit indicates the oscillation stop detection function's detection results.  
/ XST  
Data  
Description  
0
The writes "0" are invalid.  
Write  
Sets the oscillation stop detection function as use-enabled and  
sets up for next detection operation  
Oscillation stop was detected  
1
0
1
(result is that bit value is held until a "1" is written)  
Read  
Oscillation stop was not detected  
2) Caution points  
To prevent detection errors during operation of the oscillation stop  
detection function, be sure to prevent stops due to VDD power flicker and  
prevent application of voltage exceeding the maximum rated voltage to  
any pin.  
Example of voltage fluctuation that  
makes oscillation stop hard to detect  
In particular, fluctuation in the supply voltage may occur as shown in the  
figure at right, such as when a back-up battery is used. If this occurs,  
internal data may be lost even when the / XST bit value has not changed  
from "1" to "0" so be sure to avoid any input that contains large amounts  
of chattering.  
V
DD  
8.7.3. Voltage drop detection  
This function detects when a voltage drop occurs. Detection of a voltage drop changes the VDET bit value to "1".  
The threshold voltage value for detection can be set via the VDSL bit as 2.1 V or 1.3 V.  
1) VDSL bit  
This bit is used to set the power drop detection function's threshold voltage value.  
VDSL  
Data  
Description  
Sets 2.1 V as the power drop detection function's threshold  
voltage value  
Sets 1.3 V as the power drop detection function's threshold  
voltage value  
Default  
0
Write / Read  
1
2) VDET bit  
This bit indicates the power drop detection function's detection results. VDET = "1" once a power voltage drop  
has occurred. This detection operation is then stopped and the bit value (1) is held.  
VDET  
Data  
Description  
Default  
Clears the VDET bit to zero, restarts the power drop detection  
operation and sets up for next power drop detection operation  
0
Write  
1
0
1
The writes "1" are invalid.  
Default  
Power drop was not detected  
Read  
Power drop was detected  
(result is that bit value is held until cleared to zero)  
3) Caution points  
To reduce current  
consumption while  
monitoring the supply  
VDD  
2.1 V or 1.3 V  
voltage, the supply voltage  
monitor circuit samples for  
only 7.8 ms during each  
second, as shown at right.  
Sampling is stopped once  
the VDET bit = "1". (Clear  
the VDET bit to zero to  
resume operation of the  
detection function.)  
7.8 ms  
PON  
Internal initialization  
period (1 to 2 s)  
1 s  
Sampling for supply  
voltage monitoring  
VDET  
(D6 in address Fh)  
Write 0 to  
VDET  
Write 0 to PON  
& VDET  
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/
8.7.4. Estimation of status based on detection results  
The power supply status and clock status can be confirmed by reading the detection results indicated by the PON,  
/XST, and VDET bits.  
The following are status estimates based on various combinations of detection results.  
Address F h  
Estimated status  
Control 2 Register  
bit 4  
bit 5  
bit 6  
Status of power supply and  
oscillation circuit  
Status of clock and backup  
PON / XST VDET  
• No supply voltage drop,  
but oscillation has  
stopped.  
• Clock abnormality has occurred → Initialization is  
required  
0
0
0
Clock has stopped temporarily, possibly due to  
condensation.  
• Supply voltage has  
dropped and oscillation  
has stopped.  
• Clock abnormality has occurred → Initialization is  
required  
Clock has stopped, perhaps due to drop in backup  
power supply.  
• Normal status.  
0
0
0
0
1
1
1
0
1
• Normal status.  
• Supply voltage has  
dropped but oscillation  
continues.  
• Clock is normal, but an abnormality exists in the power  
supply.  
Backup power supply may have dropped to a  
hazardous level.  
• Supply voltage has  
dropped to 0 V.  
• Initialization is required regardless of the clock status  
and whether or not a voltage drop has occurred.  
Initialization is required due to bits that are reset  
when PON = "1".  
Χ
Χ
1
1
0
1
• Power supply flickering is  
likely.  
The example shown above is when a "1" has already been written to /XST.  
Threshold voltage ( 2.1 V or 1.3 V )  
Supply voltage  
32768-Hz oscillation  
Normal voltage detector  
Power-on reset (PON)  
Oscillation stop detection  
(/XST)  
Supply voltage monitor  
(VDET)  
Internal initialization  
period (1 to 2 s)  
PON, VDET←0  
/XST←1  
VDET←0  
/XST←1  
Internal initialization  
period (1 to 2 s)  
PON,VDET←0  
/XST←1  
Note  
When a crystal oscillation is stopping, RX-8035 cannot output ACK signal in I2C access.  
Therefore, In initial-power-ON, please access RX-8035, after crystal oscillation started.  
Internal crystal start-up time are 1sec. (Max.)  
At initial-power-on, please start access after fixed waiting time.  
Or retry repeated access to RX8025 till ACK output from RX8025 with time-out processing.  
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2
8.8. Reading/Writing Data via the I C Bus Interface  
8.8.1. Overview of I2C-BUS  
The I2C bus supports bi-directional communications via two signal lines: the SDA (data) line and SCL (clock) line. A  
combination of these two signals is used to transmit and receive communication start/stop signals, data transfer  
signals, acknowledge signals, and so on.  
Both the SCL and SDA signals are held at high level whenever communications are not being performed. The  
starting and stopping of communications is controlled at the rising edge or falling edge of SDA while SCL is at high  
level. During data transfers, data changes that occur on the SDA line are performed while the SCL line is at low level,  
and on the receiving side the data is captured while the SCL line is at high level. In either case, the data is  
transferred via the SCL line at a rate of one bit per clock pulse. The I2C bus device does not include a chip select pin  
such as is found in ordinary logic devices. Instead of using a chip select pin, slave addresses are allocated to each  
device and the receiving device responds to communications only when its slave address matches the slave address  
in the received data.  
8.8.2. System configuration  
All ports connected to the I2C bus must be either open drain or open collector ports in order to enable AND  
connections to multiple devices.  
SCL and SDA are both connected to the VDD line via a pull-up resistance. Consequently, SCL and SDA are both  
held at high level when the bus is released (when communication is not being performed).  
V
DD  
SDA  
SCL  
Master  
Slave  
Master  
Slave  
Transmitter/  
Receiver  
Transmitter/  
Receiver  
Transmitter/  
Receiver  
Transmitter/  
Receiver  
CPU, etc.  
RX - 8025  
Other I2C bus device  
Any device that controls the transmission and reception of data is defined as a master device and any device that is  
controlled by a master device is defined as a slave device.  
Also, any device that transmits data is defined as a transmitter and any device that receives data is defined as a  
receiver.  
In the case of this RTC module, controllers such as a CPU are defined as master devices and the RTC module is  
defined as a slave device. When a device is used for both transmitting and receiving data, it is defined as either a  
transmitter or receiver depending on these conditions.  
Note  
When a crystal oscillation is stopping, RX-8035 cannot output ACK signal in I2C access.  
Therefore, In initial-power-ON, please access RX-8035, after crystal oscillation started.  
Internal crystal start-up time are 1sec. (Max.)  
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/
8.8.3. Starting and stopping I2C bus communications  
STOP  
RE-START  
START  
SCL  
SDA  
0.5 s ( Max. )  
1) START condition, repeated START condition, and STOP condition  
(1) START condition  
2
• This condition regulates how communications on the I C-BUS are started.  
SDA level changes from high to low while SCL is at high level  
(2) STOP condition  
2
• This condition regulates how communications on the I C-BUS are terminated.  
SDA level changes from low to high while SCL is at high level  
(3) Repeated START condition (RESTART condition)  
• In some cases, the START condition occurs between a previous START condition and the next  
STOP condition, in which case the second START condition is distinguished as a RESTART  
condition. Since the required status is the same as for the START condition, the SDA level  
changes from high to low while SCL is at high level.  
Some important matters when RX8025 is controlled in I2C.  
When a stop condition occurred during communication, SDA of RX8025 is freed to Hi-Z.  
As a result, as for all the reading data after STOP, "1" is received.  
This can cause data error in a system.  
Data every 4 bits are stored to RX-8 025 in writing.  
When writing, Data every 4 bits are stored to RX-8025.  
Therefore, it is written in at the RTC inside to 4 bits (nybble) just before that when a stop condition  
occurs during write-access.  
When update of the clock counters occurs during serial communication, the error that read/write data  
become false setting occurs.  
Therefore, update of a clock counter of RX8025 is stopped temporarily to prevent this error when  
RX8025 receives a start condition.  
A update of clock counter is revised , afterwards when RX8025 receives a stop condition.  
And clock of RX8025 is started again immediately.  
However, for example, a RX8025 time continues stopping when STOP is not transmitted by power  
supply troubles of a host.  
To evade this problem, RX8025 re-start counters of clock, when a stop-condition is not received even if  
2Hz (0.5 seconds) pulse two times occurs at inside counter of RX-8025.  
And I2C interface is reset.  
As a result, SDA becomes Hi-Z, and all the reading data become "1".  
Please consider the following communication conditions to operate this compensation function  
precisely.  
In I2C communication, please complete stop condition from the first start condition within 0.5 second.  
Re-START condition are included in 0.5second.  
When restart occurs, RX-8 025 stops the time once more, and it is it for 2Hz pulse twice waiting.  
Therefore, when restart continued occurring in a short time, clock pause is not released.  
As a result, the time will delay very much.  
And waiting more than 62 s(Min.) is necessary from the transmission of a stop condition to the  
transmission of a next start condition.  
Update of the clock which occurred during I2C communication is corrected in 62us(Min.).  
Therefore RX8025 time delay when this waiting is short.  
This time compensation function of RX8025 is possible only one second.  
STOP  
START  
SCL  
SDA  
62 µs ( Min. )  
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8.8.4. Data transfers and acknowledge responses during I2C-BUS communications  
1) Data transfers  
Data transfers are performed in 8-bit (1 byte) units once the START condition has occurred. There is no limit on  
the amount (bytes) of data that are transferred between the START condition and STOP condition.  
The address auto increment function operates during both write and read operations.  
After address Fh, incrementation goes to address 0h.  
Updating of data on the transmitter (transmitting side)'s SDA line is performed while the SCL line is at low level.  
The receiver (receiving side) captures data while the SCL line is at high level.  
SCL  
SDA  
Data is valid  
Data can be  
when data line is  
changed  
stable  
Note with caution that if the SDA data is changed while the SCL line is at high level, it will be treated as a  
START, RESTART, or STOP condition.  
2) Data acknowledge response (ACK signal)  
When transferring data, the receiver generates a confirmation response (ACK signal, low active) each time an  
8-bit data segment is received. If there is no ACK signal from the receiver, it indicates that normal  
communication has not been established. (This does not include instances where the master device intentionally  
does not generate an ACK signal.)  
Immediately after the falling edge of the clock pulse corresponding to the 8th bit of data on the SCL line, the  
transmitter releases the SDA line and the receiver sets the SDA line to low (= acknowledge) level.  
SCL from Master  
1
2
8
9
SDA from transmitter (sending  
side)  
Release SDA  
SDA from receiver (receiving  
side)  
Low active  
ACK signal  
After transmitting the ACK signal, if the Master remains the receiver for transfer of the next byte, the SDA is  
released at the falling edge of the clock corresponding to the 9th bit of data on the SCL line. Data transfer  
resumes when the Master becomes the transmitter.  
When the Master is the receiver, if the Master does not send an ACK signal in response to the last byte sent  
from the slave, that indicates to the transmitter that data transfer has ended. At that point, the transmitter  
continues to release the SDA and awaits a STOP condition from the Master.  
8.8.5. Slave address  
The I2C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a  
chip select pin, slave addresses are allocated to each device.  
All communications begin with transmitting the [START condition] + [slave address (+ R/W specification)]. The  
receiving device responds to this communication only when the specified slave address it has received matches its  
own slave address.  
Slave addresses have a fixed length of 7 bits. This RTC's slave address is [ 0110 010 ].  
An R/W bit ("*" above) is added to each 7-bit slave address during 8-bit transfers.  
Slave address  
R / W bit  
Transfer data  
bit 7  
0
bit 6  
1
bit 5  
bit 4  
0
bit 3  
bit 2  
1
bit 1  
0
bit 0  
Read  
Write  
65 h  
64 h  
1 (= Read)  
0 (= Write)  
1
0
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/
8.8.6. I2C bus's basic transfer format  
• The write/read steps are illustrated below.  
Master is transmitter (sending side),  
RTC is receiver (receiving side)  
START condition,  
sent by Master  
Confirmation response from  
Master  
S
Sr  
P
A
/A  
A
RESTART condition,  
sent by Master  
Master does not respond  
Master is receiver (receiving side)  
RTC is transmitter (sending side)  
､
STOP condition,  
sent by Master  
Confirmation response from  
RTC  
1) Write via I2C bus  
• The steps for writing via the I2C bus are shown below.  
bit  
bit  
6
bit  
5
bit  
4
bit  
3
bit  
2
bit  
1
bit  
0
Address setting  
0 h F h 1)  
Transfer mode  
0 h 1)  
Slave address (7 bits)  
S
A
A
A
P
7
Write  
0
(
(
0
1
1
0
0
1
0
Address + transfer mode specification  
Write data  
Slave address + write specification  
1) Specifies the write start address.  
2) Specifies the write mode (= 0h fixed).  
2) Read via I2C bus  
(1) Standard read method for I2C bus  
• The steps for standard reading of the I2C bus are shown below.  
Standard Read mode  
Transfer mode setting = 0h  
Address setting  
0 h F h  
Transfer mode  
Slave address (7 bits)  
S
A
A
Write  
0
•
0
0
0
0
0
1
1
0
0
1
0
Address and transfer mode settings  
Slave address + write specification  
1) Specifies the read start address.  
2) Specifies the Standard Read  
mode (= 0h)  
This "write" is the writing of the read  
start address, which occurs during a  
read operation.  
bit  
7
bit  
6
bit  
5
bit  
4
bit  
3
bit  
2
bit  
1
bit  
0
bit  
7
bit  
6
bit  
5
bit  
4
bit  
3
bit  
2
bit  
1
bit  
0
Slave address (7 bits)  
Sr  
A
A
/A  
P
Read  
0
1
1
0
0
1
0
1
R
e
s
t
a
r
Data read (1)  
Data read (2)  
Slave address + read specification  
N
o
Data is read from the specified  
start address.  
Address auto incrementation function  
is used to add one to the last address  
read to set the start address for the  
next data to be read.  
Indicates next byte will be read.  
A
C
K
t
(2) Simplified read method  
• This RTC module also provides a special read method that uses fewer read steps.  
Simplified Read mode  
Address setting  
0 h F h  
Slave address (7 bits)  
Transfer mode  
S
A
A
Transfer mode setting = 4h  
•
Write  
0
0
1
0
0
0
1
1
0
0
1
0
Address and transfer mode settings  
Slave address + write specification  
1) Specifies the read start address.  
2) Specifies the Simplified  
Read mode (= 4h)  
This "write" is the writing of the read  
start address, which occurs during a  
read operation.  
bit  
7
bit  
6
bit  
5
bit  
4
bit  
3
bit  
2
bit  
1
bit  
0
bit  
7
bit  
6
bit  
bit  
4
bit  
3
bit  
2
bit  
1
bit  
0
A
/A  
P
5
Data read (1)  
Data read (2)  
N
o
Data is read from the specified  
start address.  
Address auto incrementation function  
is used to add one to the last address  
read to set the start address for the  
next data to be read.  
A
C
K
(3) Read method from address Fh, with no specified start address for read operation  
• Only when reading from address Fh (Fh → 0h → 1h → 2h, etc.) can a read operation be performed  
without specifying the read start address or the transfer mode.  
bit  
7
bit  
6
bit  
5
bit  
4
bit  
3
bit  
2
bit  
1
bit  
0
bit  
7
bit  
6
bit  
5
bit  
4
bit  
3
bit  
2
bit  
1
bit  
0
Slave address (7 bits)  
S
A
A
/A  
P
Read  
1
0
1
1
0
0
1
0
N
o
Data read (1)  
Data read (2)  
Slave address + read specification  
Since no address is specified, data is  
read from address Fh.  
The address auto incrementation  
function is used to read data from  
address Fh + 1 (= 0h).  
Indicates next byte will be read.  
A
C
K
The above steps are an example of transfers of one or two bytes only. There is no limit to the number of bytes  
transferred during actual communications. (However, the transfer time must be no longer than 0.5 seconds and  
access to the Address Dh (Reserved) register is prohibited.)  
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8.9. External Connection Example  
D 1  
Note  
4.7 µF  
V
DD  
Schottky  
Barrier  
Diode  
+
RX - 8025  
DD  
V
OPEN  
TEST  
SCL  
0.1 µF  
SDA  
/ INTA  
/ INTB  
FOE  
FOUT  
GND  
Note : Pull-up resistor connections.  
• SCL and SDA  
Connect to the system-power-supply .  
• / INTA and / INTB  
When , uses these interrupt signals at battery backup, connect these pins to backup power supply.  
Note : Use a secondary cell or lithium cell. A diode is not required when using a secondary cell.  
When using a lithium cell, be sure to use a diode. Contact the battery manufacturer for  
details regarding applied resistance values.  
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9. External Dimensions / Marking Layout  
9.1. External Dimensions  
RX-8025 SA (SOP-14pin)  
• External dimensions  
• Recommended soldering  
10.1  
±
0.2  
0° - 10°  
#14  
#8  
1.4  
5.4  
1.4  
5.0 7.4  
±
0.2  
0.1  
0.6  
#1  
#7  
0.15  
1.27  
0.7  
0.05  
Min.  
1.27 × 6 = 7.62  
3.2  
±
0.35  
1.27 1.2  
Unit : mm  
The cylinder of the crystal oscillator can be seen in this area ( back and front ),  
but it has no affect on the performance of the device.  
RX-8025 NB (SON-22pin)  
• External dimensions  
• Soldering pattern  
6.3 Max.  
0.25 0.75  
#14  
#22  
#14  
#22  
#22  
0.7  
#14  
0.25 0.5  
#1  
#11  
0.7  
#1  
#11  
#11  
#1  
P 0.5 × 10 = 5.0  
5.25  
0.2  
0.5  
Unit : mm  
0.1  
1)  
The cylinder of the crystal oscillator can be seen in this area ( back and front ),  
but it has no affect on the performance of the device.  
2)  
In this area, At a parts side of electronic base, you must not do layout any signal line.  
9.2. Marking Layout  
RX - 8025 SA (SOP-14pin)  
Type  
Logo  
R 8025  
E A123B  
Production lot  
RX - 8025 NB (SON-22pin)  
Type  
Logo  
R8025  
E A123B  
Production lot  
The layout shown above is a simplified drawing of the seal and label. Details such as the fonts, sizes, and positioning of  
label contents are not necessarily as shown.  
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/
10. Reference Data  
(1) Example of frequency and temperature characteristics  
[Finding the frequency stability]  
T = +25 C Typ.  
θ
°
10-6  
= -0.035 10-6 Typ.  
×
α
×
1. Frequency and temperature characteristics can be  
0
approximated using the following equations.  
2
∆f  
T
= α (θ  
T - θX)  
: Frequency deviation in any  
temperature  
: Coefficient of secondary temperature  
(−0.035±0.005) × 10-6 / °C2  
: Ultimate temperature (+25±5 °C)  
: Any temperature  
∆f  
T
-50  
-100  
-150  
α
(1 / °C2)  
θ
θ
T
(°C)  
(°C)  
X
-50  
0
+50  
+100  
2. To determine overall clock accuracy, add the frequency  
precision and voltage characteristics.  
Temperature [ C]  
°
∆f/f = ∆f/fo + ∆fT + ∆fV  
: Clock accuracy (stable frequency) in any  
temperature and voltage  
∆f/f  
(2) Example of frequency and voltage characteristics  
Condition :  
: Frequency precision  
: Frequency deviation in any temperature  
: Frequency deviation in any voltage  
∆f/fo  
3 V as reference, Ta=+25 °C  
+ 3  
∆f  
∆f  
T
V
0
3. How to find the date difference  
Date difference = ∆f/f × 86400 (seconds)  
* For example: ∆f/f = 11.574 × 10-6 is an error of  
approximately 1 second/day.  
- 3  
2
3
4
5
DD  
Supply Voltage V [V]  
(3) Current and voltage consumption characteristics  
(3-1) Current consumption when non-accessed (i)  
when FOUT=OFF  
(3-2) Current consumption when non-accessed (ii)  
when FOUT=32.768 kHz  
Condition :  
Condition :  
Ta = +25 °C  
Ta = +25 °C  
fSCL = 0 Hz  
1.0  
10  
f
SCL = 0 Hz  
FOE = GND, /INTA, /INTB = VDD  
FOUT ; Output OFF  
FOE, /INTA, /INTB = VDD  
FOUT ; 32.768 kHz output ON  
CL=30 pF  
0.5  
5
CL=0 pF  
5
2
3
4
5
2
3
4
Supply Voltage VDD[V]  
Supply Voltage VDD[V]  
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/
11. Application notes  
1) Notes on handling  
This module uses a C-MOS IC to realize low power consumption. Carefully note the following cautions when handling.  
(1) Static electricity  
While this module has built-in circuitry designed to protect it against electrostatic discharge, the chip could still be damaged by a  
large discharge of static electricity. Containers used for packing and transport should be constructed of conductive materials. In  
addition, only soldering irons, measurement circuits, and other such devices which do not leak high voltage should be used with  
this module, which should also be grounded when such devices are being used.  
(2) Noise  
If a signal with excessive external noise is applied to the power supply or input pins, the device may malfunction or "latch up." In  
order to ensure stable operation, connect a filter capacitor (preferably ceramic) of greater that 0.1F as close as possible to the  
power supply pins (between VDD and GNDs). Also, avoid placing any device that generates high level of electronic noise near  
this module.  
* Do not connect signal lines to the shaded area in the figure shown in Fig. 1 and, if possible, embed this area in a GND land.  
(3) Voltage levels of input pins  
When the input pins are at the mid-level, this will cause increased current consumption and a reduced noise margin, and can  
impair the functioning of the device. Therefore, try as much as possible to apply the voltage level close to VDD or GND.  
(4) Handling of unused pins  
Since the input impedance of the input pins is extremely high, operating the device with these pins in the open circuit state can  
lead to unstable voltage level and malfunctions due to noise. Therefore, pull-up or pull-down resistors should be provided for all  
unused input pins.  
2) Notes on packaging  
(1) Soldering heat resistance.  
If the temperature within the package exceeds +260 °C, the characteristics of the crystal oscillator will be degraded and it may  
be damaged. The reflow conditions within our reflow profile is recommended. Therefore, always check the mounting  
temperature and time before mounting this device. Also, check again if the mounting conditions are later changed.  
* See Fig. 2 profile for our evaluation of Soldering heat resistance for reference.  
(2) Mounting equipment  
While this module can be used with general-purpose mounting equipment, the internal crystal oscillator may be damaged in  
some circumstances, depending on the equipment and conditions. Therefore, be sure to check this. In addition, if the mounting  
conditions are later changed, the same check should be performed again.  
(3) Ultrasonic cleaning  
Depending on the usage conditions, there is a possibility that the crystal oscillator will be damaged by resonance during  
ultrasonic cleaning. Since the conditions under which ultrasonic cleaning is carried out (the type of cleaner, power level, time,  
state of the inside of the cleaning vessel, etc.) vary widely, this device is not warranted against damage during ultrasonic  
cleaning.  
(4) Mounting orientation  
This device can be damaged if it is mounted in the wrong orientation. Always confirm the orientation of the device before  
mounting.  
(5) Leakage between pins  
Leakage between pins may occur if the power is turned on while the device has condensation or dirt on it. Make sure the device  
is dry and clean before supplying power to it.  
Fig. 1 : Example GND Pattern  
RX - 8025 SA ( SOP-14pin )  
Fig. 2 : Reference profile for our evaluation of Soldering heat resistance.  
Temperature [ °C ]  
+260 °C Max.  
−1 −5 °C / s  
+1 +5 °C / s  
RX - 8025 NB ( SON-22pin )  
+170 °C  
+220 °C  
+1 +5 °C / s  
100 s  
35 s  
Pre-heating area  
Stable Melting area  
time [ s ]  
In addition, please confirm the Notes of an individual specification.  
Page - 30  
ETM10E-04  
Application Manual  
AMERICA  
EPSON ELECTRONICS AMERICA, INC.  
HEADQUARTER  
214 Devcon Drive, San Jose, CA 95112, U.S.A.  
Phone: (1)800-228-3964  
FAX :(1)408-922-0238  
http://www.eea.epson.com  
Chicago Office  
1827 Walden Office Square. Suite 450 Schaumburg, IL 60173, U.S.A.  
Phone: (1)847-925-8350  
Fax: (1)847 925-8965  
El Segundo Office  
1960 E. Grand Ave., 2nd Floor, El Segundo, CA 90245, U.S.A.  
Phone: (1)800-249-7730 (Toll free) : (1)310-955-5300 (Main)  
Fax: (1)310-955-5400  
EUROPE  
EPSON EUROPE ELECTRONICS GmbH  
HEADQUARTER Riesstrasse 15, 80992 Munich, Germany  
Phone: (49)-(0)89-14005-0 Fax: (49)-(0)89-14005-110  
http://www.epson-electronics.de  
ASIA  
EPSON (China) CO., LTD.  
HEADQUARTER  
7F, Jinbao Building No.89 Jinbao Street Dongcheng District, Beijing, China, 100005  
Phone: (86) 10-8522-1199 Fax: (86) 10-8522-1120  
http://www.epson.com.cn/ed/  
Shanghai Branch  
Shenzhen Branch  
High-Tech Building,900 Yishan Road Shanghai 200233,China  
Phone: (86) 21-5423-5577 Fax: (86) 21-5423-4677  
12/F, Dawning Mansion,#12 Keji South Road, Hi-Tech Park,Shenzhen, China  
Phone: (86) 755-2699-3828 Fax: (86) 755-2699-3838  
EPSON HONG KONG LTD.  
Unit 715-723 7/F Trade Square, 681 Cheung Sha Wan Road, Kowloon, Hong Kong  
Phone: (86) 755-2699-3828 (Shenzhen Branch)  
Fax: (86) 755-2699-3838 (Shenzhen Branch)  
http://www.epson.com.hk  
EPSON TAIWAN TECHNOLOGY & TRADING LTD.  
14F, No.7, Song Ren Road, Taipei 110  
Phone: (886) 2-8786-6688 Fax: (886)2-8786-6660  
http://www.epson.com.tw/ElectronicComponent  
EPSON SINGAPORE PTE. LTD.  
No 1 HarbourFront Place, #03-02 HarbourFront Tower One, Singapore 098633.  
Phone: (65)- 6586-5500 Fax: (65) 6271-3182  
http://www.epson.com.sg/epson_singapore/electronic_devices/electronic_devices.page  
SEIKO EPSON CORPORATION KOREA Office  
5F, KLI 63 Building,60 Yoido-dong, Youngdeungpo-Ku, Seoul, 150-763, Korea  
Phone: (82) 2-784-6027 Fax: (82) 2-767-3677  
http://www.epson-device.co.kr  
Distributor  
Electronic devices information on WWW server  
http://www5.epsondevice.com/en/quartz/index.html  
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