请登录

免费注册
全部商品
电子元器件
方案中心
工业品
PDF资料
购物车 0
上传BOM

产品分类

找货询价

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

QQ咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

会员中心
购物车
技术支持

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

售后咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

CYM1851V33P6-25C

型号：

CYM1851V33P6-25C

品牌：

CYPRESS[ CYPRESS ]

页数：

8 页

PDF大小：

205 K

下载PDF手册
33  
fax id: 2052  
PRELIMINARY  
CYM1851V33  
1,024K x 32 3.3V Static RAM Module  
packages mounted on an epoxy laminate substrate. Four chip  
selects are used to independently enable the four bytes. Read-  
ing or writing can be executed on individual bytes or any com-  
Features  
• High-density 3.3V 32-megabit SRAM module  
bination of multiple bytes through proper use of selects.  
• 32-bit Standard Footprint supports densities from  
16K x 32 through 1M x 32  
• High-speed SRAMs  
The CYM1851V33 is designed for use with standard 72-pin  
SIMM sockets. The pinout is downward compatible with the  
64-pin JEDEC ZIP/SIMM module family (CYM1821,  
CYM1831, CYM1836, and CYM1841). Thus, a single mother-  
board design can be used to accommodate memory depth  
ranging from 16K words (CYM1821) to 1,024K words  
(CYM1851). The CYM1851V33 is offered in vertical and an-  
gled SIMM configurations and both are available with either  
tin-lead or 10 micro-inches of gold flash on the edge contacts.  
— Access time of 12 ns  
• Low active power  
— 3.3W (max.) at 12 ns  
• 72 pins  
• Available in ZIP, SIMM, or angled SIMM format  
Functional Description  
Presence detect pins (PD −PD ) are used to identify module  
0
3
memory density in applications where modules with alternate  
word depths can be interchanged.  
The CYM1851V33 is a 3.3V high-performance 32-megabit  
static RAM module organized as 1,024K words by 32 bits. This  
module is constructed from eight 1,024K x 4 SRAMs in SOJ  
Logic Block Diagram  
Pin Configuration  
ZIP/SIMM  
Top View  
PD - GND  
0
PD - OPEN  
NC  
PD  
1
3
5
1
NC  
3
PD  
0
A0-A19  
2
4
PD - GND  
2
2
PD  
20  
GND  
PD - OPEN  
3
OE  
6
8
7
9
PD  
1
8
I/O  
0
WE  
I/O  
I/O  
1
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
I/O  
I/O  
I/O  
9
10  
11  
I/O  
I/O  
3
2
1M x 4  
SRAM  
1M x 4  
SRAM  
I/O4–I/O7  
I/O −I/O  
0
3
V
4
4
4
4
4
CC  
7
8
9
4
A
0
A
A
1
2
A
A
I/O  
CS  
A
1
I/O  
I/O  
I/O  
I/O  
12  
13  
14  
15  
I/O  
I/O  
I/O  
1M x 4  
SRAM  
1M x 4  
5
I/O12–I/O15  
I/O20–I/O23  
I/O28–I/O31  
I/O −I/O  
8
11  
SRAM  
4
4
4
6
7
WE  
GND  
CS  
2
3
4
33  
35  
A
15  
A
14  
CS1  
34  
36  
CS  
CS  
2
1M x 4  
SRAM  
1M x 4  
SRAM  
I/O −I/O  
16  
19  
37  
39  
41  
43  
45  
47  
49  
51  
53  
55  
57  
59  
61  
63  
65  
67  
69  
4
CS  
3
16  
38  
40  
42  
44  
46  
48  
50  
52  
54  
56  
58  
60  
62  
64  
66  
68  
70  
72  
A
17  
A
OE  
I/O  
I/O  
I/O  
I/O  
CS  
CS  
GND  
24  
25  
26  
27  
I/O  
16  
I/O  
17  
1M x 4  
SRAM  
1M x 4  
SRAM  
I/O − I/O  
I/O  
24  
27  
18  
I/O  
19  
A
3
A
10  
A
4
5
A
A
A
11  
12  
13  
A
1851V33–1  
V
CC  
A
6
I/O  
I/O  
I/O  
I/O  
20  
21  
22  
23  
I/O  
28  
29  
30  
I/O  
I/O  
I/O  
A
31  
GND  
1851V33–2  
18  
A
19  
71  
NC  
NC  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Apr 1998 - Revised June 30, 1998  
PRELIMINARY  
CYM1851V33  
Selection Guide  
1851V33-12 1851V33-15 1851V33-20  
1851V33-25 1851V33-35  
Maximum Access Time (ns)  
12  
15  
20  
25  
35  
Maximum Operating Current (mA)  
1450  
540  
1250  
520  
1100  
480  
1100  
480  
1100  
480  
Maximum Standby Current (mA)  
Shaded area contains advance information.  
Maximum Ratings  
Operating Range  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Ambient  
Temperature  
Range  
V
CC  
Storage Temperature ................................. –55°C to +125°C  
Commercial  
0°C to +70°C  
3.3V +10%/  
−5%  
Ambient Temperature with  
Power Applied............................................... –10°C to +85°C  
Supply Voltage to Ground Potential ............... –0.5V to +4.6V  
DC Voltage Applied to Outputs  
in High Z State ................................................ –0.5V to +V  
CC  
DC Input Voltage............................................ –0.5V to +4.6V  
Electrical Characteristics Over the Operating Range  
Parameter  
Description  
Output HIGH Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
Input Load Current  
Output Leakage Current  
Test Conditions  
= Min., I = −4.0 mA  
OH  
Min.  
Max.  
Unit  
V
V
V
V
2.4  
OH  
CC  
CC  
V
= Min., I = 4.0 mA  
0.4  
+ 0.3  
CC  
V
OL  
OL  
V
2.0  
–0.3  
–16  
–10  
V
V
IH  
IL  
V
0.8  
+16  
V
I
I
I
GND < V < V  
CC  
µA  
µA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
IX  
I
GND < V < V , Output Disabled  
+10  
OZ  
CC  
O
CC  
V
Operating Supply  
V
= Max., I  
= 0 mA, -12  
1450  
1250  
1100  
540  
CC  
CC  
OUT  
Current  
CS < V  
f f  
N
IL, = MAX  
-15  
-20, -25, -35  
-12  
I
Automatic CS Power-Down  
Max. V , CS > V ,  
CC IH  
SB1  
SB2  
[1]  
Current  
Min. Duty Cycle = 100%  
-15  
520  
-20, -25, -35  
480  
I
Automatic CS Power-Down  
Max. V , CS > V − 0.2V, V > V − 0.2V,  
270  
CC  
CC  
IN  
CC  
[1]  
Current  
or V < 0.2V  
IN  
Shaded area contains advance information.  
Capacitance[2]  
Parameter  
Description  
Test Conditions  
T = 25°C, f = 1 MHz,  
Max.  
40  
Unit  
C
C
C
Input Capacitance (WE, OE, A  
Input Capacitance (CS)  
Output Capacitance  
)
pF  
pF  
pF  
INA  
0−19  
A
V
= 5.0V  
CC  
10  
INB  
8
OUT  
Notes:  
1. A pull-up resistor to VCC on the CS input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given.  
2. Tested on a sample basis.  
2
PRELIMINARY  
CYM1851V33  
AC Test Loads and Waveforms  
R1 317  
R1 317  
ALL INPUT PULSES  
90%  
10%  
Ω
Ω
5V  
5V  
3.0V  
GND  
90%  
10%  
OUTPUT  
OUTPUT  
R2  
351  
R2  
351  
Ω
Ω
30 pF  
5 pF  
5 ns  
5 ns  
≥
≥
INCLUDING  
JIG AND  
SCOPE  
INCLUDING  
JIG AND  
SCOPE  
1851V33–3  
1851V33–4  
(a)  
(b)  
Equivalent to:  
THÉVENIN EQUIVALENT  
167  
Ω
1.73V  
OUTPUT  
[3]  
Switching Characteristics Over the Operating Range  
1851V33-12  
1851V33-15  
Parameter  
Description  
Min.  
Max.  
Min.  
Max.  
Unit  
READ CYCLE  
t
t
t
t
t
t
t
t
t
t
Read Cycle Time  
12  
15  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RC  
Address to Data Valid  
12  
15  
AA  
Data Hold from Address Change  
CS LOW to Data Valid  
OE LOW to Data Valid  
OE LOW to Low Z  
3
3
OHA  
ACS  
DOE  
LZOE  
HZOE  
LZCS  
HZCS  
PD  
12  
7
15  
8
0
3
0
3
OE HIGH to High Z  
7
8
[4]  
CS LOW to Low Z  
[4, 5]  
CS HIGH to High Z  
7
8
CS HIGH to Power-Down  
12  
15  
[6]  
WRITE CYCLE  
t
t
t
t
t
t
t
t
t
t
Write Cycle Time  
12  
9
15  
10  
10  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
CS LOW to Write End  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
SCS  
AW  
9
0
HA  
1
1
SA  
10  
7
12  
8
PWE  
SD  
Data Set-Up to Write End  
Data Hold from Write End  
WE HIGH to Low Z  
1
1
HD  
3
3
LZWE  
HZWE  
[5]  
WE LOW to High Z  
0
7
0
8
Shaded area contains advance information.  
3
PRELIMINARY  
CYM1851V33  
[3]  
Switching Characteristics Over the Operating Range (continued)  
1851V33-20  
1851V33-25  
1851V33-35  
Parameter  
Description  
Min.  
20  
Max.  
Min.  
Max.  
Min.  
Max.  
Unit  
READ CYCLE  
t
t
t
t
t
t
t
t
t
t
Read Cycle Time  
25  
35  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RC  
Address to Data Valid  
Data Hold from Address Change  
CS LOW to Data Valid  
OE LOW to Data Valid  
OE LOW to Low Z  
20  
25  
35  
AA  
3
3
3
OHA  
ACS  
DOE  
LZOE  
HZOE  
LZCS  
HZCS  
PD  
20  
12  
25  
15  
35  
18  
0
3
0
3
0
3
OE HIGH to High Z  
10  
12  
15  
[4]  
CS LOW to Low Z  
[4, 5]  
CS HIGH to High Z  
10  
20  
12  
25  
15  
35  
CS HIGH to Power-Down  
[6]  
WRITE CYCLE  
t
t
t
t
t
t
t
t
t
t
Write Cycle Time  
20  
17  
17  
3
25  
20  
20  
3
35  
30  
30  
3
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
CS LOW to Write End  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
SCS  
AW  
HA  
2
2
2
SA  
15  
12  
2
20  
15  
2
30  
20  
2
PWE  
SD  
Data Set-Up to Write End  
Data Hold from Write End  
WE HIGH to Low Z  
HD  
3
3
3
LZWE  
HZWE  
[5]  
WE LOW to High Z  
0
12  
0
12  
0
15  
Switching Waveforms  
[7,8]  
Read Cycle No. 1  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
1851V33–5  
Notes:  
3. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified  
OL/IOH and 30-pF load capacitance.  
I
4. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device. These parameters are guaranteed and not 100% tested.  
5. tHZCS and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage.  
6. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can  
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.  
7. WE is HIGH for read cycle.  
8. Device is continuously selected, CS = VIL, and OE= VIL  
.
4
PRELIMINARY  
CYM1851V33  
Switching Waveforms (continued)  
[7,9]  
Read Cycle No. 2  
t
RC  
CS  
t
ACS  
OE  
t
HZOE  
t
DOE  
t
HZCS  
t
LZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA VALID  
DATA OUT  
t
LZCS  
t
PD  
t
PU  
ICC  
V
CC  
50%  
50%  
SUPPLY  
CURRENT  
ISB  
1851V33–6  
[6]  
Write Cycle No. 1 (WE Controlled)  
t
WC  
ADDRESS  
t
SCS  
CS  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
t
HD  
SD  
DATA IN  
DATA VALID  
t
t
LZWE  
HZWE  
HIGH IMPEDANCE  
DATA OUT  
DATA UNDEFINED  
1851V33–7  
Note:  
9. Address valid prior to or coincident with CS transition LOW.  
5
PRELIMINARY  
CYM1851V33  
Switching Waveforms (continued)  
[6,10]  
Write Cycle No. 2 (CS Controlled)  
t
WC  
ADDRESS  
t
SA  
t
SCS  
CS  
t
t
HA  
AW  
t
PWE  
WE  
t
t
HD  
SD  
DATA IN  
DATA VALID  
t
HZWE  
HIGH IMPEDANCE  
DATA OUT  
DATA UNDEFINED  
1851V33–8  
Note:  
10. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.  
Truth Table  
CS WE OE Inputs/Output  
Mode  
Deselect/Power-Down  
Read  
H
L
L
L
X
H
L
X
L
High Z  
Data Out  
Data In  
High Z  
X
H
Write  
H
Deselect  
Ordering Information  
Speed  
Package  
Operating  
(ns)  
Ordering Code  
Type  
PM04  
PM04  
PN04  
PN04  
PZ09  
PM04  
PM04  
PN04  
PN04  
PZ09  
Package Type  
72-Pin Plastic SIMM Module  
Range  
12  
CYM1851V33PM-12C  
CYM1851V33P8-12C  
CYM1851V33PN-12C  
CYM1851V33P6-12C  
CYM1851V33PZ-12C  
CYM1851V33PM-15C  
CYM1851V33P8-15C  
CYM1851V33PN-15C  
CYM1851V33P6-15C  
CYM1851V33PZ-15C  
Commercial  
72-Pin Plastic SIMM Module (gold contacts)  
72-Pin Plastic Angled SIMM Module  
72-Pin Plastic Angled SIMM Module (gold contacts)  
72-Pin Plastic ZIP Module  
15  
72-Pin Plastic SIMM Module  
Commercial  
72-Pin Plastic SIMM Module (gold contacts)  
72-Pin Plastic Angled SIMM Module  
72-Pin Plastic Angled SIMM Module (gold contacts)  
72-Pin Plastic ZIP Module  
Shaded area contains advance information.  
6
PRELIMINARY  
CYM1851V33  
Ordering Information (continued)  
Speed  
(ns)  
Package  
Type  
Operating  
Range  
Ordering Code  
Package Type  
20  
25  
35  
CYM1851V33PM-20C  
CYM1851V33P8-20C  
CYM1851V33PN-20C  
CYM1851V33P6-20C  
CYM1851V33PZ-20C  
CYM1851V33PM-25C  
CYM1851V33P8-25C  
CYM1851V33PN-25C  
CYM1851V33P6-25C  
CYM1851V33PZ-25C  
CYM1851V33PM-35C  
CYM1851V33P8-35C  
CYM1851V33PN-35C  
CYM1851V33P6-35C  
CYM1851V33PZ-35C  
PM04  
PM04  
PN04  
PN04  
PZ09  
PM04  
PM04  
PN04  
PN04  
PZ09  
PM04  
PM04  
PN04  
PN04  
PZ09  
72-Pin Plastic SIMM Module  
Commercial  
72-Pin Plastic SIMM Module (gold contacts)  
72-Pin Plastic Angled SIMM Module  
72-Pin Plastic Angled SIMM Module (gold contacts)  
72-Pin Plastic ZIP Module  
72-Pin Plastic SIMM Module  
Commercial  
Commercial  
72-Pin Plastic SIMM Module (gold contacts)  
72-Pin Plastic Angled SIMM Module  
72-Pin Plastic Angled SIMM Module (gold contacts)  
72-Pin Plastic ZIP Module  
72-Pin Plastic SIMM Module  
72-Pin Plastic SIMM Module (gold contacts)  
72-Pin Plastic Angled SIMM Module  
72-Pin Plastic Angled SIMM Module (gold contacts)  
72-Pin Plastic ZIP Module  
Document #: 38-M-00090-A  
Package Diagrams  
72-Pin Plastic SIMM Module PM04  
72-Pin Plastic Angled SIMM Module PN04  
7
PRELIMINARY  
CYM1851V33  
Package Diagrams (continued)  
72-Pin Plastic ZIP Module PZ09  
© Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
厂商 型号 描述 页数 下载

MERRIMAC

 		CYM-13R-9G 定向耦合器[ DIRECTIONAL COUPLER ] 2 页

SUMIDA

 		CYM-2B 滤波线圈\u003c SMD型： CYM系列\u003e[ Filter Coils < SMD Type: CYM Series> ] 2 页

ETC

 		CYM1220HD-10C X4 SRAM模块\n[ x4 SRAM Module ] 5 页

ETC

 		CYM1220HD-12C X4 SRAM模块\n[ x4 SRAM Module ] 5 页

ETC

 		CYM1220HD-12MB X4 SRAM模块\n[ x4 SRAM Module ] 5 页

ETC

 		CYM1220HD-15C X4 SRAM模块\n[ x4 SRAM Module ] 5 页

ETC

 		CYM1220HD-15MB X4 SRAM模块\n[ x4 SRAM Module ] 5 页

ETC

 		CYM1220HD-20MB X4 SRAM模块\n[ x4 SRAM Module ] 5 页

CYPRESS

 		CYM1240HD-25C [ SRAM Module, 256KX4, 25ns, CMOS, CDIP28, HERMETIC SEALED, MODULE, DIP-28 ] 1 页

CYPRESS

 		CYM1240HD-25MB [ SRAM Module, 256KX4, 25ns, CMOS, CDIP28, HERMETIC SEALED, MODULE, DIP-28 ] 1 页

购物指南

支付方式

配送服务

售后服务

发票须知

优惠券使用规则

特色服务

PCBA制造

国产品牌推荐

国产料号替代

质量保证

技术资料

行业资讯

关于我们

关于达普

联系我们

联系我们

服务热线：400-618-9990

企业邮箱：smail@ic72.com

服务时间：周一至周六 8:30-17:30

达普官方微信号

PDF索引：

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

IC型号索引：

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

Copyright 2024 gkzhan.com Al Rights Reserved 京ICP备06008810号-21 京

深圳网络警察报警平台
公共信息安全网络监察
经营性网站备案信息
不良信息举报中心
工商网监电子标识
全国公安机关备案
0.210829s