HYS 64/72Txx0x0GU
Unbuffered DDR2 SDRAM-Modules
4.6 IDD Measurement Conditions
(VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V)
Symbol
Parameter/Condition
Operating Current - One bank Active - Precharge
tCK = tCKmin., tRC = tRCmin., tRAS = tRASmin., CKE is HIGH, CS is high between valid commands. Address and con-
trol inputs are SWITCHING, Databus inputs are SWITCHING.
IDD0
IDD1
IDD2P
Operating Current - One bank Active - Read - Precharge
IOUT = 0 mA, BL = 4, tCK = tCKmin., tRC = tRCmin., tRAS = tRASmin.,tRCD = tRCDmin.,AL = 0, CL = CLmin.;
CKE is HIGH, CS is high between valid commands. Address and control inputs are SWITCHING, Databus inputs are
SWITCHING.
Precharge Power-Down Current: All banks idle; CKE is LOW; tCK = tCKmin.;
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
Precharge Standby Current: All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.;
IDD2N
Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Precharge Quiet Standby Current: All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.;
IDD2Q
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
Active Power-Down Current: All banks open; tCK = tCKmin., CKE is LOW; Other control and address inputs are STA-
IDD3P(0)
IDD3P(1)
IDD3N
BLE, Data bus inputs are FLOATING. MRS A12 bit is set to “0” (Fast Power-down Exit);
Active Power-Down Current: All banks open; tCK = tCKmin., CKE is LOW; Other control and address inputs are STA-
BLE, Data bus inputs are FLOATING. MRS A12 bit is set to “1” (Slow Power-down Exit);
Active Standby Current: All banks open; tCK = tCKmin.; tRAS = tRASmax; tRP = tRPmin.,CKE is HIGH; CS is high
between valid commands. Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Operating Current - Burst Read: All banks open; Continuous burst reads; BL = 4;AL = 0, CL = CLmin.; tCK = tCKmin.;
tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands.
IDD4R
Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0mA.
Operating Current - Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.;
tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands.
Address inputs are SWITCHING; Data Bus inputs are SWITCHING;
IDD4W
Burst Auto-Refresh Current: tCK = tCKmin., Refresh command every tRFC = tRFCmin. interval, CKE is HIGH, CS is
IDD5B
IDD5D
IDD6
HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Distributed Auto-Refresh Current: tCK = tCKmin., Refresh command every tRFC = tREFI interval, CKE is LOW and CS
is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Self-Refresh Current: CKE ≤ 0.2V; external clock off, CK and CK at 0V; Other control and address inputs are FLOAT-
ING, Data bus inputs are FLOATING. RESET = Low. IDD6 current values are guaranteed up to TCASE of 85oC max.
All Bank Interleave Read Current:
1. All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control and address
bus inputs are STABLE during DESELECTS. Iout = 0mA.
2. Timing pattern:
IDD7
- DDR2 -400-333: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D (12 clocks)
- DDR2 -533-444: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D (16 clocks)
- DDR2 -667-444: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D (19 clocks)
3. Legend: A = Activate, RA = Read with Auto-Precharge, D=DESELECT
Notes:
1. IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.
2. Definitions for IDD:
LOW is defined as VIN <= VIL(ac)max; HIGH is defined as VIN >= VIH(ac)min.
STABLE is defined as inputs are stable at a HIGH or LOW level.
FLOATING is defined as inputs are VREF = VDDQ / 2.
SWITCHING is defined as:
inputs are changing between HIGH and LOW every other clock (once per two cycles) for address and control signals, and
inputs changing between HIGH and LOW every other clock (once per cycle) for DQ signals not including mask or strobes.
3. IDD1, IDD4R, and IDD7A current measurements are defined with the outputs disabled (Iout = 0 mA). To achieve this on module
level the output buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
3. For two rank modules: For all active current measurements the other rank is in Precharge Power-Down Mode IDD2P
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