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CYK512K16SCCA-55BAI

型号：

CYK512K16SCCA-55BAI

品牌：

CYPRESS[ CYPRESS ]

页数：

10 页

PDF大小：

238 K

下载PDF手册
CYK512K16SCCA  
MoBL  
8-Mbit (512K x 16) Pseudo Static RAM  
Features  
Functional Description[1]  
• Advanced low power MoBL® architecture  
• High speed: 55 ns, 70 ns  
• Wide voltage range: 2.7V to 3.3V  
• Typical active current: 2 mA @ f = 1 MHz  
• Typical active current: 11 mA @ f = fMAX  
• Low standby power  
The CYK512K16SCCA is a high-performance CMOS pseudo  
static RAM (PSRAM) organized as 512K words by 16 bits that  
supports an asynchronous memory interface. This device  
features advanced circuit design to provide ultra-low active  
current. This is ideal for providing More Battery Life(MoBL)  
in portable applications such as cellular telephones. The  
device can be put into standby mode reducing power  
consumption dramatically when deselected (CE1 LOW, CE2  
HIGH or both BHE and BLE are HIGH). The input/output pins  
(I/O0 through I/O15) are placed in a high-impedance state  
when: deselected (CE1 HIGH, CE2 LOW), OE is deasserted  
HIGH, or during a write operation (Chip Enabled and Write  
Enable WE LOW). Reading from the device is accomplished  
by asserting the Chip Enables (CE1 LOW and CE2 HIGH) and  
Output Enable (OE) LOW while forcing the Write Enable (WE)  
HIGH. If Byte Low Enable (BLE) is LOW, then data from the  
memory location specified by the address pins will appear on  
I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from  
memory will appear on I/O8 to I/O15. See the Truth Table for a  
complete description of read and write modes.  
• Automatic power-down when deselected  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
512K x 16  
RAM Array  
I/O0–I/O7  
I/O8–I/O15  
COLUMN DECODER  
BHE  
WE  
CE2  
CE1  
OE  
BLE  
CE2  
CE1  
Power -Down  
Circuit  
BHE  
BLE  
Note:  
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-05425 Rev. *C  
Revised May 13, 2004  
 
CYK512K16SCCA  
MoBL  
Pin Configuration[2, 3, 4]  
48-Ball FBGA  
Top View  
1
2
4
3
5
6
A
A
2
A
CE2  
OE  
BLE  
0
1
A
B
C
A
A
I/O BHE  
CE1 I/O  
4
3
0
8
A
A
6
I/O  
I/O  
I/O  
I/O  
5
10  
1
2
9
VCC  
A
V
I/O  
I/O  
3
A17  
D
E
F
SS  
7
11  
VSS  
DNU  
A
16  
V
CC  
I/O  
I/O  
12  
4
A
A
15  
I/O  
I/O  
I/O  
I/O  
14  
13  
5
14  
6
A
A
G
H
I/O  
I/O  
NC  
WE  
13  
12  
15  
7
A
A
A
A
A18  
NC  
10  
9
11  
8
Product Portfolio[5]  
Power Dissipation  
Operating, ICC (mA)  
f = 1 MHz f = fMAX  
VCC Range  
(V)  
Standby, ISB2  
(µA)  
Speed  
(ns)  
55  
Product  
Min.  
Typ.  
3.0  
Max.  
3.3  
Typ.[5]  
Max.  
5
Typ.[5]  
11  
Max.  
22  
Typ.[5]  
Max.  
CYK512K16SCCA  
2.7  
2
55  
100  
70  
17  
Notes:  
2. DNU pins are to be left floating or tied to V  
.
SS  
3. Ball G2, H6 are the address expansion pins for the 16-Mbit and 32-Mbit densities respectively.  
4. NC “no connect”—not connected internally to the die.  
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V (typ) and T = 25°C.  
CC  
CC  
A
Document #: 38-05425 Rev. *C  
Page 2 of 10  
 
 
 
 
CYK512K16SCCA  
MoBL  
DC Input Voltage[6, 7, 8] ....................................−0.4V to 3.7V  
Output Current into Outputs (LOW) ............................ 20 mA  
Maximum Ratings  
(Above which the useful life may be impaired. For user guide-  
Static Discharge Voltage ......................................... > 2001V  
lines, not tested.)  
(per MIL-STD-883, Method 3015)  
Storage Temperature .................................–65°C to +150°C  
Latch-up Current ....................................................> 200 mA  
Ambient Temperature with  
Power Applied ..............................................–40°C to +85°C  
Operating Range  
Supply Voltage to Ground Potential ................ −0.4V to 4.6V  
Ambient  
DC Voltage Applied to Outputs  
Range  
Temperature (TA)  
VCC  
in High-Z State[6, 7, 8] ....................................... −0.4V to 3.7V  
Industrial  
−25°C to +85°C  
2.7V to 3.3V  
DC Electrical Characteristics (Over the Operating Range)[5, 6, 7, 8]  
CYK512K16SCCA-55  
Min. Typ.[5] Max.  
CYK512K16SCCA-70  
Min. Typ.[5] Max. Unit  
Parameter  
Vcc  
VOH  
Description  
Supply Voltage  
Output HIGH Voltage IOH = −0.1 mA  
Test Conditions  
2.7  
VCC  
0.4  
3.0  
3.3  
0.4  
VCC  
0.4  
2.7  
VCC  
0.4  
3.3  
V
V
–
–
VOL  
VIH  
Output LOW Voltage IOL = 0.1 mA  
Input HIGH Voltage  
0.4  
VCC  
0.4  
V
V
0.8 *  
VCC  
+
0.8 *  
VCC  
+
VIL  
IIX  
Input LOW Voltage F = 0  
−0.4  
−1  
0.4  
+1  
−0.4  
−1  
0.4  
+1  
V
µA  
Input Leakage  
Current  
GND < VIN < VCC  
IOZ  
ICC  
Output Leakage  
Current  
VCC Operating  
Supply Current  
GND < VOUT < VCC, Output  
Disabled  
−1  
+1  
−1  
+1  
µA  
f = fMAX = 1/tRC VCC = 3.3V,  
11  
2
22  
5
11  
2
17  
5
mA  
I
OUT = 0 mA,  
f = 1 MHz  
CE > VCC − 0.2V, CE2 < 0.2V  
CMOS level  
ISB1  
Automatic CE1  
100  
400  
100  
400  
µA  
µA  
Power-down Current VIN > VCC − 0.2V, VIN < 0.2V,  
—CMOS Inputs  
f = fMAX(Address and Data Only),  
f = 0 (OE, WE, BHE and BLE)  
CE > VCC − 0.2V, CE2 < 0.2V  
ISB2  
Automatic CE1  
55  
100  
55  
100  
Power-down Current VIN > VCC − 0.2V or VIN < 0.2V,  
—CMOS Inputs  
f = 0, VCC =3.3V  
Capacitance[9]  
Parameter  
Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
Max.  
8
8
Unit  
pF  
pF  
CIN  
COUT  
TA = 25°C, f = 1 MHz  
V
CC = VCC(typ)  
Thermal Resistance[9]  
Parameter  
Description  
Test Conditions  
FBGA  
Unit  
θJA  
Thermal Resistance  
Test conditions follow standard test methods  
and procedures for measuring thermal  
impedance, per EIA / JESD51.  
55  
°C/W  
(Junction to Ambient)  
θJC  
Thermal Resistance  
(Junction to Case)  
17  
°C/W  
Notes:  
6. V  
7. V  
= V + 0.5V for pulse durations less than 20 ns.  
CC  
IH(MAX)  
= –0.5V for pulse durations less than 20 ns.  
IL(MIN)  
8. Overshoot and undershoot specifications are characterized and are not 100% tested.  
9. Tested initially and after design or process changes that may affect these parameters.  
Document #: 38-05425 Rev. *C  
Page 3 of 10  
 
 
 
 
CYK512K16SCCA  
MoBL  
AC Test Loads and Waveforms  
R1  
ALL INPUT PULSES  
90%  
10%  
VCC  
OUTPUT  
VCC  
GND  
Rise Time = 1 V/ns  
90%  
10%  
Fall Time = 1 V/ns  
R2  
30 pF  
INCLUDING  
JIG AND  
SCOPE  
Equivalent to: THEVENIN EQUIVALENT  
RTH  
OUTPUT  
VTH  
Parameters  
3.0V VCC  
22000  
22000  
11000  
1.50  
Unit  
Ω
R1  
R2  
RTH  
VTH  
Ω
Ω
V
Switching Characteristics (Over the Operating Range) [10, 11, 12, 13, 14]  
CYK512K16SCCA-55  
CYK512K16SCCA-70  
Parameter  
Read Cycle  
tRC  
Description  
Min.  
55[14]  
5
Max.  
Min.  
Max.  
Unit  
Read Cycle Time  
Address to Data Valid  
70  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
55  
70  
tOHA  
tACE  
Data Hold from Address Change  
CE1 LOW and CE2 HIGH to Data Valid  
OE LOW to Data Valid  
OE LOW to Low Z[11, 12]  
OE HIGH to High Z[11, 12]  
CE1 LOW and CE2 HIGH to Low Z[11, 12]  
CE1 HIGH and CE2 LOW to High Z[11, 12]  
BLE/BHE LOW to Data Valid  
BLE/BHE LOW to Low Z[11, 12]  
BLE/BHE HIGH to High-Z[11, 12]  
Address Skew  
5
55  
25  
70  
35  
tDOE  
tLZOE  
tHZOE  
tLZCE  
tHZCE  
tDBE  
5
5
5
5
25  
25  
25  
55  
25  
70  
tLZBE  
5
5
tHZBE  
10  
0
25  
10  
[14]  
tSK  
Notes:  
10. Test conditions assume signal transition time of 1V/ns or higher, timing reference levels of V  
/2, input pulse levels of 0V to V  
and output loading of  
CC(typ)  
CC(typ),  
the specified I /I and 30-pF load capacitance  
OL OH  
11. t  
, t  
, t  
and t  
transitions are measured when the outputs enter a high-impedance state.  
HZOE HZCE HZBE  
HZWE  
12. High-Z and Low-Z parameters are characterized and are not 100% tested.  
13. The internal write time of the memory is defined by the overlap of WE, CE = V , CE = V , BHE and/or BLE =V . All signals must be ACTIVE to initiate a write  
1
IL  
2
IH  
IL  
and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that  
terminates write.  
14. To achieve 55-ns performance, the read access should be CE controlled. In this case t  
is the critical parameter and t is satisfied when the addresses are  
SK  
ACE  
stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle.  
Document #: 38-05425 Rev. *C  
Page 4 of 10  
 
 
 
 
 
CYK512K16SCCA  
MoBL  
Switching Characteristics (Over the Operating Range) (continued)[10, 11, 12, 13, 14]  
CYK512K16SCCA-55  
CYK512K16SCCA-70  
Parameter  
Write Cycle[13]  
Description  
Min.  
Max.  
Min.  
Max.  
Unit  
tWC  
tSCE  
tAW  
tHA  
tSA  
tPWE  
tBW  
tSD  
tHD  
tHZWE  
tLZWE  
Write Cycle Time  
55  
45  
45  
0
70  
55  
55  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CE1 LOW and CE2 HIGH to Write End  
Address Set-up to Write End  
Address Hold from Write End  
Address Set-up to Write Start  
WE Pulse Width  
BLE/BHE LOW to Write End  
Data Set-up to Write End  
Data Hold from Write End  
WE LOW to High Z[11, 12]  
WE HIGH to Low Z[11, 12]  
0
0
40  
50  
25  
0
55  
55  
25  
0
25  
25  
5
5
Switching Waveforms  
Read Cycle 1 (Address Transition Controlled)[14, 15, 16]  
tRC  
ADDRESS  
t
AA  
tSK  
PREVIOUS DATA VALID  
t
OHA  
DATA OUT  
DATA VALID  
Read Cycle 2 (OE Controlled)[14, 15]  
ADDRESS  
tRC  
tSK  
CE1  
tHZCE  
CE  
2
tACE  
BHE/BLE  
tDBE  
tHZBE  
tLZBE  
OE  
tHZOE  
tDOE  
tLZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA OUT  
DATA VALID  
tLZCE  
I
CC  
t
V
CC  
Notes:  
15. WE is HIGH for Read Cycle.  
16. Device is continuously selected. OE, CE = V  
.
IL  
Document #: 38-05425 Rev. *C  
Page 5 of 10  
 
CYK512K16SCCA  
MoBL  
Switching Waveforms (continued)  
Write Cycle No. 1(WE Controlled)[12, 13, 17, 18, 19]  
t
WC  
ADDRESS  
t
SCE  
CE  
1
CE  
2  
t
t
HA  
AW  
t
t
PWE  
SA  
WE  
t
BW  
BHE/BLE  
OE  
t
SD  
t
HD  
VALID DATA  
DATAI/O  
DO N’T CARE  
t
HZOE  
Write Cycle 2 (CE1 or CE2 Controlled)[12, 13, 17, 18, 19]  
tWC  
ADDRESS  
CE1  
tSCE  
CE  
2
tSA  
tAW  
tHA  
tPWE  
WE  
tBW  
BHE/BLE  
OE  
tSD  
VALID DATA  
tHD  
DATA I/O  
DON’T CARE  
tHZOE  
Notes:  
17. Data I/O is high impedance if OE >V  
.
IH  
18. If Chip Enable goes INACTIVE simultaneously with WE = HIGH, the output remains in a high-impedance state.  
19. During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.  
Document #: 38-05425 Rev. *C  
Page 6 of 10  
 
 
 
CYK512K16SCCA  
MoBL  
Switching Waveforms (continued)  
Write Cycle 3 (WE Controlled, OE LOW)[18, 19]  
tWC  
ADDRESS  
CE1  
tSCE  
CE  
2
tBW  
tAW  
BHE/BLE  
tHA  
tSA  
tPWE  
WE  
t
HD  
tSD  
DON’T CARE  
DATAI/O  
VALID DATA  
tLZWE  
tHZWE  
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[18, 19]  
t
WC  
ADDRESS  
CE1  
CE  
2
t
SCE  
AW  
t
t
HA  
tBW  
BH E/BLE  
WE  
t
SA  
tPWE  
t
HD  
t
SD  
DON’T CARE  
DATA I/O  
VALID DATA  
Document #: 38-05425 Rev. *C  
Page 7 of 10  
CYK512K16SCCA  
MoBL  
Truth Table[20]  
CE1  
H
X
X
L
CE2  
X
L
X
H
WE  
X
X
X
H
OE  
X
X
X
L
BHE BLE  
Inputs/Outputs  
High Z  
High Z  
High Z  
Data Out (I/O0–I/O15  
Mode  
Power  
X
X
H
L
X
X
H
L
Deselect/Power-down  
Deselect/Power-down  
Deselect/Power-down  
Standby (ISB  
Standby (ISB  
Standby (ISB)  
)
)
)
Read (Upper Byte and Lower Active (ICC)  
Byte)  
L
L
H
H
H
H
L
L
H
L
L
Data Out (I/O0–I/O7);  
I/O8–I/O15 in High Z  
Data Out (I/O8–I/O15);  
I/O0–I/O7 in High Z  
Read (Lower Byte only)  
Active (ICC  
)
H
Read (Upper Byte only)  
Active (ICC)  
L
L
L
L
H
H
H
H
H
H
H
L
H
H
H
X
L
H
L
L
L
H
L
High Z  
High Z  
High Z  
Output Disabled  
Output Disabled  
Output Disabled  
Active (ICC  
Active (ICC  
Active (ICC  
)
)
)
L
Data In (I/O0–I/O15  
)
Write (Upper Byte and Lower Active (ICC)  
Byte)  
L
L
H
H
L
L
X
X
H
L
L
Data In (I/O0–I/O7);  
I/O8–I/O15 in High Z  
Data In (I/O8–I/O15);  
I/O0 –I/O7 in High Z  
Write (Lower Byte Only)  
Active (ICC  
)
H
Write (Upper Byte Only)  
Active (ICC)  
Ordering Information  
Speed  
Package  
Name  
BA48K  
Operating  
Range  
Industrial  
(ns)  
55  
Ordering Code  
CYK512K16SCCAU-55BAI  
Package Type  
48-ball Fine Pitch BGA (6.0 x 8.0 x 1.2 mm)  
70  
CYK512K16SCCAU-70BAI  
BA48K  
48-ball Fine Pitch BGA (6.0 x 8.0 x 1.2 mm)  
Industrial  
Note:  
20. H = Logic HIGH, L = Logic LOW, X = Don’t Care  
Document #: 38-05425 Rev. *C  
Page 8 of 10  
 
CYK512K16SCCA  
MoBL  
Package Diagrams  
48-Ball (6 mm x 8mm x 1.2 mm) FBGA BA48K  
BOTTOM VIEW  
A1 CORNER  
TOP VIEW  
Ø0.05 M C  
Ø0.25 M C A B  
Ø0.30 0.05ꢀ(48X  
A1 CORNER  
1
2
3
5
6
6
5
3
2
1
(
(
A
B
A
B
C
C
D
D
E
F
E
F
G
H
G
H
1.475  
A
A
0.75  
3.75  
6.00 0.10  
B
6.00 0.10  
B
0.15ꢀ(8X  
REFERENCE JEDEC MO-207  
SEATING PLANE  
51-85193-*A  
C
MoBL is a registered trademark, and MoBL3 and More Battery Life are trademarks, of Cypress Semiconductor Corporation. All  
product and company names mentioned in this document are the trademarks of their respective holders.  
Document #: 38-05425 Rev. *C  
Page 9 of 10  
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
CYK512K16SCCA  
MoBL  
Document History Page  
Document Title: CYK512K16SCCA 8-Mbit (512K x 16) Pseudo Static RAM  
Document #: 38-05425  
Orig. of  
REV.  
**  
ECN NO. Issue Date Change  
Description of Change  
130538  
01/27/04  
AWK  
New Data Sheet  
*A  
216680  
See ECN  
REF  
Added 55 ns Speed bin  
Updated from Advance Information to Final Data Sheet.  
*B  
*C  
220121  
230851  
See ECN  
See ECN  
REF  
AJU  
Changed the tOHA for 70 ns speed grade from 10 ns to 5 ns  
Changed the ISB2 from 80 µA to 100 µA  
Changed Ordering code from CYK512K16SCCA to CYK512K16SCCAU in  
‘Ordering Information’ table  
Modified MAX limit on DC Input voltage from 3.3V to 3.7V in ‘Maximum  
Ratings’ section  
Document #: 38-05425 Rev. *C  
Page 10 of 10  
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