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INTEGRATED CIRCUITS

DATA SHEET

TZA3019

2.5 Gbits/s dual

postamplifier with level

detectors and 2 × 2 switch

Product speciﬁcation

2001 Jun 25

Supersedes data of 2000 Apr 10

File under Integrated Circuits, IC19

Philips Semiconductors

Product speciﬁcation

2.5 Gbits/s dual postampliﬁer with level

detectors and 2 × 2 switch

TZA3019

FEATURES

APPLICATIONS

• Dual postamplifier

• Postamplifier for Synchronous Digital Hierarchy and

Synchronous Optical Network (SDH/SONET)

transponder

• Single 3.3 V power supply

• Wideband operation from 50 kHz to 2.5 GHz (typical

value)

• SDH/SONET wavelength converter

• Crosspoint or channel switch

• PECL driver

• Fully differential

• Channels are delay matched

• Fibre channel arbitrated loop

• Protection ring

• On-chip DC-offset compensations without external

capacitor

• Interfacing with positive or negative supplied logic

• Switching possibility between channels

• Monitoring

• Signal level detectors

• Positive Emitter Coupled Logic (PECL) or Current-Mode

Logic (CML) compatible data outputs adjustable from

200 to 800 mV (p-p) single-ended

• Swing converter CML 200 mV (p-p) to

PECL 800 mV (p-p)

• Port bypass circuit

• Power-down capability for unused outputs and detectors

• Rise and fall times 80 ps (typical value)

• 2.5 GHz clock amplification.

• Possibility to invert the output of each channel

separately

GENERAL DESCRIPTION

The TZA3019 is a low gain postamplifier multiplexer with a

dual RSSI and/or LOS detector that is designed for use in

critical signal path control applications, such as

loop-through, redundant channel switching or Wavelength

Division Multiplexing (WDM). The signal path is

unregistered, so no clock is required for the data inputs.

The signal path is fully differential and delay matched. It is

capable of operating from 50 kHz to 2.5 GHz.

• Input level-detection circuits for Received Signal

Strength Indicator (RSSI) or Loss Of Signal (LOS)

detection, programmable from 0.4 to 400 mV (p-p)

single-ended, with open-drain comparator output for

direct interfacing with positive or negative logic

• Reference voltage for output level and LOS adjustment

• Automatic strongest input signal switch possibility

(TZA3019 version B)

The TZA3019 HTQFP32 and HBCC32 packages can be

delivered in three versions:

• HTQFP32 or HBCC32 plastic package with exposed

pad.

• TZA3019AHT and TZA3019AVH with two RSSI signals

• TZA3019BHT and TZA3019BVH with one RSSI and

one LOS signal

• TZA3019CHT and TZA3019CVH with two LOS signals.

ORDERING INFORMATION

TYPE

PACKAGE

NUMBER

NAME

DESCRIPTION

VERSION

TZA3019AHT

TZA3019BHT

TZA3019CHT

TZA3019AVH

TZA3019BVH

TZA3019CVH

TZA3019U

HTQFP32 plastic, heatsink thin quad ﬂat package; 32 leads; body 5 × 5 × 1.0 mm

SOT547-2

HBCC32

−

plastic, heatsink bottom chip carrier; 32 terminals; body 5 × 5 × 0.65 mm SOT560-1

bare die; 2.22 × 2.22 × 0.28 mm

−

2001 Jun 25

2

Philips Semiconductors

Product speciﬁcation

2.5 Gbits/s dual postampliﬁer with level

detectors and 2 × 2 switch

TZA3019

BLOCK DIAGRAM

handbook, full pagewidth

32

25

27

GND1B

RSSI1

GND1A

10

LOSTH1

LOS

DETECTOR

1×

offset

level

TZA3019AHT

TZA3019AVH

12

29

31

LEVEL1

INV1

S1

24

1

2

3

V

CC1B

V

SWITCH

CC1A

23

22

21

OUT1

IN1

IN1Q

OUT1Q

A1A A1B

4

V

CC1B

V

CC1A

15

8

14

BAND GAP

REFERENCE

DFT

V

TEST

ref

V

17

18

19

CC2A

V

A2A A2B

CC2B

7

6

5

OUT2Q

OUT2

IN2Q

IN2

V

20

CC2A

SWITCH

V

CC2B

30

28

13

S2

INV2

level

LEVEL2

offset

26

1×

RSSI2

LOS

DETECTOR

11

9

LOSTH2

GND2A

16

GND2B

MGT028

Fig.1 Block diagram (TZA3019AHT and TZA3019AVH).

3

2001 Jun 25

Philips Semiconductors

Product speciﬁcation

2.5 Gbits/s dual postampliﬁer with level

detectors and 2 × 2 switch

TZA3019

handbook, full pagewidth

32

25

27

GND1A

GND1B

LOS1

10

LOSTH1

LOS

DETECTOR

5 kΩ

offset

level

TZA3019BHT

TZA3019BVH

12

LEVEL1

29

INV1

31

S1

24

V

1

CC1B

V

SWITCH

CC1A

2

3

23

22

21

OUT1

IN1

IN1Q

OUT1Q

A1A A1B

V

4

CC1B

CC1A

TEST

CC2A

15

8

14

BAND GAP

REFERENCE

DFT

V

ref

V

17

18

19

V

A2A A2B

CC2B

7

6

5

OUT2Q

OUT2

IN2Q

IN2

20

CC2A

SWITCH

V

CC2B

30

28

13

S2

INV2

level

LEVEL2

offset

26

1×

RSSI2

LOS

DETECTOR

11

9

LOSTH2

GND2A

16

GND2B

MGT027

Fig.2 Block diagram (TZA3019BHT and TZA3019BVH).

4

2001 Jun 25

Philips Semiconductors

Product speciﬁcation

2.5 Gbits/s dual postampliﬁer with level

detectors and 2 × 2 switch

TZA3019

handbook, full pagewidth

32

25

27

GND1B

LOS1

GND1A

10

LOSTH1

LOS

DETECTOR

5 kΩ

offset

level

TZA3019CHT

TZA3019CVH

12

LEVEL1

29

INV1

31

S1

24

V

1

CC1B

V

SWITCH

CC1A

IN1

2

3

23

22

21

OUT1

IN1Q

OUT1Q

V

A1A A1B

4

CC1B

CC1A

TEST

15

8

14

BAND GAP

REFERENCE

DFT

V

ref

V

17

18

19

CC2A

V

CC2B

A2A A2B

7

6

5

OUT2Q

OUT2

IN2Q

IN2

20

SWITCH

CC2A

S2

V

CC2B

30

28

13

INV2

level

LEVEL2

offset

LOS

DETECTOR

5 kΩ

26

LOS2

11

9

LOSTH2

GND2A

16

GND2B

MGS553

Fig.3 Block diagram (TZA3019CHT and TZA3019CVH).

5

2001 Jun 25

Philips Semiconductors

Product speciﬁcation

2.5 Gbits/s dual postampliﬁer with level

detectors and 2 × 2 switch

TZA3019

PINNING

SYMBOL TZA3019xHT/xVH⁽¹⁾PAD TYPE⁽²⁾

DESCRIPTION

A

B

C

V_CC1A

IN1

1

2

1

2

1

2

1

2

S

I

supply voltage for input 1 and LOS1 circuits

differential circuit 1 input; complimentary to pin IN1Q; DC bias

level is set internally at approximately V_CC− 0.33 V

IN1Q

3

I

differential circuit 1 input; complimentary to pin IN1; DC bias level

is set internally at approximately V_CC− 0.33 V

V_CC1A

n.c.

4

−

5

6

4

−

5

6

4

−

5

6

4

5

6

7

8

S

−

S

I

supply voltage for input 1 and LOS1 circuits

not connected

n.c.

not connected

V_CC2A

IN2

supply voltage for input 2 and LOS2 circuits

differential circuit 2 input; complimentary to pin IN2Q; DC bias

level is set internally at approximately V_CC− 0.33 V

IN2Q

7

9

I

differential circuit 2 input; complimentary to pin IN2; DC bias level

is set internally at approximately V_CC− 0.33 V

V_CC2A

8

9

8

9

8

9

10

11

12

S

I

supply voltage for input 2 and LOS2 circuits

ground for input 2 and LOS2 circuits

GND2A

LOSTH1

10

input for level detector programming of input 1 circuit; threshold

level is set by connecting external resistors between pins V_CC1A

and V_ref; when forced to GND1A or not connected, the

LOS1 circuit will be switched off

LOSTH2

11

13

I

input for level detector programming of input 2 circuit; threshold

level is set by connecting external resistors between pins V_CC2A

and V_ref; when forced to GND2A or not connected, the

LOS2 circuit will be switched off

n.c.

−

14

15

−

not connected

LEVEL1

12

I

input for programming output level of output 1 circuit; output level

is set by connecting external resistors between

pins V_CC1Aand V_ref; when forced to V_CC1Aor not connected,

pins OUT1 and OUT1Q will be switched off

LEVEL2

V_ref

13

14

13

14

13

14

16

I

input for programming output level of output 2 circuit; output level

is set by connecting external resistors between pins V_CC2A

and V_ref; when forced to V_CC2Aor not connected, pins OUT2

and OUT2Q will be switched off

17

O

reference voltage for level circuit and LOS threshold programming;

typical value is V_CC− 1.6 V; no external capacitor allowed

n.c.

−

18

19

20

21

22

−

I

not connected

TEST

GND2B

V_CC2B

OUT2Q

15

16

17

18

15

16

17

18

15

16

17

18

for test purposes only; to be left open-circuit in the application

ground for output 2 circuit

S

O

supply voltage for output 2 circuit

PECL or CML compatible differential circuit 2 output;

complimentary to pin OUT2

2001 Jun 25

6

Philips Semiconductors

Product speciﬁcation

2.5 Gbits/s dual postampliﬁer with level

detectors and 2 × 2 switch

TZA3019

SYMBOL TZA3019xHT/xVH⁽¹⁾PAD TYPE⁽²⁾

DESCRIPTION

A

B

C

OUT2

19

23

O

PECL or CML compatible differential circuit 2 output;

complimentary to pin OUT2Q

V_CC2B

n.c.

20

−

20

−

20

−

24

25

26

27

28

S

−

supply voltage for output 2 circuit

not connected

n.c.

−

not connected

V_CC1B

OUT1Q

21

22

21

22

21

22

S

O

supply voltage for output 1 circuit

PECL or CML compatible differential circuit 1 output;

complimentary to pin OUT1

OUT1

23

29

O

PECL or CML compatible differential circuit 1 output;

complimentary to pin OUT1Q

V_CC1B

GND1B

RSSI2

LOS2

24

25

26

−

24

25

26

−

24

25

−

30

31

32

S

O

supply voltage for output 1 circuit

ground for output 1 circuit

output of received signal strength indicator of detector 2

26

33 O-DRN output loss of signal detector 2; detection of input 2 signal; direct

drive of positive or negative supplied logic via internal 5 kΩ

resistor

RSSI1

LOS1

27

−

34

O

output of received signal strength indicator of detector 1

−

27

35 O-DRN output loss of signal detector 1; detection of input 1 signal; direct

drive of positive or negative supplied logic via internal 5 kΩ

resistor

INV2

INV1

S2

28

29

30

31

28

29

30

31

28

29

30

31

36

37

38

39

TTL

input to invert the signal of pins OUT2 and OUT2Q; directly

positive (inverted) or negative supplied logic driven

input to invert the signal of pins OUT1 and OUT1Q; directly of

positive (inverted) or negative supplied logic driven

input selector output 2 circuit; directly positive (inverted) or

negative supplied logic driven

S1

input selector output 1 circuit; directly positive (inverted) or

negative supplied logic driven

GND1A

GNDp

32

40

S

ground for input 1 and LOS1 circuits

ground pad (exposed die pad)

pad

−

Notes

1. The ‘x’ in TZA3019xHT/xVH represents versions A, B and C.

2. Pin type abbreviations: O = output, I = input, S = power supply, TTL = logic input and O-DRN = open-drain output.

2001 Jun 25

7

Philips Semiconductors

Product speciﬁcation

2.5 Gbits/s dual postampliﬁer with level

detectors and 2 × 2 switch

TZA3019

handbook, full pagewidth

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

V

CC1B

CC1A

IN1

OUT1

exposed pad

IN1Q

OUT1Q

V

CC1A

CC1B

TZA3019xHT

V

CC2A

IN2

CC2B

OUT2

GNDp

IN2Q

OUT2Q

V

CC2A

CC2B

MGS554

Fig.4 Pin configuration HTQFP32 package.

handbook, full pagewidth

V

1

32 31 30 29 28 27 26

exposed pad

25

CC1A

V

IN1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

CC1B

IN1Q

OUT1

V

OUT1Q

CC1A

V

TZA3019xVH

CC1B

CC2A

IN2

V

CC2B

IN2Q

OUT2

GNDp

V

OUT2Q

CC2A

V

9

10 11 12 13 14 15 16

17

CC2B

MGT029

Fig.5 Pin configuration HBCC32 package.

8

2001 Jun 25

Philips Semiconductors

Product speciﬁcation

2.5 Gbits/s dual postampliﬁer with level

detectors and 2 × 2 switch

TZA3019

FUNCTIONAL DESCRIPTION

Matching the transmitting end to absorb reflections is only

recommended for very sensitive applications.

The TZA3019 is a dual postamplifier with multiplexer and

loss of signal detection (see Figs 1, 2 and 3). The RF path

starts with the multiplexer, which connects an amplifier to

one of the two inputs. It is possible to invert the output for

easy layout of the Printed-Circuit Board (PCB). The signal

is amplified to a certain level. To guarantee this level with

minimum distortion over the temperature range and level

range, an active control part is added. The offset

compensation circuit following the inverter minimizes the

offset.

In such cases, pull-up resistors of 100 Ω should be

connected as close as possible to the IC from pins OUT1

and OUT1Q, and pins OUT2 and OUT2Q to GND1B and

GND2B respectively. These matching resistors are not

needed in most applications.

V

handbook, halfpage

CC1A,

CC2A

12 pF

420 Ω

50 Ω

The Received Signal Strength Indicator (RSSI) or the Loss

Of Signal (LOS) detector uses a 7-stage ‘successive

detection’ circuit. It provides a logarithmic output. The LOS

detector is followed by a comparator with a programmable

threshold. The input signal level-detection is implemented

to check if the input signal voltage is above the user

programmed level. This can insure that data will only be

transmitted when the input signal-to-noise ratio is sufficient

for low bit error rate system operation. A second

offset compensation circuit minimizes the offset of the

logarithmic amplifier.

50 Ω

IN1, IN2

IN1Q, IN2Q

GND1A,

GND2A

MGS555

Fig.6 RF input circuit.

RF input circuit

The input circuit contains internal 50 Ω resistors

decoupled to V_CCvia an internal common mode 12 pF

capacitor (see Fig.6).

Postampliﬁer level adjustment

The postamplifier boosts the signal up to PECL levels. The

output can be either CML- or PECL-level compatible,

adjusted by means of the voltage on pins LEVEL1

and LEVEL2. The DC voltages of pins OUT1 and OUT1Q,

and pins OUT2 and OUT2Q match with the DC-levels

on pins LEVEL1 and LEVEL2, respectively. Due to the

receiving end 50 Ω load resistance, it means that at the

same level of V_o(p-p), V_LEVEL1and V_LEVEL2with

The input pins are DC-biased at approximately

V_CC− 0.33 V by an internal reference generator. The

TZA3019 can be DC-coupled, but AC-coupling is

preferred. In case of DC-coupling, the driving source must

operate within the allowable input range

(V_CC− 1.0 V to V_CC+ 0.3 V). A DC-offset voltage of more

than a few millivolts should be avoided, since the internal

DC-offset compensation circuit has a limited correction

range. When AC-coupling is used, if no DC-compatibility is

required, the values of the coupling capacitors must be

large enough to pass the lowest input frequency of

interest. Capacitor tolerance and resistor variation must be

included for an accurate calculation. Do not use signal

frequencies around the low cut-off circuit frequencies

(f_−3dB(l)= 50 kHz for the postamplifiers and f_−3dB(l)= 1 MHz

for the LOS circuits).

AC-coupling are not equal to V_LEVEL1and V_LEVEL2with

DC-coupling (see Figs 7 and 8).

When pin LEVEL1 or LEVEL2 is connected to V_CCor not

connected, the postamplifier is in power-down state

(see Fig.7).

Postampliﬁer DC offset cancellation loop

Offset control loops connected between the inputs of the

buffers A1A and A2A and the outputs of the amplifiers A1B

and A2B (see Figs 1, 2 and 3) will keep the input of both

buffers at their toggle point during the absence of an input

signal. The active offset compensation circuit is integrated,

so no external capacitor is required. The loop time

constant determines the lower cut-off frequency of the

amplifier chain. The cut-off frequency of the offset

RF output circuit

Matching the main amplifier outputs (see Fig.7) is not

mandatory. In most applications, the transmission line

receiving end will be properly matched, while very little

reflections occur.

compensations is fixed internally at approximately 5 kHz.

2001 Jun 25

9

Philips Semiconductors

Product speciﬁcation

2.5 Gbits/s dual postampliﬁer with level

detectors and 2 × 2 switch

TZA3019

V

CC1A,

V

CC1B,

CC2B

handbook, full pagewidth

V

CC2A

50

Ω

50

Ω

100 Ω

R1

OUT1,

OUT2

V

o

OUT1Q,

OUT2Q

LEVEL1,

LEVEL2

V

level

REG

R2

V

CC

V

ref

V

level

o(se)(p-p)

V

o

(V)

MGS556

V_level= 0.5 × V_o(se)(p-p)

.

R1

V_level= V_ref

×

.

----------------------

R1 + R2

Level detector in power-down mode: V_LEVEL1or V_LEVEL2= V_CC

.

a. DC-coupling.

V

CC1A,

V

CC1B,

handbook, full pagewidth

V

CC2A

CC2B

50

Ω

50

Ω

100 Ω

OUT1,

OUT2

V

o

R1

OUT1Q,

OUT2Q

LEVEL1,

LEVEL2

V

level

V

CC

REG

R2

V

ref

V

level

o(se)(p-p)

V

o

(V)

MGL811

V_level= 1.5 × V_o(se)(p-p)

.

R1

R1 + R2

V_level= V_ref

×

.

----------------------

Level detector in power-down mode: V_LEVEL1or V_LEVEL2= V_CC

.

b. AC-coupling.

Fig.7 RF output configurations.

2001 Jun 25

10

Philips Semiconductors

Product speciﬁcation

2.5 Gbits/s dual postampliﬁer with level

detectors and 2 × 2 switch

TZA3019

MGS557

handbook, full pagewidth

1000

V

o(se)(p-p)

(mV)

800

DC-coupled

AC-coupled

600

400

200

0

20

40

60

80

100

V

(% of V

)

ref

level

Fig.8 Output signal as a function of V_level

.

TTL logic input of selector and inverter

The logic levels are differently defined for positive or

Table 2 OUT2 and OUT2Q as function of input S2

S2

OUT2

OUT2Q

negative logic (see Fig.9). It should be noted that positive

logic levels are inverted if a negative supply voltage is

used.

0

1

IN2

IN1

IN2Q

IN1Q

Table 3 OUT1 and OUT1Q as function of input INV1

Outputs as a function of switch input pins S1, S2,

INV1 and INV2

INV1

OUT1

OUT1Q

IN1Q or IN2Q

IN1 or IN2

See Tables 1, 2, 3 and 4.

0

1

IN1 or IN2

The default value for the switch input pins S1, S2, INV1

and INV2 if not connected, is zero.

IN1Q or IN2Q

Table 4 OUT2 and OUT2Q as function of input INV2

Table 1 OUT1 and OUT1Q as function of input S1

INV2

OUT2

OUT2Q

S1

0

OUT1

IN1

OUT1Q

IN1Q

0

1

IN1 or IN2

IN1Q or IN2Q

IN1 or IN2

IN1Q or IN2Q

1

IN2

IN2Q

2001 Jun 25

11

Philips Semiconductors

Product speciﬁcation

2.5 Gbits/s dual postampliﬁer with level

detectors and 2 × 2 switch

TZA3019

logic

level

MGS560

handbook, full pagewidth

2.0 V

(1)

2.0 V

1

0

TTL

0.8 V

1.4 V

V

GND

CC

−1

0

+1

+2

+3

+4

+5

+6

V (V)

I

a. Positive circuit supply voltage V_CCand positive logic supply voltage V_CC

.

handbook, full pagewidth

logic

level

MGS559

2.0 V

1

0

(1)

TTL

0.8 V

1.4 V

V

CC

EE

GND

−4

−3

−2

−1

0

+1

+2

+3

V (V)

I

b. Negative circuit supply voltage V_EEand positive logic supply voltage V_CC

.

handbook, full pagewidth

logic

level

MGS558

2.0 V

(1)

2.0 V

1

0

TTL

0.8 V

1.4 V

V

GND

EE

−4

−3

−2

−1

0

+1

+2

+3

V (V)

I

c. Negative circuit supply voltage V_EEand positive logic supply voltage V_EE

.

(1) Level not defined.

Fig.9 Logic levels on pins S1, S2, INV1 and INV2 as a function of the input voltages.

12

2001 Jun 25

Philips Semiconductors

Product speciﬁcation

2.5 Gbits/s dual postampliﬁer with level

detectors and 2 × 2 switch

TZA3019

RSSI and LOS detection

where S_RSSI= sensitivity (see Chapter “Characteristics”).

The TZA3019 allows AC-signal level detection. This can

prevent the outputs from reacting to noise during the

absence of a valid input signal, and can insure that data

only will be transmitted when the signal-to-noise ratio of

the input signal is sufficient to insure low bit error rate

system operation.

Example: a 200 mV (p-p) single-ended 1.2 GB/s PRBS

signal has an V_RSSIof V_CC− 1.013 V.

ndbook, halfpage3

MGS564

10

The RSSI detection circuit uses seven limiting amplifiers in

a ‘successive detection’ topology to closely approximate

logarithmic response over a total range of 70 dB. The

detectors provide full-wave rectification of the AC signals

presented at each previous amplifier stage. Their outputs

are current drivers. Each cell incorporates a low-pass filter,

being the first step in recovering the average value of the

demodulated signal of the input frequency. The summed

detector output currents are converted to a voltage by an

internal load resistor. This voltage is buffered and

V

i(se)(p-p)

(mV)

2

10

LOS1,

LOS2

LOW-level

(1)

(2)

10

1

LOS1,

LOS2

HIGH-level

(3)

available in the A and B versions of the TZA3019. When

V_RSSIis used V_LOSTHmust not be connected to GND to

prevent the LOS comparator from switching to the standby

mode. The LOS comparator detects an input signal above

a fixed threshold, resulting in a LOW-level at the LOS

circuit output.The threshold level is determined by the

voltage on pins LOSTH1 or LOSTH2 (see Fig.10). A filter

with a time constant of 1 µs nominal is included to prevent

noise spikes from triggering the level detector.

−1

10

20

30

40

, V

50

60

70

V

(% of V

)

LOSTH1 LOSTH2

ref

V

−0.16

V

−0.48

V

−0.8

V

−1.12

CC

V

, V

(V)

RSSI1 RSSI2

The comparator (with internal 3 dB hysteresis) drives an

open-drain circuit with an internal resistor (5 kΩ) for direct

interfacing to positive or negative logic (see Fig.11). Only

available in the B and C versions of the TZA3019.

(1) PRBS pattern input signal with a frequency <1 GHz.

(2) Linearity error typically 0.5 dB.

(3) ϕ = 1/12.5 dB/mV.

The response is independent of the sign of the input signal

because of the particular way the circuit has been built.

This is part of the demodulating nature of the detector,

which results in an alternating input voltage being

transformed to a rectified and filtered quasi DC-output

signal. For the TZA3019 the logarithmic voltage slope is

ϕ = 1/12.5 dB/mV and is essentially temperature and

supply independent through four feedback loops in the

reference circuit. The internal LOS detector output voltage

is based on V_ref. The demodulator characteristic depends

on the waveform and the response depends roughly on

the input signal RMS value. This influences high

frequencies, a square wave input of 2.4 GHz (LOS circuit

bandwidth of 2.4 GHz) offsets the intercept voltage by

20%. V_LOSTHcan be calculated using the following

formula:

Fig.10 Loss of signal assert level.

A full understanding of the offset control loop is useful. The

primary purpose of the loop is to extend the lower end of

the dynamic range in any case where the offset voltage of

the first stage might be high enough to cause later stages

to prematurely enter limiting, caused by the high DC-gain

of the amplifier system. The offset is automatically and

continuously compensated via a feedback path from the

last stage. An offset at the output of the logarithmic

converter is equivalent to a change of amplitude at the

input. Consequently, with DC-coupling, signal absence,

either LOW-level or HIGH-level is detected as a full signal,

only signals with an average value equal to zero give zero

output. Version B can be used for an auto function, which

switches the strongest input signal to output 1 and the

weakest to output 2. To achieve this output V_RSSI2must be

used as the reference voltage for input V_LOSTH. Then the

output LOS1 can switch S1 and S2.

V_LOSTH= V_RSSI

=

V_i(p-p)

V

_CC+ 0.458 – S_RSSI× 20 log

(1)

-------------------

26E – 8

2001 Jun 25

13

Philips Semiconductors

Product speciﬁcation

2.5 Gbits/s dual postampliﬁer with level

detectors and 2 × 2 switch

TZA3019

V

handbook, halfpage

CC

GND

56 kΩ

5.6 kΩ

LOS1,

LOS2

TZA3019

LOS1,

LOS2

TZA3019

5 kΩ

GND1A,

GND2A

GND1A,

GND2A

I

LOS

GND

I

LOS

V

EE

MGS563

MGS562

a. Positive supply and positive logic.

b. Negative supply and positive logic.

GND

handbook, halfpage

56 kΩ

LOS1,

LOS2

TZA3019

5 kΩ

GND1A,

GND2A

I

LOS

V

EE

MGS561

V_CC− V_EE< 7 V.

c. Negative supply and negative logic.

Fig.11 Loss of signal output pins LOS1 and LOS2.

Supply current

(1)

60

For the supply currents I_CC1Band I_CC2B, see Fig.0.

58

I

50

Using a positive supply voltage

CC1B,

CC2B

(mA)

Although the TZA3019 has been designed to use a single

+3.3 V supply voltage (see Fig.13), some care should be

taken with respect to RF transmission lines. The on-chip

signals refer to the various V_CCpins. The external

transmission lines will most likely be referred to the

pins V_GND1A, V_GND2A, V_GND1Band V_GND2B, being the

system ground. The RF signals will change from one

reference plane to another when interfacing the RF inputs

and outputs. A positive supply application is very

vulnerable to interference with respect to this point. For a

successful +3.3 V application, special care should be

taken when designing the PCB layout in order to reduce

the influence of interference and to keep the positive

supply voltage as clean as possible.

40

30

20

17

10

5

0

0.2

0.5

V

0.8

1

(V)

o(se)(p-p)

MGS566

(1) I_CC1Band I_CC2Bat T_amb= 25 °C.

Fig.0 Supply current as a function of output

voltage.

2001 Jun 25

14

Philips Semiconductors

Product speciﬁcation

2.5 Gbits/s dual postampliﬁer with level

detectors and 2 × 2 switch

TZA3019

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

SYMBOL

V_CC

V_n

PARAMETER

MIN.

−0.5

MAX.

+5.5

UNIT

supply voltage

DC voltage

V

pins IN1, IN1Q, IN2, IN2Q, LOSTH1, LOSTH2, LEVEL1, LEVEL2, −0.5

V_CC+ 0.5

V_ref, TEST, OUT2Q, OUT2, OUT1Q, OUT1, GNDp, V_CC1A, V_CC2A

,

V_CC1Band V_CC2B

pins LOS1, LOS2, INV1, INV2, S1 and S2

DC current

−0.5

+7

V

I_n

pins IN1, IN1Q, IN2 and IN2Q

pins LOSTH1, LOSTH2, LEVEL1 and LEVEL2

pins V_ref,TEST, LOS1 and LOS2

pins OUT1, OUT1Q, OUT2 and OUT2Q

pins INV1, INV2, S1 and S2

total power dissipation

−20

0

+20

14

mA

µA

mA

µA

W

−1

−30

0

+1

+30

20

P_tot

T_stg

T_j

−

1.2

storage temperature

−65

−

+150

150

+85

°C

junction temperature

°C

T_amb

ambient temperature

−40

°C

THERMAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

VALUE

UNIT

R_th(j-s)

thermal resistance from junction to

solder point (exposed die pad)

note 1

15

K/W

R_th(j-a)

thermal resistance from junction to

ambient

1s2p multi-layer test board; notes 1

and 2

33

18

R_th(s-a)

thermal resistance from solder point to 1s2p multi-layer test board; notes 1

ambient (exposed die pad)

and 2

R_th(s-a)(req)

required thermal resistance from

solder point to ambient

LOS circuits switched on

V_o= 200 mV (p-p) single-ended;

both output circuits

60

30

K/W

V_o= 800 mV (p-p) single-ended;

both output circuits

Notes

1. JEDEC standard.

2. HTQFP32 and HBCC32 packages.

2001 Jun 25

15

Philips Semiconductors

Product speciﬁcation

2.5 Gbits/s dual postampliﬁer with level

detectors and 2 × 2 switch

TZA3019

CHARACTERISTICS

Typical values at T_amb= 25 °C and V_CC= 3.3 V; minimum and maximum values are valid over the entire ambient

temperature range and supply voltage range; all voltages referenced to ground; note 1; unless otherwise speciﬁed.

SYMBOL

Supply

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

SUPPLY PINS V_CC1A, V_CC1B, V_CC2AAND V_CC2B

V_CC

supply voltage

3.13

3.3

24

40

6

3.47

V

I_CC1A

I_CC2A

,

supply current A

LOS circuit power-down

LOS circuit switched on

ampliﬁer power-down

14

24

2

34

56

10

24

mA

I_CC1B

I_CC2B

supply current B

V_o= 200 mV (p-p)

single-ended; one output

circuit

11

17

V_o= 800 mV (p-p)

single-ended; one output

circuit

43

60

77

mA

P_tot

total power dissipation

power-down

100

200

300

mW

both LOS circuits switched

on

V_o= 200 mV (p-p)

single-ended; both

output circuits

220

450

380

660

555

925

mW

V_o= 800 mV (p-p)

single-ended; both

output circuits

TC

temperature coefﬁcient

LOS circuit switched on;

−80

−50

−30

−15

µA/K

I_CC1A; I_CC2A

V_o= 800 mV (p-p)

single-ended; I_CC1B; I_CC2B

T_j

junction temperature

ambient temperature

−40

−

+125

+85

°C

T_amb

+25

Inputs multiplexer and loss of signal detector

PECL OR CML INPUT PINS IN1, IN1Q, IN2 AND IN2Q

V_i(p-p)

input voltage swing

(peak-to-peak value)

single-ended; notes 2

and 3

50

−

500

mV

V_i(bias)

V_I

DC input bias voltage

V

_CC− 0.4

_CC− 1.0

V

_CC− 0.33 V_CC− 0.28 V

DC and AC input window

voltage

note 3

V

−

V_CC+ 0.3

V

R_i

C_i

input resistance

single-ended

35

50

70

Ω

input capacitance

single-ended; note 3

0.6

0.8

1.2

pF

2001 Jun 25

16

Philips Semiconductors

Product speciﬁcation

2.5 Gbits/s dual postampliﬁer with level

detectors and 2 × 2 switch

TZA3019

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Postampliﬁer

AMPLIFIERS A1A, A1B, A2A AND A2B

G_v

small signal voltage gain

V_o= 200 mV (p-p)

single-ended; note 4

9

15

29

20

34

dB

V_o= 800 mV (p-p)

21

dB

single-ended; note 4

f_D

signal path data rate

notes 5 and 9

−

2.5

5

−

Gbits/s

kHz

f_−3dB(l)

low −3 dB cut-off frequency note 3

2

10

DC compensation

f_−3dB(h)

high −3 dB cut-off

−

2.0

−

GHz

frequency

t_PD

propagation delay

note 3

150

200

0

250

5

ps

∆t_PD

propagation delay

difference

at the same signal levels;

note 3

−

J

total jitter

20 bits of the 28.5 kbits

pattern; notes 3 and 6

−

8

−

ps

α_ct

crosstalk

crosstalk of IC only

110

dB

PECL OR CML OUTPUT PINS OUT1, OUT1Q, OUT2 AND OUT2Q

V_o(se)(p-p)

single-ended output

voltage

(peak-to-peak value)

50 Ω load

200

−

800

+1

mV

TC

temperature coefﬁcient

output level

−1

0

mV/K

t_r

rise time

20% to 80%; notes 5 and 6

80% to 20%; notes 5 and 6

single-ended

−

80

−

ps

Ω

t_f

fall time

−

80

−

R_o

C_o

output resistance

output capacitance

70

0.6

100

0.8

130

1.2

single-ended; note 3

pF

LEVEL CONTROL INPUT PINS LEVEL1 AND LEVEL2

V_i

R_i

input voltage

V

_CC− V_ref

−

V_CC

600

V

input resistance

measured to V_CC1A

or V_CC2A

150

350

kΩ

Multiplexer and inverter switch

PECL OR CML INPUT PINS IN1, IN1Q, IN2 AND IN2Q

α_OS(red)

input offset reduction

V_o= 200 mV (p-p)

single-ended; note 7

3.8

6

9

13.5

22

dB

mV

µV

dB

V_o= 800 mV (p-p)

single-ended; note 7

14

−

V_io(cor)

input offset voltage

correction range

peak-to-peak value;

single-ended

−10

−

+10

170

12

V_{n(i)(eq)(rms)}equivalent input noise

voltage (RMS value)

V_o= 800 mV (p-p)

single-ended; note 3

75

5

Fn

noise factor

note 3

−

2001 Jun 25

17

Philips Semiconductors

Product speciﬁcation

2.5 Gbits/s dual postampliﬁer with level

detectors and 2 × 2 switch

TZA3019

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

SWITCH CIRCUIT

t_a

t_d

assert time

de-assert time

multiplexer and inverter

−

100

−

ns

80

ns

TTL INPUT PINS S1, S2, INV1 AND INV2

V_IL

V_IH

R_i

LOW-level input voltage

HIGH-level input voltage

input resistance

positive logic; note 10

−0.3

2.0

−

+0.8

V

−

V_CC+ 0.8

400

V

measured to GND1A

or GND2A

100

180

kΩ

I_i

input current

−40

−

+40

µA

Received signal strength indicator and loss of signal detector

RSSI AND LOS CIRCUIT

V_i(se)(p-p)

single-ended input voltage

swing (peak-to-peak value)

0.4

400

mV

DR

dynamic range

LOS sensitivity

57

10

9

60

63

dB

S_RSSI

50 MHz, square; note 8

620 MHz, square; note 8

1.2 GHz, square; note 8

12.5

12

15

mV/dB

14

11

13.5

15

100 MB/s PRBS (2³¹− 1);

9

12.5

note 8

1.2 GB/s PRBS (2³¹− 1);

note 8

2.4 GB/s PRBS (2³¹− 1);

note 8

10

−2

12

0

14.5

14

mV/dB

µV/dBK

TC_sens

temperature coefﬁcient

sensitivity

+2

LE

linearity error

see Fig.10; note 3

notes 3 and 7

−

0.5

35

−

1

dB

mV

α_OS(red)

V_io(cor)

input offset reduction

25

−5

50

+5

on-chip DC-offset

compensation correction

range

peak-to-peak value

single-ended

f_−3dB(l)

f_−3dB(h)

low −3 dB cut-off frequency

0.5

1.5

1

2

MHz

GHz

high −3 dB cut-off

note 8

2.5

frequency

LOS CIRCUIT

hys_LOS

LOS hysteresis

input signal waveform

dependency

2.0

3.0

4.0

dB

t_a

t_d

assert time

note 3

−

5

µs

de-assert time

2001 Jun 25

18

Philips Semiconductors

Product speciﬁcation

2.5 Gbits/s dual postampliﬁer with level

detectors and 2 × 2 switch

TZA3019

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

INPUT PINS LOSTH1 AND LOSTH2

V_i

R_i

input voltage

0

−

V_CC

V

input resistance

measured to GND1A

or GND2A

150

350

600

kΩ

OUTPUT PINS LOS1 AND LOS2

I_o(sink)

R_o

output sink current

output resistance

−

1

mA

internal output series

resistance

3.5

5

6.5

kΩ

OUTPUT PINS RSSI1 AND RSSI2

V_o

I_o

output voltage

output current

V

_CC− 1.2

−

V_CC

+1

V

−1

mA

Band gap reference circuit

OUTPUT PIN V_ref

V_ref

reference voltage

V_CC− 1.85 V_CC− 1.6

V_CC− 1.45 V

C_ext

allowed external

capacitance

−

10

pF

I_o(sink)

output sink current

−

500

µA

Notes

1. It is assumed that both CML inputs carry a complementary signal with the specified peak-to-peak value (true

differential excitation).

2. Minimum signal with limiting output.

3. Guaranteed by design.

V_o

4. G_V

=

------

V_i

5. Based on −3dB cut-off frequency.

6. V_i= 100 mV (p-p) single-ended and V_o= 200 mV (p-p) single-ended.

G _AC

7. Input offset reduction =

-----------

G_DC

8. Sensitivity depends on the waveform and is therefore a function of −3 dB cut-off frequency see Equation (1).

9. Low limit can go as low as DC if input signal overrides input offset voltage correction range.

10. When using a negative supply voltage, positive or negative logic can be used. The values will be different (see Fig.9).

2001 Jun 25

19

Philips Semiconductors

Product speciﬁcation

2.5 Gbits/s dual postampliﬁer with level

detectors and 2 × 2 switch

TZA3019

APPLICATION INFORMATION

To minimize low frequency switching noise in the vicinity of

the TZA3019, the power supply line should be filtered once

using a beaded capacitor circuit with a low cut-off

frequency.

RF input and output connections

Striplines, or microstrips, with an odd mode characteristic

impedance of Z_o= 50 Ω have to be used for the differential

RF connections on the PCB. This applies to both the signal

inputs and the signal outputs. The two lines in each pair

should have the same length.

The exposed die pad GNDp connection on the PCB also

needs to be a large copper area to improve heat transfer

to the PCB and thus support IC cooling (see Figs 13

and 14).

Grounding and power supply decoupling

The ground connection on the PCB needs to be a large

copper filled area connected to a common ground plane

with an inductance as low as possible.

2001 Jun 25

20

Philips Semiconductors

Product speciﬁcation

2.5 Gbits/s dual postampliﬁer with level

detectors and 2 × 2 switch

TZA3019

handbook, full pagewidth

2

Boundary of 200 mm area

0

1

2

3

4

5 mm

To central

GND decoupling

0603

V

CC1A

CC1B

OUT1

IN1

IN1Q

V

OUT1Q

V

CC1A

CC1B

V

CC2A

CC2B

IN2

OUT2

IN2Q

V

OUT2Q

V

CC2A

CC2B

0603

To central

GND decoupling

To central

GND decoupling

0603

HTQFP

MGS568

In order to enable heat flow out of the package, the following measures have to be taken:

(1) Solder the 3 × 3 mm²die pad to a plane with maximum size.

(2) Add a plane with minimum 200 mm²in an inner layer, surrounded by ground layers.

(3) Use maximum amount of vias to connect two planes.

(4) Use minimum of openings in heat transport area between hot plane and ground planes.

Fig.13 PCB layout for positive supply voltage.

2001 Jun 25

21

Philips Semiconductors

Product speciﬁcation

2.5 Gbits/s dual postampliﬁer with level

detectors and 2 × 2 switch

TZA3019

handbook, full pagewidth

2

Boundary of 200 mm area

0

1

2

3

4

5 mm

To central

GND decoupling

To central

GND decoupling

0603

V

CC1A

CC1B

OUT1

IN1

IN1Q

OUT1Q

V

CC1A

CC1B

V

CC2A

CC2B

IN2

OUT2

IN2Q

OUT2Q

V

CC2A

CC2B

0603

To central

GND decoupling

To central

GND decoupling

0603

HTQFP

MGS567

In order to enable heat flow out of the package, the following measures have to be taken:

(1) Solder the 3 × 3 mm²die pad to a plane with maximum size.

(2) Add a plane with minimum 200 mm²in an inner layer, surrounded by ground layers.

(3) Use maximum amount of vias to connect two planes.

(4) Use minimum of openings in heat transport area between hot plane and ground planes.

Fig.14 PCB layout for negative supply voltage.

2001 Jun 25

22

Philips Semiconductors

Product speciﬁcation

2.5 Gbits/s dual postampliﬁer with level

detectors and 2 × 2 switch

TZA3019

BONDING PAD LOCATIONS

COORDINATES⁽¹⁾

SYMBOL

OUT2

PAD

x

y

SYMBOL

PAD

x

y

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

+928

+707

+550

+393

+236

+79

−396

−239

−81

V_CC1A

1

2

−928

−707

−550

−393

−236

−79

+710

+553

+396

+239

+81

V_CC2B

n.c.

IN1

IN1Q

3

n.c.

+81

V_CC1A

n.c.

4

V_CC1B

OUT1Q

OUT1

V_CC1B

GND1B

RSSI2

LOS2

RSSI1

LOS1

INV2

+239

+396

+553

+710

+928

5

n.c.

6

−81

V_CC2A

IN2

7

−239

−396

−553

−710

−928

−710

−553

8

IN2Q

9

V_CC2A

GND2A

LOSTH1

LOSTH2

n.c.

10

11

12

13

14

15

16

17

18

19

20

21

22

−79

INV1

−236

−393

−550

−707

LEVEL1

LEVEL2

V_ref

S2

+79

S1

+236

+393

+550

+707

+928

GND1A

n.c.

Note

TEST

GND2B

V_CC2B

OUT2Q

1. All x and y coordinates represent the position of the

centre of the pad in µm with respect to the centre of the

die (see Fig.15).

2001 Jun 25

23

Philips Semiconductors

Product speciﬁcation

2.5 Gbits/s dual postampliﬁer with level

detectors and 2 × 2 switch

TZA3019

handbook, full pagewidth

40 39 38 37 36 35 34 33 32 31

V

1

2

30

29

28

27

26

25

24

23

22

21

CC1A

IN1

CC1B

OUT1

IN1Q

3

OUT1Q

V

4

CC1A

n.c.

CC1B

5

n.c.

x

0

6

n.c.

0

y

V

7

CC2A

IN2

CC2B

8

OUT2

TZA3019U

9

IN2Q

OUT2Q

V

10

CC2A

CC2B

11 12 13 14 15 16 17 18 19 20

MGT030

Fig.15 Bonding pad locations TZA3019U.

2001 Jun 25

24

Philips Semiconductors

Product speciﬁcation

2.5 Gbits/s dual postampliﬁer with level

detectors and 2 × 2 switch

TZA3019

PACKAGE OUTLINES

HTQFP32: plastic, heatsink thin quad flat package; 32 leads; body 5 x 5 x 1.0 mm

SOT547-2

c

y

heathsink side

X

D

h

24

17

A

Z

25

E

16

e

H

E

(A )

3

h

A

2

A

1

w M

p

θ

b

L

p

pin 1 index

L

9

32

detail X

1

8

w M

Z

v

M

A

B

D

b

p

e

D

B

H

v M

D

0

2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

v

w

y

Z

E

θ

1

2

3

p

h

D

E

p

D

max.

0.15 1.05

0.05 0.95

0.27 0.20 5.1

0.17 0.09 4.9

3.1

2.7

5.1

4.9

3.1

2.7

7.1

6.9

7.1

6.9

0.75

0.45

0.89 0.89

0.61 0.61

7°

0°

mm

1.2

0.25

0.5

1.0

0.2 0.08 0.08

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

EIAJ

SOT547-2

99-06-15

2001 Jun 25

25

Philips Semiconductors

Product speciﬁcation

2.5 Gbits/s dual postampliﬁer with level

detectors and 2 × 2 switch

TZA3019

HBCC32: plastic, heatsink bottom chip carrier; 32 terminals; body 5 x 5 x 0.65 mm

SOT560-1

D

x

B

b

w M

1

w M

ball A1

index area

b

3

E

w M

b

w M

2

detail X

x

C

A

B

C

e

1

e

y

v

A

E

e

4

e

2

1

32

A

X

D

1

A

2

e

3

A

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

b

E

e

1

w

b

D

E

e

3

e

4

v

x

y

UNIT

1

2

1

2

3

1

2

max.

0.10 0.70 0.35 0.50 0.50 0.50 5.1

0.05 0.60 0.20 0.30 0.35 0.35 4.9

3.2 5.1

3.0 4.9

3.2

3.0

mm 0.80

0.15 0.15 0.05

0.5

4.2

4.15 4.15

0.2

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

EIAJ

99-09-10

00-02-01

SOT560-1

MO-217

2001 Jun 25

26

Philips Semiconductors

Product speciﬁcation

2.5 Gbits/s dual postampliﬁer with level

detectors and 2 × 2 switch

TZA3019

SOLDERING

If wave soldering is used the following conditions must be

observed for optimal results:

Introduction to soldering surface mount packages

• Use a double-wave soldering method comprising a

turbulent wave with high upward pressure followed by a

smooth laminar wave.

This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in

our “Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).

• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the

transport direction of the printed-circuit board;

There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering can still be used for

certain surface mount ICs, but it is not suitable for fine pitch

SMDs. In these situations reflow soldering is

recommended.

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the

printed-circuit board.

Reﬂow soldering

The footprint must incorporate solder thieves at the

downstream end.

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement.

• For packages with leads on four sides, the footprint must

be placed at a 45° angle to the transport direction of the

printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

Several methods exist for reflowing; for example,

convection or convection/infrared heating in a conveyor

type oven. Throughput times (preheating, soldering and

cooling) vary between 100 and 200 seconds depending

on heating method.

During placement and before soldering, the package must

be fixed with a droplet of adhesive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

Typical reflow peak temperatures range from

215 to 250 °C. The top-surface temperature of the

packages should preferable be kept below 220 °C for

thick/large packages, and below 235 °C for small/thin

packages.

Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

Manual soldering

Wave soldering

Fix the component by first soldering two

diagonally-opposite end leads. Use a low voltage (24 V or

less) soldering iron applied to the flat part of the lead.

Contact time must be limited to 10 seconds at up to

300 °C.

Conventional single wave soldering is not recommended

for surface mount devices (SMDs) or printed-circuit boards

with a high component density, as solder bridging and

non-wetting can present major problems.

When using a dedicated tool, all other leads can be

soldered in one operation within 2 to 5 seconds between

270 and 320 °C.

To overcome these problems the double-wave soldering

method was specifically developed.

2001 Jun 25

27

Philips Semiconductors

Product speciﬁcation

2.5 Gbits/s dual postampliﬁer with level

detectors and 2 × 2 switch

TZA3019

Suitability of surface mount IC packages for wave and reﬂow soldering methods

SOLDERING METHOD

PACKAGE

WAVE

not suitable

REFLOW⁽¹⁾

BGA, HBGA, LFBGA, SQFP, TFBGA

HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS

PLCC⁽³⁾, SO, SOJ

suitable

not suitable⁽²⁾

suitable

LQFP, QFP, TQFP

not recommended⁽³⁾⁽⁴⁾suitable

not recommended⁽⁵⁾

suitable

SSOP, TSSOP, VSO

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package

cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the

Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

DATA SHEET STATUS

PRODUCT

DATA SHEET STATUS⁽¹⁾

DEFINITIONS

STATUS⁽²⁾

Objective data

Development This data sheet contains data from the objective specification for product

development. Philips Semiconductors reserves the right to change the

speciﬁcation in any manner without notice.

Preliminary data

Product data

Qualiﬁcation

This data sheet contains data from the preliminary specification.

Supplementary data will be published at a later date. Philips

Semiconductors reserves the right to change the speciﬁcation without

notice, in order to improve the design and supply the best possible

product.

Production

This data sheet contains data from the product specification. Philips

Semiconductors reserves the right to make changes at any time in order

to improve the design, manufacturing and supply. Changes will be

communicated according to the Customer Product/Process Change

Notiﬁcation (CPCN) procedure SNW-SQ-650A.

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was

published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

2001 Jun 25

28

Philips Semiconductors

Product speciﬁcation

2.5 Gbits/s dual postampliﬁer with level

detectors and 2 × 2 switch

TZA3019

DEFINITIONS

Right to make changes

Philips Semiconductors

reserves the right to make changes, without notice, in the

products, including circuits, standard cells, and/or

software, described or contained herein in order to

improve design and/or performance. Philips

Semiconductors assumes no responsibility or liability for

the use of any of these products, conveys no licence or title

under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that

these products are free from patent, copyright, or mask

work right infringement, unless otherwise specified.

Short-form specification

The data in a short-form

specification is extracted from a full data sheet with the

same type number and title. For detailed information see

the relevant data sheet or data handbook.

Limiting values definition Limiting values given are in

accordance with the Absolute Maximum Rating System

(IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device.

These are stress ratings only and operation of the device

at these or at any other conditions above those given in the

Characteristics sections of the specification is not implied.

Exposure to limiting values for extended periods may

affect device reliability.

Bare die

All die are tested and are guaranteed to

comply with all data sheet limits up to the point of wafer

sawing for a period of ninety (90) days from the date of

Philips' delivery. If there are data sheet limits not

guaranteed, these will be separately indicated in the data

sheet. There are no post packing tests performed on

individual die or wafer. Philips Semiconductors has no

control of third party procedures in the sawing, handling,

packing or assembly of the die. Accordingly, Philips

Semiconductors assumes no liability for device

Application information

Applications that are

described herein for any of these products are for

illustrative purposes only. Philips Semiconductors make

no representation or warranty that such applications will be

suitable for the specified use without further testing or

modification.

functionality or performance of the die or systems after

third party sawing, handling, packing or assembly of the

die. It is the responsibility of the customer to test and

qualify their application in which the die is used.

DISCLAIMERS

Life support applications

These products are not

designed for use in life support appliances, devices, or

systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips

Semiconductors customers using or selling these products

for use in such applications do so at their own risk and

agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

2001 Jun 25

29

Philips Semiconductors

Product speciﬁcation

2.5 Gbits/s dual postampliﬁer with level

detectors and 2 × 2 switch

TZA3019

NOTES

2001 Jun 25

30

Philips Semiconductors

Product speciﬁcation

2.5 Gbits/s dual postampliﬁer with level

detectors and 2 × 2 switch

TZA3019

NOTES

2001 Jun 25

31

Philips Semiconductors – a worldwide company

Argentina: see South America

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. +31 40 27 82785, Fax. +31 40 27 88399

Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,

Tel. +61 2 9704 8141, Fax. +61 2 9704 8139

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. +64 9 849 4160, Fax. +64 9 849 7811

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210

Norway: Box 1, Manglerud 0612, OSLO,

Tel. +47 22 74 8000, Fax. +47 22 74 8341

Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773

Pakistan: see Singapore

Belgium: see The Netherlands

Brazil: see South America

Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,

Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474

Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,

Tel. +359 2 68 9211, Fax. +359 2 68 9102

Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,

Tel. +48 22 5710 000, Fax. +48 22 5710 001

Portugal: see Spain

Romania: see Italy

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,

Tel. +1 800 234 7381, Fax. +1 800 943 0087

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,

72 Tat Chee Avenue, Kowloon Tong, HONG KONG,

Tel. +852 2319 7888, Fax. +852 2319 7700

Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. +7 095 755 6918, Fax. +7 095 755 6919

Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Colombia: see South America

Czech Republic: see Austria

Tel. +65 350 2538, Fax. +65 251 6500

Slovakia: see Austria

Slovenia: see Italy

Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,

Tel. +45 33 29 3333, Fax. +45 33 29 3905

South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

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Tel. +27 11 471 5401, Fax. +27 11 471 5398

Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. +358 9 615 800, Fax. +358 9 6158 0920

France: 7 - 9 Rue du Mont Valérien, BP317, 92156 SURESNES Cedex,

Tel. +33 1 4728 6600, Fax. +33 1 4728 6638

South America: Al. Vicente Pinzon, 173, 6th floor,

04547-130 SÃO PAULO, SP, Brazil,

Tel. +55 11 821 2333, Fax. +55 11 821 2382

Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. +49 40 2353 60, Fax. +49 40 2353 6300

Spain: Balmes 22, 08007 BARCELONA,

Tel. +34 93 301 6312, Fax. +34 93 301 4107

Hungary: Philips Hungary Ltd., H-1119 Budapest, Fehervari ut 84/A,

Tel: +36 1 382 1700, Fax: +36 1 382 1800

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,

Tel. +46 8 5985 2000, Fax. +46 8 5985 2745

India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,

Tel. +91 22 493 8541, Fax. +91 22 493 0966

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,

Tel. +41 1 488 2741 Fax. +41 1 488 3263

Indonesia: PT Philips Development Corporation, Semiconductors Division,

Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,

Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080

Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1,

TAIPEI, Taiwan Tel. +886 2 2134 2451, Fax. +886 2 2134 2874

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,

60/14 MOO 11, Bangna Trad Road KM. 3, Bagna, BANGKOK 10260,

Tel. +66 2 361 7910, Fax. +66 2 398 3447

Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. +353 1 7640 000, Fax. +353 1 7640 200

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,

Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,

TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007

ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813

Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,

Tel. +39 039 203 6838, Fax +39 039 203 6800

252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,

TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057

MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,

Tel. +82 2 709 1412, Fax. +82 2 709 1415

Tel. +1 800 234 7381, Fax. +1 800 943 0087

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. +60 3 750 5214, Fax. +60 3 757 4880

Uruguay: see South America

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Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. +381 11 3341 299, Fax.+381 11 3342 553

Middle East: see Italy

For all other countries apply to: Philips Semiconductors,

Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN,

The Netherlands, Fax. +31 40 27 24825

Internet: http://www.semiconductors.philips.com

72

SCA

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

403510/200/02/pp32

Date of release: 2001 Jun 25

Document order number: 9397 750 08204

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