TN12, TS12 and TYNx12 Series
Fig. 3-2:
Relative variation of thermal
Fig. 4-1: Relative variation of gate trigger
current, holding current and latching versus
junction temperature for TS12 series.
impedance junction to ambient versus pulse
duration (recommended pad layout, FR4 PC
board).
K = [Zth(j-a)/Rth(j-a)]
IGT,IH,IL [Tj] / IGT,IH,IL [Tj = 25 °C]
1.00
2.0
1.8
1.6
1.4
IGT
DPAK
D2PAK
1.2
IH & IL
TO-220AB
0.10
1.0
0.8
0.6
0.4
0.2
0.0
Rgk = 1kΩ
tp(s)
Tj(°C)
40 60
0.01
1E-2
1E-1
1E+0
1E+1
1E+2 5E+2
-40 -20
0
20
80 100 120 140
Fig. 4-2: Relative variation of gate trigger
current, holding current and latching current
versus junction temperature for TN12 & TYN
series.
Fig. 5: Relative variation of holding current
versus gate-cathode resistance (typical values)
for TS12 series.
IH[Rgk] / IH[Rgk = 1k Ω]
IGT,IH,IL [Tj] / IGT,IH,IL [Tj = 25 °C]
5.0
2.4
2.2
Tj = 25°C
4.5
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
IGT
4.0
3.5
3.0
2.5
2.0
1.5
1.0
IH & IL
Tj(°C)
40 60
0.5
Rgk(kΩ)
0.0
-40 -20
0
20
80 100 120 140
1E-2
1E-1
1E+0
1E+1
Fig. 6: Relative variation of dV/dt immunity
versus gate-cathode resistance (typical values)
for TS12 series.
Fig. 7: Relative variation of dV/dt immunity
versus gate-cathode capacitance (typical values)
for TS12 series.
dV/dt[Rgk] / dV/dt [Rgk = 220Ω]
dV/dt[Cgk] / dV/dt [Rgk = 220Ω]
10.0
4.0
Tj = 125°C
VD = 0.67 x VDRM
VD = 0.67 x VDRM
Tj = 125°C
Rgk = 220Ω
3.5
3.0
2.5
2.0
1.5
1.0
1.0
Rgk(kΩ)
0.5
Cgk(nF)
0.1
0.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0
25
50
75
100
125
150
5/10