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CYP15G0401DXA-BGC

型号:

CYP15G0401DXA-BGC

描述:

四路的HOTLink II收发器[ Quad HOTLink II Transceiver ]

品牌:

CYPRESS[ CYPRESS ]

页数:

48 页

PDF大小:

1052 K

PRELIMINARY  
CYP15G0401DXA  
Quad HOTLink II™ Transceiver  
fiber-optic modules  
Features  
copper cables  
• 2nd generation HOTLink® technology  
• Fibre Channel and Gigabit Ethernet compliant 8B/10B-  
coded or 10-bit unencoded  
circuit board traces  
• JTAG boundary scan  
• 8-bit encoded data transport  
• 10-bit unencoded data transport  
• Selectable parity check/generate  
• Selectable multi-channel bonding options  
— Four 8-bit channels  
• Built-In Self-Test (BIST) for at-speed link testing  
• Per-channel Link Quality Indicator  
Analog signal detect  
Digital signal detect  
Frequency range detect  
• Low Power (2.8W typical)  
Single +3.3V VCC supply  
• 256-ball Thermally Enhanced BGA  
0.25µ BiCMOS technology  
— Two 16-bit channels  
— One 32-bit channel  
— N x 32-bit channel support (inter-chip)  
• Selectable input clocking options  
• Selectable output clocking options  
• MultiFrame™ receive framer provides alignment to  
— Bit, byte, half-word, word, multi-word  
Functional Description  
The CYP15G0401DXA Quad HOTLink IITransceiver is a  
point-to-point or point-to-multipoint communications building  
block allowing the transfer of data over high-speed serial links  
(optical fiber, balanced, and unbalanced copper transmission  
lines) at signaling speeds ranging from 200-to-1500 MBaud  
per serial link. The multiple channels in each device may be  
combined to allow transport of wide buses across significant  
distances with minimal concern for offsets in clock phase or  
link delay.  
— COMMA or Full K28.5 detect  
— Single or Multi-byte framer for byte alignment  
— Low-latency option  
• Skew alignment support for multiple bytes of offset  
• Synchronous LVTTL parallel input interface  
• Synchronous LVTTL parallel output interface  
• 200-to-1500 MBaud serial signaling rate  
• Internal PLLs with no external PLL components  
• Dual differential PECL-compatible serial inputs per  
channel  
• Dual differential PECL-compatible serial outputs per  
channel  
Each transmit channel accepts parallel characters in an Input  
Register, encodes each character for transport, and converts  
it to serial data. Each receive channel accepts serial data and  
converts it to parallel data, decodes the data into characters,  
and presents these characters to an output register. Figure 1  
illustrates typical connections between independent host sys-  
tems and corresponding CYP15G0401DXA parts. As a sec-  
ond-generation HOTLink device, the CYP15G0401DXA ex-  
tends the HOTLink family with enhanced levels of integration  
and faster data rates, while maintaining serial-link compatibility  
(data, command, and BIST) with other HOTLink devices.  
— Source matched for 50transmission lines  
— No external bias resistors required  
— Signaling-rate controlled edge-rates  
• Compatible with  
10  
10  
Serial Links  
10  
10  
10  
10  
10  
10  
10  
10  
10  
Serial Links  
10  
10  
10  
10  
10  
Serial Links  
Serial Links  
Backplane or  
Cabled  
Connections  
Figure 1. HOTLink IISystem Connections  
Cypress Semiconductor Corporation  
Document #: 38-02002 Rev. *B  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Revised July 10, 2001  
PRELIMINARY  
CYP15G0401DXA  
The transmit section of the CYP15G0401DXA Quad HOTLink  
II consists of four byte-wide channels that can be operated  
independently or bonded to form wider buses. Each channel  
can accept either 8-bit data characters or pre-encoded 10-bit  
transmission characters. Data characters are passed from the  
Transmit Input Register to an embedded 8B/10B Encoder to  
improve their serial transmission characteristics. These en-  
coded characters are then serialized and output from dual  
Positive ECL (PECL) compatible differential transmission-line  
drivers at a bit-rate of either 10- or 20-times the input reference  
clock.  
For those systems using buses wider than a single byte, the  
four independent receive paths can be bonded together to al-  
low synchronous delivery of data across a two-byte-wide (16-  
bit) path, or across all four bytes (32-bit). Multiple  
CYP15G0401DXA devices may be bonded together to provide  
synchronous transport of buses wider than 32 bits.  
The parallel I/O interface may be configured for numerous  
forms of clocking to provide the highest flexibility in system  
architecture. In additional to clocking the transmit path inter-  
faces from one or multiple sources, the receive interface may  
be configured to present data relative to a recovered clock  
(output) or to a local reference clock (input).  
The receive section of the CYP15G0401DXA Quad HOTLink  
II consists of four byte-wide channels that can be operated  
independently or synchronously bonded for greater band-  
width. Each channel accepts a serial bit-stream from one of  
two PECL-compatible differential line receivers and, using a  
completely integrated PLL Clock Synchronizer, recovers the  
timing information necessary for data reconstruction. Each re-  
covered bit-stream is deserialized and framed into characters,  
8B/10B decoded, and checked for transmission errors. Recov-  
ered decoded characters are then written to an internal Elas-  
ticity Buffer, and presented to the destination host system. The  
integrated 8B/10B encoder/decoder may be bypassed for sys-  
tems that present externally encoded or scrambled data at the  
parallel interface.  
Each transmit and receive channel contains independent  
Built-In Self-Test (BIST) pattern generators and checkers. This  
BIST hardware allows at-speed testing of the high-speed se-  
rial data paths in each transmit and receive section, and  
across the interconnecting links.  
HOTLink-II devices are ideal for a variety of applications where  
parallel interfaces can be replaced with high-speed, point-to-  
point serial links. Some applications include interconnecting  
workstations, backplanes, servers, mass storage, and video  
transmission equipment.  
CYP15G0401DXA Transceiver Logic Block Diagram  
x10  
x10  
x10  
x10  
x11  
x11  
x11  
x11  
Phase  
Align  
Buffer  
Phase  
Align  
Buffer  
Phase  
Align  
Buffer  
Phase  
Align  
Buffer  
Elasticity  
Buffer  
Elasticity  
Buffer  
Elasticity  
Buffer  
Elasticity  
Buffer  
Decoder  
8B/10B  
Decoder  
8B/10B  
Decoder  
8B/10B  
Encoder  
8B/10B  
Decoder  
8B/10B  
Encoder  
8B/10B  
Encoder  
8B/10B  
Encoder  
8B/10B  
Framer  
Framer  
Framer  
Framer  
Serializer  
Serializer  
Deserializer  
Deserializer  
Serializer  
Deserializer  
Serializer  
Deserializer  
RX  
RX  
RX  
RX  
TX  
TX  
TX  
TX  
Document #: 38-02002 Rev. *B  
Page 2 of 48  
PRELIMINARY  
CYP15G0401DXA  
= Internal Signal  
Transmit Path Block Diagram  
REFCLK+  
REFCLK–  
Character-Rate Clock  
Transmit PLL  
Clock Multiplier  
Bit-Rate Clock  
TXRATE  
SPDSEL  
BISTLE  
Character-Rate Clock  
TXCLKO+  
TXCLKO–  
BOE[7:0]  
RBIST[D:A]  
BIST Enable  
Latch  
2
Transmit  
Mode  
TXMODE[1:0]  
Output  
Enable  
Latch  
OELE  
4
TXCKSEL  
TXPERA  
8
SCSEL  
12  
10  
12  
12  
OUTA1+  
OUTA1–  
TXDA[7:0]  
8
TXOPA  
OUTA2+  
OUTA2–  
2
TXCTA[1:0]  
TXLBA  
H M L  
TXCLKA  
TXPERB  
10  
11  
TXDB[7:0]  
8
11  
11  
OUTB1+  
OUTB1–  
TXOPB  
2
OUTB2+  
OUTB2–  
TXCTB[1:0]  
H M L  
TXLBB  
TXCLKB  
TXPERC  
11  
10  
11  
11  
OUTC1+  
OUTC1–  
TXDC[7:0]  
8
TXOPC  
OUTC2+  
OUTC2–  
2
TXCTC[1:0]  
TXLBC  
H M L  
TXCLKC  
TXPERD  
10  
11  
TXDD[7:0]  
8
11  
11  
OUTD1+  
OUTD1–  
TXOPD  
OUTD2+  
OUTD2–  
TXCTD[1:0]  
H M L  
TXLBD  
TXCLKD  
TXRST  
Parity Control  
PARCTL  
Document #: 38-02002 Rev. *B  
Page 3 of 48  
PRELIMINARY  
CYP15G0401DXA  
= Internal Signal  
TRSTZ  
Receive Path Block Diagram  
RXLE  
RX PLL Enable  
Latch  
BOE[7:0]  
TMS  
TCLK  
TDI  
Parity Control  
Character-Rate Clock  
JTAG  
Boundary  
Scan  
SDASEL  
Controller  
TDO  
LPEN  
INSELA  
Receive  
Signal  
Monitor  
LFIA  
INA1+  
INA1–  
8
RXDA[7:0]  
INA2+  
INA2–  
Clock &  
Data  
Recovery  
PLL  
RXOPA  
3
RXSTA[2:0]  
TXLBA  
Clock  
Select  
RXCLKA+  
RXCLKA–  
÷2  
Receive  
Signal  
Monitor  
INSELB  
LFIB  
INB1+  
INB1–  
8
RXDB[7:0]  
INB2+  
INB2–  
Clock &  
Data  
Recovery  
PLL  
RXOPB  
3
TXLBB  
RXSTB[2:0]  
Clock  
Select  
RXCLKB+  
RXCLKB–  
÷2  
Receive  
Signal  
Monitor  
INSELC  
LFIC  
INC1+  
INC1–  
8
RXDC[7:0]  
INC2+  
INC2–  
Clock &  
Data  
Recovery  
PLL  
RXOPC  
3
RXSTC[2:0]  
TXLBC  
Clock  
Select  
RXCLKC+  
RXCLKC–  
÷2  
Receive  
Signal  
Monitor  
LFID  
INSELD  
IND1+  
8
RXDD[7:0]  
IND1–  
IND2+  
IND2–  
Clock &  
Data  
Recovery  
PLL  
RXOPD  
3
RXSTD[2:0]  
TXLBD  
RBIST[D:A]  
Clock  
Select  
RXCLKD+  
RXCLKD–  
÷2  
FRAMCHAR  
RXRATE  
RFEN  
RFMODE  
RXCKSEL  
DECMODE  
2
BONDST  
BOND_ALL  
BOND_INH  
Bonding  
Control  
MASTER  
2
RXMODE[1:0]  
Document #: 38-02002 Rev. *B  
Page 4 of 48  
PRELIMINARY  
CYP15G0401DXA  
Pin Configuration (Top View)  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
INC1-  
OUT  
INC2-  
OUT  
IND1-  
OUT  
IND2-  
OUT  
INA1-  
OUT  
INA2-  
OUT  
INB1-  
OUT  
INB2-  
OUT  
A
B
C
D
E
F
VCC  
VCC  
VCC  
VCC  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
VCC  
VCC  
VCC  
VCC  
C1−  
C2−  
D1−  
D2−  
A1−  
A2−  
B1−  
B2−  
INC1+  
TDI  
OUT  
C1+  
INC2+  
OUT  
C2+  
IND1+  
OUT  
D1+  
IND2+  
BOE[7]  
BOE[6]  
OUT  
D2+  
INA1+  
BOE[3]  
BOE[2]  
OUT  
A1+  
INA2+  
OUT  
A2+  
INB1+  
OUT  
B1+  
INB2+  
LPEN  
RFEN  
OUT  
B2+  
TMS  
INSELC INSELB  
PAR  
CTL  
SDA  
SEL  
BOE[5]  
BOE[4]  
BOE[1]  
BOE[0]  
TX  
MODE  
[0]  
RX  
MODE  
[0]  
TX  
RATE  
RX  
RATE  
TDO  
TCLK  
TRSTZ INSELD INSELA  
RF  
MODE  
SPD  
SEL  
TX  
MODE  
[1]  
RX  
MODE  
[1]  
BOND  
INH  
RXLE  
MAS  
TER  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
TX  
PERC  
TX  
OPC  
TX  
DC[0]  
RXCK  
SEL  
BISTLE  
RX  
STB[1]  
RXOPB  
RX  
STB[0]  
TX  
TXCK  
SEL  
TX  
TX  
DEC  
OELE  
FRAM  
CHAR  
RX  
G
H
J
DC[7]  
DC[4]  
DC[1]  
MODE  
DB[1]  
GND GND GND GND  
GND GND GND GND  
TX  
CTC[1]  
TX  
DC[5]  
TX  
DC[2]  
TX  
DC[3]  
RX  
STB[2]  
RX  
DB[0]  
RX  
DB[5]  
RX  
DB[2]  
RX  
RXCLK  
TX  
LFIC  
RX  
RX  
RX  
RX  
CLK  
B+  
K
L
DC[2]  
C–  
CTC[0]  
DB[3]  
DB[4]  
DB[7]  
RX  
DC[3]  
RXCLK  
C+  
TX  
CLKC  
TX  
DC[6]  
RX  
DB[6]  
LFIB  
RX  
CLK  
B−  
TX  
DB[6]  
RX  
RX  
RX  
RX  
TX  
TX  
TX  
TX  
M
N
P
R
T
DC[4]  
DC[5]  
DC[7]  
DC[6]  
CTB[1]  
CTB[0]  
DB[7]  
CLKB  
GND GND GND GND  
GND GND GND GND  
RX  
DC[1]  
RX  
DC[0]  
RX  
STC[0]  
RX  
STC[1]  
TX  
DB[5]  
TX  
DB[4]  
TX  
DB[3]  
TX  
DB[2]  
RX  
STC[2]  
RX  
OPC  
TX  
PERD  
TX  
OPD  
TX  
DB[1]  
TX  
DB[0]  
TX  
OPB  
TX  
PERB  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
TX  
TX  
TX  
TX  
RX  
RX  
RX  
BOND  
_ALL  
REF  
TXDA[1]  
TXDA[4]  
TX  
RX  
RXOPA  
RX  
RX  
U
V
W
Y
VCC  
VCC  
VCC  
VCC  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
VCC  
VCC  
VCC  
VCC  
DD[0]  
DD[1]  
DD[2]  
CTD[1]  
DD[2]  
DD[1]  
OPD  
CLK  
CTA[0]  
DA[2]  
STA[2]  
STA[1]  
TX  
DD[3]  
TX  
DD[4]  
TX  
CTD[0]  
RX  
DD[6]  
RX  
DD[3]  
RX  
STD[0]  
RX  
STD[2]  
BOND  
ST[0]  
+REF  
CLK  
BOND  
ST[1]  
TXDA[3] TXDA[7]  
TXDA[2] TXDA[6]  
TXDA[0] TXDA[5]  
RX  
DA[7]  
RX  
DA[3]  
RX  
DA[0]  
RX  
STA[0]  
TX  
DD[5]  
TX  
DD[7]  
LFID  
RXCLK  
D–  
RX  
DD[4]  
RX  
STD[1]  
TX  
CLK  
O−  
TXRST  
N/C  
TXOPA  
SCSEL  
LFIA  
RX  
CLK  
A−  
RX  
DA[4]  
RX  
DA[1]  
TX  
DD[6]  
TX  
CLKD  
RX  
DD[7]  
RXCLK  
D+  
RX  
DD[5]  
RX  
DD[0]  
TX  
CLK  
O+  
TX  
CLKA  
TX  
PERA  
TX  
CTA[1]  
RX  
CLK  
A+  
RX  
DA[6]  
RX  
DA[5]  
Document #: 38-02002 Rev. *B  
Page 5 of 48  
PRELIMINARY  
CYP15G0401DXA  
Pin Configuration (Bottom View)  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
OUT  
INB2-  
OUT  
INB1-  
OUT  
INA2-  
OUT  
INA1-  
OUT  
IND2-  
OUT  
IND1-  
OUT  
INC2-  
OUT  
INC1-  
VCC  
VCC  
VCC  
VCC  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
VCC  
VCC  
VCC  
VCC  
A
B
C
D
E
F
B2−  
B1−  
A2−  
A1−  
D2−  
D1−  
C2−  
C1−  
OUT  
B2+  
INB2+  
LPEN  
RFEN  
OUT  
B1+  
INB1+  
OUT  
A2+  
INA2+  
OUT  
A1+  
INA1+  
BOE[3]  
BOE[2]  
OUT  
D2+  
IND2+  
BOE[7]  
BOE[6]  
OUT  
D1+  
IND1+  
OUT  
C2+  
INC2+  
OUT  
C1+  
INC1+  
TDI  
TDO  
RX  
RATE  
TX  
RATE  
RX  
MODE  
[0]  
TX  
MODE  
[0]  
BOE[1]  
BOE[0]  
BOE[5]  
BOE[4]  
SDA  
SEL  
PAR  
CTL  
INSELB INSELC  
TMS  
MAS  
TER  
RXLE  
BOND  
INH  
RX  
MODE  
[1]  
TX  
MODE  
[1]  
SPD  
SEL  
RF  
MODE  
INSELA INSELD TRSTZ  
TCLK  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
RX  
STB[0]  
RXOPB  
RX  
STB[1]  
BISTLE  
RXCK  
SEL  
TX  
DC[0]  
TX  
OPC  
TX  
PERC  
RX  
FRAM  
CHAR  
OELE  
DEC  
TX  
TX  
TXCK  
SEL  
TX  
G
H
J
DB[1]  
MODE  
DC[1]  
DC[4]  
DC[7]  
GND GND GND GND  
GND GND GND GND  
RX  
DB[2]  
RX  
DB[5]  
RX  
DB[0]  
RX  
STB[2]  
TX  
DC[3]  
TX  
DC[2]  
TX  
DC[5]  
TX  
CTC[1]  
RX  
CLK  
B+  
RX  
RX  
RX  
LFIC  
TX  
RXCLK  
RX  
K
L
DB[7]  
DB[4]  
DB[3]  
CTC[0]  
C−  
DC[2]  
TX  
DB[6]  
RX  
CLK  
B−  
LFIB  
RX  
DB[6]  
TX  
DC[6]  
TX  
CLKC  
RXCLK  
C+  
RX  
DC[3]  
TX  
TX  
TX  
TX  
RX  
RX  
RX  
RX  
M
N
P
R
T
CLKB  
DB[7]  
CTB[0]  
CTB[1]  
DC[6]  
DC[7]  
DC[5]  
DC[4]  
GND GND GND GND  
GND GND GND GND  
TX  
DB[2]  
TX  
DB[3]  
TX  
DB[4]  
TX  
DB[5]  
RX  
STC[1]  
RX  
STC[0]  
RX  
DC[0]  
RX  
DC[1]  
TX  
PERB  
TX  
OPB  
TX  
DB[0]  
TX  
DB[1]  
TX  
OPD  
TX  
PERD  
RX  
OPC  
RX  
STC[2]  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
RX  
RX  
RXOPA  
RX  
TX  
TXDA[4]  
TXDA[1]  
REF  
BOND  
_ALL  
RX  
RX  
RX  
TX  
TX  
TX  
TX  
VCC  
VCC  
VCC  
VCC  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
VCC  
VCC  
VCC  
VCC  
U
V
W
Y
STA[1]  
STA[2]  
DA[2]  
CTA[0]  
CLK  
OPD  
DD[1]  
DD[2]  
CTD[1]  
DD[2]  
DD[1]  
DD[0]  
RX  
STA[0]  
RX  
DA[0]  
RX  
DA[3]  
RX  
DA[7]  
TXDA[7] TXDA[3]  
TXDA[6] TXDA[2]  
TXDA[5] TXDA[0]  
BOND  
ST[1]  
+REF  
CLK  
BOND  
ST[0]  
RX  
STD[2]  
RX  
STD[0]  
RX  
DD[3]  
RX  
DD[6]  
TX  
CTD[0]  
TX  
DD[4]  
TX  
DD[3]  
RX  
DA[1]  
RX  
DA[4]  
RX  
CLK  
A−  
LFIA  
SCSEL  
TXOPA  
TXRST  
N/C  
TX  
CLK  
O−  
RX  
STD[1]  
RX  
DD[4]  
RXCLK  
D–  
LFID  
TX  
DD[7]  
TX  
DD[5]  
RX  
DA[5]  
RX  
DA[6]  
RX  
CLK  
A+  
TX  
CTA[1]  
TX  
PERA  
TX  
CLKA  
TX  
CLK  
O+  
RX  
DD[0]  
RX  
DD[5]  
RXCLK  
D+  
RX  
DD[7]  
TX  
CLKD  
TX  
DD[6]  
Document #: 38-02002 Rev. *B  
Page 6 of 48  
PRELIMINARY  
CYP15G0401DXA  
DC Input Voltage ..................................... 0.5V to VCC+0.5V  
Maximum Ratings  
Static Discharge Voltage...............................................> 2001 V  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
(per MIL-STD-883, Method 3015)  
Latch-Up Current...........................................................> 200 mA  
Storage Temperature..................................65°C to +150°C  
Ambient Temperature with  
Power Applied.............................................55°C to +125°C  
Operating Range  
Ambient  
Supply Voltage to Ground Potential............... 0.5V to +4.2V  
Range  
Commercial  
Industrial  
Temperature  
0°C to +70°C  
40°C to +85°C  
VCC  
DC Voltage Applied to LVTTL Outputs  
in High-Z State.........................................0.5V to VCC+0.5V  
+3.3V +5%/5%  
+3.3V +5%/5%  
Output Current into LVTTL Outputs (LOW)..................30 mA  
Pin Descriptions  
CYP15G0401DXA Quad HOTLink II Transceiver  
Name  
I/O Characteristics  
Signal Description  
Transmit Path Data Signals  
TXPERA  
TXPERB  
TXPERC  
TXPERD  
LVTTL Output,  
Transmit Path Parity Error. Active HIGH. Asserted (HIGH) if parity checking is enabled  
changes relative to and a parity error is detected at the encoder. This output is HIGH for one transmit  
REFCLK[1]  
character clock period to indicate detection of a parity error in the character presented  
to the encoder.  
If a parity error is detected, the character in error is replaced with a C0.7 character to  
force a corresponding bad-character detection at the remote end of the link. This re-  
placement takes place regardless of the encoded/non-encoded state of the interface.  
When BIST is enabled for the specific transmit channel, BIST progress is presented on  
these outputs. Once every 511 character times (plus a 16-character Word Sync Se-  
quence when the receive channels are clocked by a common clock), the associated  
TXPERx signal will pulse HIGH for one transmit-character clock period to indicate a  
complete pass through the BIST sequence.  
These outputs also provide indication of a transmit Phase-Align Buffer underflow or  
overflow. When the transmit Phase-Align Buffers are enabled (TXCKSEL LOW, or  
TXCKSEL = LOW and TXRATE = HIGH), if an underflow or overflow condition is detect-  
ed, TXPERx for the channel in error is asserted and remains asserted until either an  
atomic Word Sync Sequence is transmitted or TXRST is sampled LOW to re-center the  
transmit Phase-Align Buffers.  
TXCTA[1:0]  
TXCTB[1:0]  
TXCTC[1:0]  
TXCTD[1:0]  
LVTTL Input,  
synchronous,  
sampled by the  
Transmit Control. These inputs are captured on the rising edge of the transmit interface  
clock (selected by TXCKSEL) and are passed to the encoder or transmit shifter. They  
identify how the associated TXDx[7:0] characters are interpreted. When the encoder is  
selected TXCLKxbypassed, these inputs are interpreted as data bits. When the encoder is enabled, these  
or REFCLK[1]  
inputs determine if the TXDx[7:0] character is encoded as Data, a Special Character  
code, or replaced with other Special Character codes. See Table 1 for details.  
TXDA[7:0]  
TXDB[7:0]  
TXDC[7:0]  
TXDD[7:0]  
LVTTL Input,  
synchronous,  
sampled by the  
selected TXCLKx↑  
or REFCLK[1]  
Transmit Data Inputs. These inputs are captured on the rising edge of the transmit  
interface clock (selected by TXCKSEL) and passed to the encoder or transmit shifter.  
When the encoder is enabled (TXMODE[1:0] LL), TXDx[7:0] specify the specific data  
or command character to be sent.  
TXOPA  
TXOPB  
TXOPC  
TXOPD  
LVTTL Input,  
synchronous,  
internal pull-up,  
sampled by the  
respectiveTXCLKx↑  
or REFCLK[1]  
Transmit Path Odd Parity. When parity checking is enabled (PARCTL LOW), the parity  
captured at these inputs is XORed with the data on the associated TXDx bus to verify  
the integrity of the captured character.  
Note:  
1. When REFCLK is configured for half-rate operation (TXRATE = HIGH), these inputs are sampled (or the outputs change) relative to both the rising and falling  
edges of REFCLK.  
Document #: 38-02002 Rev. *B  
Page 7 of 48  
PRELIMINARY  
CYP15G0401DXA  
Pin Descriptions  
CYP15G0401DXA Quad HOTLink II Transceiver  
Name I/O Characteristics  
TXRST LVTTL Input, asyn- Transmit Clock Phase Reset, active LOW. When LOW, the transmit Phase-Align Buffers  
Signal Description  
chronous,  
are allowed to adjust their data-transfer timing (relative to the selected input clock) to  
allow clean transfer of data from the input register to the encoder or transmit shift reg-  
ister. When TXRST is deasserted (HIGH), the internal phase relationship between the  
associated TXCLKx and the internal character-rate clock is fixed and the device oper-  
ates normally.  
internal pull-up,  
sampled by  
TXCLKAor  
REFCLK[1]  
When configured for half-rate REFCLK sampling of the transmit character stream (TX-  
CKSEL = LOW and TXRATE = HIGH), assertion of TXRST is only used to clear phase  
align buffer faults caused by highly asymmetric REFCLK periods or REFCLKs with  
excessive cycle-to-cycle jitter.  
During this alignment period, one or more characters may be added to or lost from all  
the associated transmit paths as the transmit Phase-Align Buffers are adjusted.  
TXRST must be sampled LOW by a minimum of two consecutive rising edges of TX-  
CLKA (or one REFCLK) to ensure the reset operation is initiated correctly on all chan-  
nels.  
This input is not interpreted when both TXCKSEL and TXRATE are LOW.  
SCSEL  
LVTTL Input,  
synchronous,  
Special Character Select. Used in some transmit modes along with TXCTx[1:0] to en-  
code special characters or to initiate a Word Sync Sequence. When the transmit paths  
internal pull-down, are configured for independent inputs clocks (TXCKSEL = MID), SCSEL is captured  
sampled by  
relative to TXCLKA.  
TXCLKA↑  
or REFCLK[1]  
Transmit Path Clock and Clock Control  
TXCKSEL  
3-Level Select [2]  
Transmit Clock Select. Selects the transmit clock source, used to write data into the  
Static Control Input transmit input register, for the transmit channel(s).  
When LOW, all four input registers are clocked by REFCLK[1]  
.
When MID, TXCLKxis used as the input register clock for TXDx[7:0] and TXCTx[1:0].  
When HIGH, TXCLKAis used to clock data into the input register of each channel.  
TXCLKO±  
LVTTL Output  
Transmit Clock Output. This true and complement output clock is synthesized by the  
transmit PLL and operates synchronous to the internal transmit character clock. It op-  
erates at either the same frequency as REFCLK, or at twice the frequency of REFCLK  
(as selected by TXRATE). TXCLKO± is always equal to the transmit VCO bit-clock  
frequency ÷10. This output clock has no direct phase relationship to REFCLK or any  
recovered character clock.  
TXRATE  
LVTTL Input,  
Transmit PLL Clock Rate Select. When TXRATE = HIGH, the Transmit PLL multiplies  
Static Control input, REFCLK by 20 to generate the serial bit-rate clock. When TXRATE = LOW, the transmit  
internal pull-down  
PLL multiples REFCLK by 10 to generate the serial bit-rate clock. See Table 11 for a list  
of operating serial rates.  
When REFCLK is selected for clocking of the receive parallel interfaces (RXCKSEL =  
LOW), the TXRATE input also determines if the clock on the RXCLKA± and RXCLKC±  
outputs is a full or half-rate clock. When TXRATE = HIGH, these output clocks are half-  
rate clocks and follow the frequency and duty cycle of the REFCLK input. When TXRATE  
= LOW, these output clocks are full-rate clocks and follow the frequency and duty cycle  
of the REFCLK input.  
TXCLKA  
TXCLKB  
TXCLKC  
TXCLKD  
LVTTL Clock Input, Transmit path input clocks. These clocks must be frequency-coherent to TXCLKO± , but  
internal  
may be offset in phase. The internal operating phase of each input clock (relative to  
REFLCK) is adjusted when TXRST = LOW and locked when TXRST = HIGH.  
pull-down  
Note:  
2. 3-Level select inputs are used for static configuration. They are ternary (not binary) inputs that make use of non-standard logic levels of LOW, MID, and HIGH.  
The LOW level is usually implemented by direct connection to VSS (ground). The HIGH level is usually implemented by direct connection to VCC (power). When  
not connected or allowed to float, a 3-Level select input will self-bias to the MID level.  
Document #: 38-02002 Rev. *B  
Page 8 of 48  
PRELIMINARY  
CYP15G0401DXA  
Pin Descriptions  
CYP15G0401DXA Quad HOTLink II Transceiver  
Name I/O Characteristics  
Transmit Path Mode Control  
TXMODE[1:0]  
3-Level Select[2]  
Signal Description  
Transmit Operating Mode. These inputs are interpreted to select one of nine operating  
Static Control inputs modes of the transmit path. See Table 3 for a list of operating modes.  
Receive Path Data Signals  
RXDA[7:0]  
RXDB[7:0]  
RXDC[7:0]  
RXDD[7:0]  
LVTTL Output,  
synchronous to the receive interface clock.  
Parallel Data Output. These outputs change following the rising edge of the selected  
selected RXCLKx↑  
output or  
REFCLK[1] input  
RXSTA[2:0]  
RXSTB[2:0]  
RXSTC[2:0]  
RXSTD[2:0]  
LVTTL Output,  
Parallel Status Output. These outputs change following the rising edge of the selected  
synchronous to the receive interface clock. When the decoder is bypassed, RXSTx[1:0] become the two  
selected RXCLKxlow-order bits of the 10-bit received character, while RXSTx[2] = HIGH indicates the  
output or  
presence of a COMMA character in the output register.  
REFCLK[1] input  
RXOPA  
RXOPB  
RXOPC  
RXOPD  
3-state, LVTTL  
Receive Path Odd Parity. When parity generation is enabled (PARCTL LOW), the  
Output,synchronous parity output at these pins is valid for the data on the associated RXDx bus bits. When  
to the selected  
parity generation is disabled (PARCTL = LOW) these output drivers are disabled  
RXCLKxoutput or (High-Z).  
REFCLK[1] input  
RXRATE  
LVTTL Input  
Static Control Input,  
internal pull-down  
Receive Clock Rate Select.  
When LOW, the RXCLKx± recovered clock outputs are complementary clocks operating  
at the recovered character rate. Data for the associated receive channels should be  
latched on the rising edge of RXCLKx+ or falling edge of RXCLKx.  
When HIGH, the RXCLKx± recovered clock outputs are complementary clocks operat-  
ing at half the character rate. Data for the associated receive channels should be latched  
alternately on the rising edge of RXCLKx+ and RXCLKx.  
When operated with REFCLK clocking of the received parallel data outputs  
(RXCKSEL = LOW), the RXRATE input is not interpreted.  
Receive Path Clock and Clock Control  
RXCLKA±  
RXCLKB±  
RXCLKC±  
RXCLKD±  
3-state, LVTTL  
Output clock or  
Receive Character clock output or clock select input. When the receive Elasticity Buffers  
are disabled (RXCKSEL = MID), these true and complement clocks are the Receive  
Static control input interface clocks which are used to control timing of data output transfers. These clocks  
are output continuously at either the dual-character rate (1/20th the serial bit-rate) or  
character rate (1/10th the serial bit-rate) of the data being received, as selected by  
RXRATE.  
When configured such that all output data paths are clocked by REFCLK instead of a  
recovered clock (RXCKSEL = LOW), the RXCLKA± and RXCLKC± output drivers  
present a buffered form of REFCLK, and RXCLKB+ and RXCLKD+ are static control  
inputs used to select the master channel for bonding and status control. RXCLKA± and  
RXCLKC± are buffered forms of REFCLK that are slightly different in phase. This phase  
difference allows the user to select the optimal setup/hold timing for their specific inter-  
face.  
When dual-channel bonding is enabled and a recovered clock is used to present data  
(RXCKSEL = HIGH), RXCLKA± drives the recovered clock from either receive channel  
A or receive channel B as selected by RXCLKB+, and RXCLKC± drives the recovered  
clock from either receive channel C or receive channel D as selected by RXCLKD+.  
When quad-channel bonding is enabled and a recovered clock is used to present data  
(RXCKSEL = HIGH), RXCLKA± and RXCLKC± output the recovered clock from receive  
channel A, B, C, or D, as selected by RXCLKB+ and RXCLKD+.  
RFEN  
LVTTL input,  
asynchronous,  
internal pull-down  
Reframe Enable for all channels. Active HIGH. When HIGH the framers in all four chan-  
nels are enabled to frame per the presently enabled framing mode.  
Document #: 38-02002 Rev. *B  
Page 9 of 48  
PRELIMINARY  
CYP15G0401DXA  
Pin Descriptions  
CYP15G0401DXA Quad HOTLink II Transceiver  
Name  
I/O Characteristics  
3-Level Select[2]  
Signal Description  
Receive Operating Mode. These inputs are interpreted to select one of nine operating  
RXMODE[1:0]  
Static Control Inputs modes of the receive path. See Table 15 for details.  
RXCKSEL  
3-Level Select[2]  
Static Control Input output registers.  
Receive Clock Mode. Selects the receive clock-source used to transfer data to the  
When LOW, all four output registers are clocked by REFCLK. RXCLKB± and RXCLKD±  
outputs are disabled (High-Z), and RXCLKA± and RXCLKC± present buffered and de-  
layed forms of REFCLK. This clocking mode is required for channel bonding across  
multiple devices.  
When MID, each RXCLKx± output follows the recovered clock for the respective chan-  
nel, as selected by RXRATE.  
When HIGH, and channel bonding is enabled in dual-channel mode (RX modes 3 and  
5), RXCLKA± outputs the recovered clock from either receive channel A or receive  
channel B as selected by RXCLKB+, and RXCLKC± outputs the recovered clock from  
either receive channel C or receive channel D as selected by RXCLKD+. These output  
clocks may operate at the character-rate or half the character-rate as selected by  
RXRATE.  
When HIGH and channel bonding is enabled in quad channel mode (RX modes 6 and  
8), or if the receive channels are operated in independent mode (RX modes 0 and 2),  
RXCLKA± and RXCLKC± output the recovered clock from receive channel A, B, C, or  
D, as selected by RXCLKB+ and RXCLKD+. This output clock may operate at the char-  
acter-rate or half the character-rate as selected by RXRATE.  
FRAMCHAR  
3-Level Select[2]  
Framing Character Select. Used to control the character or portion of a character used  
Static Control Input for character framing of the received data streams.  
When LOW, the framer looks for an 8-bit positive COMMA character in the data stream.  
When MID, the framer looks for both positive and negative disparity versions of the 8-  
bit COMMA character.  
When HIGH, the framer looks for both positive and negative disparity versions of the  
K28.5 character.  
RFMODE  
3-Level Select[2]  
Reframe Mode Select. Used to control the type of character framing used to adjust the  
Static Control Input character boundaries (based on detection of one or more framing characters in the data  
stream). This signal operates in conjunction with the presently enabled channel bonding  
mode, and the type of framing character selected.  
When LOW, the low-latency framer is selected. This will frame on each occurrence of  
the selected framing character(s) in the received data stream. This mode of framing  
stretches the recovered clock for one or multiple cycles to align that clock with the  
recovered data.  
When MID, the Cypress-mode multi-byte parallel framer is selected. This requires a pair  
of the selected framing character(s), on identical 10-bit boundaries, within a span of 50  
bits, before the character boundaries are adjusted. The recovered character clock re-  
mains in the same phasing regardless of character offset.  
When HIGH, the alternate mode multi-byte parallel framer is selected. This requires  
detection of the selected framing character(s) of the allowed disparities in the received  
data stream, on identical 10-bit boundaries, on four directly adjacent characters. The  
recovered character clock remains in the same phasing regardless of character offset.  
DECMODE  
3-Level Select[2]  
Static Control Input  
Decoder Mode Select. This input selects the behavior of the decoder block.  
When LOW, the decoder is bypassed and raw 10-bit characters are passed to the output  
register.  
When MID, the Cypress decoder table for Special Code characters is used.  
When HIGH, the alternate decoder table for Special Code characters is used.  
See Table 25 for a list of the Special Codes supported in both encoded modes.  
Document #: 38-02002 Rev. *B  
Page 10 of 48  
PRELIMINARY  
CYP15G0401DXA  
Pin Descriptions  
CYP15G0401DXA Quad HOTLink II Transceiver  
Name I/O Characteristics  
Device Control Signals  
Signal Description  
PARCTL  
3-Level Select[2]  
Static Control Input functions.  
Parity Check/Generate Control. Used to control the different parity check and generate  
When LOW, parity checking is disabled, and the RXOPx outputs are all disabled  
(High-Z).  
When MID, and the encoder/decoder are enabled (TXMODE[1] L, RXMODE[1] L),  
TXDx[7:0] inputs are checked (along with TXOPx) for valid ODD parity, and ODD parity  
is generated for the RXDx[7:0] outputs and presented on RXOPx. When the encoder  
and decoder are disabled (TXMODE[1] = L, RXMODE[1] = L), theTXDx[7:0] and  
TXCTx[1:0] inputs are checked (along with TXOPx) for valid ODD parity, and ODD parity  
is generated for the RXDx[7:0] and RXSTx[1:0] outputs and presented on RXOPx.  
When HIGH, the and the encoder/decoder are enabled (TXMODE[1] L,  
RXMODE[1] L), the TXDx[7:0] and TXCTx[1:0] inputs are checked (along with  
TXOPx) for valid ODD parity, and ODD parity is generated for the RXDx[7:0] and  
RXSTx[2:0] outputs and presented on RXOPx. When the encoder is and decoder are  
disabled (TXMODE[1] = L, RXMODE[1] = L), theTXDx[7:0] and TXCTx[1:0] inputs are  
checked (along with TXOPx) for valid ODD parity, and ODD parity is generated for the  
RXDx[7:0] and RXSTx[2:0] outputs and presented on RXOPx.  
SPDSEL  
3-Level Select[2]  
,
Serial Rate Select. This input specifies the operating bit-rate range of both transmit and  
static configuration receive PLLs. LOW = 200400 MBd, MID = 400800 MBd, HIGH = 8001500 MBd.  
input  
REFCLK±  
Differential LVPECL Reference Clock. This clock input is used as the timing reference for the transmit and  
or single-ended  
receive PLLs. This input clock may also be selected to clock the transmit and receive  
parallel interfaces. For an LVCMOS or LVTTL input clock, connect REFCLK+ to the  
reference clock and leave REFCLKopen. For an LVPECL differential clock, both inputs  
must be connected.  
LVTTL input clock  
When TXCKSEL = LOW, REFCLK is used as the clock for the parallel transmit data  
(input) interface.  
When RXCKSEL = LOW, REFCLK is used as the clock for the parallel receive data  
(output) interface.  
Analog I/O and Control  
OUTA1±  
OUTB1±  
OUTC1±  
OUTD1±  
CML Differential  
Output  
Primary Differential Serial Data Outputs. These PECL-compatible CML outputs (+3.3V  
referenced) are capable of driving terminated transmission lines or standard fiber-optic  
transmitter modules. These outputs must be AC-coupled for PECL-compatible connec-  
tions.  
OUTA2±  
OUTB2±  
OUTC2±  
OUTD2±  
CML Differential  
Output  
Secondary Differential Serial Data Outputs. These PECL-compatible CML outputs  
(+3.3V referenced) are capable of driving terminated transmission lines or standard  
fiber-optic transmitter modules. These outputs must be AC-coupled for PECL-compati-  
ble connections.  
INA1±  
INB1±  
INC1±  
IND1±  
LVPECL Differential Primary Differential Serial Data Inputs. These inputs accept the serial data stream for  
Input  
deserialization and decoding. The INx1± serial streams are passed to the receiver Clock  
and Data Recovery (CDR) circuits to extract the data content when INSELx = HIGH.  
INA2±  
INB2±  
INC2±  
IND2±  
LVPECL Differential Secondary Differential Serial Data Inputs. These inputs accept the serial data stream  
Input  
for deserialization and decoding. The INx2± serial streams are passed to the receiver  
Clock and Data Recovery (CDR) circuits to extract the data content when  
INSELx = LOW.  
INSELA  
INSELB  
INSELC  
INSELD  
LVTTL Input,  
asynchronous  
Receive Input Selector. Determines which external serial bit stream is passed to the  
receiver Clock and Data Recovery circuit. When HIGH, the INx1± input is selected.  
When LOW, the INx2± input is selected.  
Document #: 38-02002 Rev. *B  
Page 11 of 48  
PRELIMINARY  
CYP15G0401DXA  
Pin Descriptions  
CYP15G0401DXA Quad HOTLink II Transceiver  
Name I/O Characteristics  
SDASEL  
3-Level Select[2]  
Signal Description  
Signal Detect Amplitude Level Select. Allows selection of one of three predefined am-  
,
static configuration plitude trip points for a valid signal indication, as listed in Table 12.  
input  
LPEN  
OELE  
LVTTL Input,  
asynchronous,  
internal pull-down  
All-Port Loop-Back-Enable. Active HIGH. When asserted (HIGH), the transmit serial  
data from each channel is internally routed to the associated receiver Clock and Data  
Recovery (CDR) circuit. All serial drivers are forced to differential logic 1. All serial data  
inputs are ignored.  
LVTTL Input,  
asynchronous,  
internal pull-up  
Serial Driver Output Enable Latch Enable. Active HIGH. When OELE = HIGH, the sig-  
nals on the BOE[7:0] inputs directly control the OUTxy± differential drivers. When the  
BOE[x] input is HIGH, the associated OUTxy± differential driver is enabled. When the  
BOE[x] input is LOW, the associated OUTxy± differential driver is powered down. When  
OELE returns LOW, the last values present on BOE[7:0] are captured in the internal  
Output Enable latch. The specific mapping of BOE[7:0] signals to transmit output en-  
ables is listed in Table 10.  
When the latch is closed, if the device is reset (TRSTZ is sampled LOW), the latch is  
reset to enable all outputs.  
BISTLE  
LVTTL Input,  
asynchronous,  
internal pull-up  
Transmit and Receive BIST Latch Enable. Active HIGH. When BISTLE = HIGH, the  
signals on the BOE[7:0] inputs directly control the transmit and receive BIST enables.  
When BOE[x] input is LOW, the associated transmit or receive channel is configured to  
generate or compare the BIST sequence. When the BOE[x] input is HIGH, the associ-  
ated transmit or receive channel is configured for normal data transmission or reception.  
When BISTLE returns LOW, the last values present on BOE[7:0] are captured in the  
internal BIST Enable latch. The specific mapping of BOE[7:0] signals to transmit and  
receive BIST enables is listed in Table 10.  
When the latch is closed, if the device is reset (TRSTZ is sampled LOW), the latch is  
reset to disable BIST on all transmit and receive channels.  
RXLE  
LVTTL Input,  
asynchronous,  
internal pull-up  
Receive Channel Power-Control Latch Enable. Active HIGH. When RXLE = HIGH, the  
signals on the BOE[7:0] inputs directly control the power enables for the receive PLLs  
and analog logic. When the BOE[7:0] input is HIGH, the associated receive channel A  
through receive channel D PLL and analog logic are active. When the BOE[7:0] input is  
LOW, the associated receive channel A through receive channel D PLL and analog logic  
are placed in a non-functional power saving mode. When RXLE returns LOW, the last  
values present on BOE[7:0] are captured in the internal RX PLL Enable latch. The  
specific mapping of BOE[7:0] signals to the associated receive channel enables is listed  
in Table 10.  
When the latch is closed, if the device is reset (TRSTZ is sampled LOW), the latch is  
reset to enable all receive channels.  
BOE[7:0]  
LVTTL Input,  
asynchronous,  
internal pull-up  
BIST, Serial Output, and Receive Channel Enables.  
These inputs are passed to and through the output enable latch when OELE is HIGH,  
and captured in this latch when OELE returns LOW.  
These inputs are passed to and through the BIST enable latch when BISTLE is HIGH,  
and captured in this latch when BISTLE returns LOW.  
These inputs are passed to and through the Receive Channel enable latch when RXLE  
is HIGH, and captured in this latch when RXLE returns LOW.  
LFIA  
LFIB  
LFIC  
LFID  
LVTTL Output,  
synchronous to the  
selected RXCLKx↑  
output or  
Link Fault Indication output. Active LOW. LFI is the logical OR of four internal conditions:  
1. Received serial data frequency outside expected range  
2. Analog amplitude below expected levels  
REFCLK[1] input,  
asynchronous to  
receive channel  
enable/disable  
3. Transition density lower than expected  
4. Receive Channel disabled  
Document #: 38-02002 Rev. *B  
Page 12 of 48  
PRELIMINARY  
CYP15G0401DXA  
Pin Descriptions  
CYP15G0401DXA Quad HOTLink II Transceiver  
Name  
I/O Characteristics  
Signal Description  
Bonding Control  
BONDST[1:0]  
Bidirectional Open Bonding Status. These signals are only used when multiple devices are bonded togeth-  
Drain,  
internal pull-up  
er. They communicate the status of the present internal bonding and Elasticity Buffer  
management events to the slave devices. These outputs change with the same timing  
as the receive output data buses, but are connected only to all the slave  
CYP15G0401DXA devices.  
When MASTER = LOW, these are output signals and present the Elasticity Buffer status  
from the selected receive channel of the device configured as the master. Receive  
master channel selection is performed using the RXCKB+ and RXCKD+ inputs. These  
status outputs indicate one of four possible conditions, on a synchronous basis, to the  
slave devices. These condition are:  
00Word Sync Sequence received  
01Add one K28.5 immediately following the next framing character received  
10Delete next framing character received  
11Normal data  
These outputs are driven only when the device is configured as a master, all four chan-  
nels are bonded together, and the receive parallel interface is clocked by REFCLK.  
MASTER  
LVTTL Input,  
Master Device Select. When LOW, the present device is configured as the master, and  
static configuration BONDST[1:0] are outputs. When MASTER = HIGH, BONDST[1:0] are inputs.  
input  
internal pull-down  
MASTER is only interpreted when configured for quad channel bonding, and the receive  
parallel interface is clocked by REFCLK.  
BOND_ALL  
BOND_INH  
Bidirectional Open All Channels Bonded Indicator. Active HIGH, wired AND. When HIGH, all receive chan-  
Drain,  
nels have detected valid framing.  
Internal pull-up  
This output is driven only when all four channels are bonded together, and the receive  
parallel interface is clocked by REFCLK.  
LVTTL Input,  
Parallel Bond Inhibit. Active LOW. When asserted (LOW), this signal inhibits the adjust-  
static configuration ment of character offsets in all receive channels if the Bonding Sequence has not been  
input  
detected in all bonded channels.  
Internal pull-up  
When HIGH, all channels that have detected the Bonding Sequence are allowed to align  
their Receive Elasticity Buffer pipelines. For any channels to bond, the selected master  
channel must be a member of the group.  
When multiple devices are used together, the BOND_INH input on all parts must be  
configured the same.  
JTAG Interface  
TMS  
LVTTL Input,  
internal pull-up  
Test Mode Select. Used to control access to the JTAG Test Modes. If maintained high  
for 5 TCLK cycles, the JTAG test controller is reset.  
JTAG Test Clock  
TCLK  
TDO  
TDI  
LVTTL Input,  
internal pull-down  
Three-State  
LVTTL Output  
Test Data Out. JTAG data output buffer which is High-Z while JTAG test mode is not  
selected.  
LVTTL Input,  
Test Data In. JTAG data input port.  
internal pull-up  
Document #: 38-02002 Rev. *B  
Page 13 of 48  
PRELIMINARY  
CYP15G0401DXA  
Pin Descriptions  
CYP15G0401DXA Quad HOTLink II Transceiver  
Name  
TRSTZ  
I/O Characteristics  
Signal Description  
LVTTL Input,  
internal pull-up  
Test Port and Device Reset. Active LOW. Initializes the JTAG controller and all state  
machines and counters in the device.  
When asserted (LOW), this input asynchronously resets the JTAG test access port  
controller.  
When sampled LOW by the rising edge of REFLCK, this input resets the internal state  
machines and sets the Elasticity Buffer pointers to a nominal offset. When the reset is  
removed (TRSTZ sampled HIGH by REFCLK), the status and data outputs will be-  
come deterministic in less than 16 REFCLK cycles.  
The BISTLE, OELE, and RXLE latches will be reset by TRSTZ.  
Power  
VCC  
+3.3V Power  
GND  
Signal and Power Ground for all internal circuits.  
Document #: 38-02002 Rev. *B  
Page 14 of 48  
PRELIMINARY  
CYP15G0401DXA  
TXCLKA. While the value on SCSEL still effects all channels,  
it is interpreted when the character containing it is read from  
the transmit Phase-Align Buffer (where all four paths are inter-  
nally clocked synchronously).  
CYP15G0401DXA HOTLink-II Operation  
The CYP15G0401DXA is a highly configurable device de-  
signed to support reliable transfer of large quantities of data,  
using high-speed serial links, from one or multiple sources to  
one or multiple destinations. This device supports four single-  
byte or single-character channels that may be combined to  
support transfer of wider buses.  
Phase-Align Buffer  
Data from the input registers is passed either to the encoder  
or to the associated Phase-Align buffer. When the transmit  
paths are operated synchronous to REFCLK(TXCKSEL = L  
and TXRATE = LOW), the Phase-Align Buffers are bypassed  
and data is passed directly to the parity check and encoder  
blocks to reduce latency.  
CYP15G0401DXA Transmit Data Path  
Operating Modes  
The transmit path of the CYP15G0401DXA supports four  
character-wide data paths. These data paths are used in mul-  
tiple operating modes as controlled by the TXMODE[1:0] in-  
puts.  
When an Input-Register clock with an uncontrolled phase re-  
lationship to REFCLK is selected (TXCKSEL L) or if data is  
captured on both edges of REFCLK (TXRATE = HIGH), the  
Phase-Align Buffers are enabled. These buffers are used to  
absorb clock phase differences between the presently select-  
ed input clock and the internal character clock.  
Input Register  
Within these operating modes, the bits in the Input Register for  
each channel support different bit assignments, based on if the  
character is unencoded, encoded with two control bits, or en-  
coded with three control bits. These assignments are shown  
in Table 1.  
Initialization of these phase-align buffers takes place when the  
TXRST input is sampled LOW by TXCLKA. When TXRST is  
returned HIGH, the present input clock phase relative to  
REFCLKis set. TXRST is an asynchronous input, but is sam-  
pled internally to synchronize it to the internal transmit path  
state machines. TXRST must be sampled LOW by a minimum  
of two consecutive TXCLKAclocks to ensure the reset oper-  
ation is initiated correctly on all channels.  
Table 1. Input Register Bit Assignments[3]  
Encoded  
2-bit  
3-bit  
Once set, the input clocks are allowed to skew in time up to  
half a character period in either direction relative to REFCLK;  
i.e., ± 180°. This time shift allows the delay paths of the char-  
acter clocks (relative to REFLCK) to change due to operating  
voltage and temperature, while not affecting the design oper-  
ation.  
Signal Name  
TXDx[0] (LSB)  
TXDx[1]  
Unencoded  
DINx[0]  
DINx[1]  
DINx[2]  
DINx[3]  
DINx[4]  
DINx[5]  
DINx[6]  
DINx[7]  
DINx[8]  
DINx[9]  
N/A  
Control  
Control  
TXDx[0]  
TXDx[1]  
TXDx[2]  
TXDx[3]  
TXDx[4]  
TXDx[5]  
TXDx[6]  
TXDx[7]  
TXCTx[0]  
TXCTx[1]  
N/A  
TXDx[0]  
TXDx[1]  
TXDx[2]  
TXDx[3]  
TXDx[4]  
TXDx[5]  
TXDx[6]  
TXDx[7]  
TXCTx[0]  
TXCTx[1]  
SCSEL  
TXDx[2]  
TXDx[3]  
If the phase offset, between the initialized location of the input  
clock and REFCLK, exceeds the skew handling capabilities  
of the Phase-Align Buffer, an error is reported on the associ-  
ated TXPERx output. This output will indicate a continuous  
error until the Phase-Align Buffer is reset. While the error re-  
mains active, the transmitter for the associated channel will  
output a continuous C0.7 character to indicate to the remote  
receiver that an error condition is present in the link.  
TXDx[4]  
TXDx[5]  
TXDx[6]  
TXDx[7]  
TXCTx[0]  
TXCTx[1] (MSB)  
SCSEL  
In specific transmit modes it is also possible to reset the  
Phase-Align Buffers individually and with minimal disruption of  
the serial data stream. When the transmit interface is config-  
ured for generation of atomic Word Sync Sequences  
(TXMODE[1] = M) and a Phase-Align Buffer error is present,  
the transmission of a Word Sync Sequence will re-center the  
buffer and clear the error condition.  
Each input register captures a minimum of eight data bits and  
two control bits on each input clock cycle. When the encoder  
is bypassed, the control bits are part of the pre-encoded 10-bit  
character.  
When the Encoder is enabled (TXMODE[1] L), the  
TXCTx[1:0] bits are interpreted along with the associated  
TXDx[7:0] character to generate the specific 10-bit transmis-  
sion character. When TXMODE[0] H, an additional special  
character select (SCSEL) input is also captured and interpret-  
ed. This SCSEL input is used to modify the encoding of the  
associated characters. When the transmit input registers are  
clocked by a common clock (TXCLKAor REFCLK), this  
SCSEL input can be changed on a clock-by-clock basis and  
effects all four channels.  
NOTE: One or more K28.5 characters may be added or lost  
from the data stream during this reset operation. When  
used with non-Cypress devices that require a complete 16-  
character Word Sync Sequence for proper receive Elastic-  
ity Buffer alignment, it is recommend that the sequence be  
followed by a second Word Sync Sequence to ensure prop-  
er operation.  
Parity Support  
In addition to the ten data and control bits that are captured at  
each channel, a TXOPx input is also available on each chan-  
nel. This allows the CYP15G0401DXA to support ODD parity  
When operated with a separate input clock on each transmit  
channel, this SCSEL input is sampled synchronous to  
Note:  
3. The TXOPx inputs are also captured in the associated input register, but their interpretation is under the separate control of PARCTL.  
Document #: 38-02002 Rev. *B  
Page 15 of 48  
PRELIMINARY  
CYP15G0401DXA  
checking for each channel. This parity checking is available for  
all operating modes (including Encoder Bypass). The specific  
mode of parity checking is controlled by the PARCTL input,  
and operates per Table 2.  
the 10-bit equivalent of the C0.7 SVS character if a Phase-  
Align Buffer overflow or underflow error is present  
a character that is part of the 511-character BIST sequence  
a K28.5 character generated as an individual character or  
as part of the 16-character Word Sync Sequence.  
Table 2. Input Register Bits Checked for Parity [5]  
Transmit Parity Check Mode (PARCTL)  
The selection of the specific characters generated are con-  
trolled by the TXMODE[1:0], SCSEL, TXCTx[1:0], and  
TXDx[7:0] inputs for each character.  
LOW  
MID  
HIGH  
Data Encoding  
Signal  
Name  
TXMODE[1] TXMODE[1]  
= LOW  
LOW  
Raw data, as received directly from the Transmit Input Regis-  
ter, is seldom in a form suitable for transmission across a serial  
link. The characters must usually be processed or transformed  
to guarantee  
TXDx[0]  
TXDx[1]  
TXDx[2]  
TXDx[3]  
TXDx[4]  
TXDx[5]  
TXDx[6]  
TXDx[7]  
TXCTx[0]  
TXCTx[1]  
TXOPx  
X [4]  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
aminimumtransitiondensity(toallowtheserialreceivePLL  
to extract a clock from the data stream)  
a DC-balance in the signaling (to prevent baseline wander)  
run-length limits in the serial data (to limit the bandwidth of  
the link)  
the remote receiver a way of determining the correct char-  
acter boundaries (framing).  
X
X
X
X
X
When the Encoder is enabled (TXMODE[1] L), the charac-  
ters to be transmitted are converted from Data or Special  
Character codes to 10-bit transmission characters (as select-  
ed by their respective TXCTx[1:0] and SCSEL inputs), using  
an integrated 8B/10B encoder. When directed to encode the  
character as a Special Character code, it is encoded using the  
Special Character encoding rules listed in Table 25. When di-  
rected to encode the character as a Data character, it is en-  
coded using the Data Character encoding rules in Table 24.  
X
X
X
X
When PARCTL is MID (open) and the encoders are enabled  
(TXMODE[1] L), only the TXD[7:0] data bits are checked for  
ODD parity along with the associated TXOPx bit. When  
PARCTL = HIGH with the encoder enabled (or MID with the  
encoder bypassed), the TXDx[7:0] and TXCTx[1:0] inputs are  
checked for ODD parity along with the associated TXOPx bit.  
When PARCTL = LOW, parity checking is disabled.  
The 8B/10B encoder is standards compliant with ANSI/NCITS  
ASC X3.230-1994 (Fibre Channel), IEEE 802.3z (Gigabit  
Ethernet), the IBMESCONand FICONchannels, and  
ATM Forum standards for data transport.  
When parity checking and the encoder are both enabled  
(TXMODE[1] L), the detection of a parity error causes a C0.7  
character of proper disparity to be passed to the transmit  
shifter. When the encoder is bypassed (TXMODE[1] = L), de-  
tection of a parity error causes a positive disparity version of a  
C0.7 transmission character to be passed to the transmit  
shifter.  
Many of the Special Character codes listed in Table 25 may be  
generated by more than one input character. The  
CYP15G0401DXA is designed to support two independent  
(but non-overlapping) Special Character code tables. This al-  
lows the CYP15G0401DXA to operate in mixed environments  
with other CYP15G0401DXAs using the enhanced Cypress  
command code set, and the reduced command sets of other  
non-Cypress devices. Even when used in an environment that  
normally uses non-Cypress Special Character codes, the se-  
lective use of Cypress command codes can permit operation  
where running disparity and error handling must be managed.  
Encoder  
The character, received from the input register or phase-align  
buffer and parity check logic, is then passed to the Encoder  
logic. This block interprets each character and any associated  
control bits, and outputs a 10-bit transmission character.  
Following conversion of each input character from 8 bits to a  
10-bit transmission character, it is passed to the Transmit  
Shifter and is shifted out LSB first, as required by ANSI and  
IEEE standards for 8B/10B coded serial data streams.  
Depending on the configured operating mode, the generated  
transmission character may be  
the 10-bit pre-encoded character accepted in the input reg-  
ister  
the 10-bit equivalent of the 8-bit Data character accepted in  
the input register  
the 10-bit equivalent of the 8-bit Special Character code  
accepted in the input register  
the 10-bit equivalent of the C0.7 SVS character if parity  
checking was enabled and a parity error was detected  
Transmit Modes  
The operating mode of the transmit path is set through the  
TXMODE[1:0] inputs. These 3-level select inputs allow one of  
nine transmit modes to be selected. Within each of these op-  
erating modes, the actual characters generated by the Encod-  
er logic block are also controlled both by these and other static  
Note:  
4. Bits marked as X are XORed together. Result must be a logic-1 for parity to be valid.  
5. Transmit path parity errors are reported on the associated TXPERx output.  
Document #: 38-02002 Rev. *B  
Page 16 of 48  
PRELIMINARY  
CYP15G0401DXA  
and dynamic control signals. The transmit modes are listed in  
Table 4. Encoder Bypass Mode (TXMODE[1:0] = LL)  
Table 3.  
Signal Name  
TXDx[0] (LSB)  
TXDx[1]  
Bus Weight  
10B Name  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
a[6]  
b
c
d
e
i
Table 3. Transmit Operating Modes  
TX Mode Operating Mode  
TXDx[2]  
Word Sync  
TXDx[3]  
Sequence  
Support  
SCSEL  
Control  
TXDx[4]  
TXCTx Function  
Encoder Bypass  
Reserved for test  
Reserved for test  
Encoder Control  
TXDx[5]  
0
1
2
3
LL None  
None  
None  
None  
TXDx[6]  
f
LM None  
LH None  
ML Atomic  
TXDx[7]  
g
h
j
TXCTx[0]  
TXCTx[1] (MSB)  
Special  
Character  
4
5
6
MM Atomic  
MH Atomic  
Word Sync Encoder Control  
These bits combine to control the interpretation of the  
TXDx[7:0] bits and the characters generated by them. These  
bits are interpreted as listed in Table 5.  
None  
Encoder Control  
Encoder Control  
HL Interruptible Special  
Character  
Table 5. TX Modes 3 and 6 Encoding  
7
8
HM Interruptible Word Sync Encoder Control  
HH Interruptible None Encoder Control  
The encoded modes (TX Modes 3 through 8) support multiple  
encoding tables. These encoding tables vary by the specific  
combinations of SCSEL, TXCTx[1], and TXCTx[0] that are  
used to control the generation of data and control characters.  
These multiple encoding forms allow maximum flexibility in in-  
terfacing to legacy applications, while also supporting numer-  
ous extensions in capabilities.  
Characters Generated  
X
0
1
X
X
0
0
1
0
1
1
1
Encoded data character  
K28.5 fill character  
Special character code  
16-character Word Sync Sequence  
TX Mode 0—Encoder Bypass  
When TXCKSEL = M, all transmit channels capture data into  
their input registers using independent TXCLKx clocks. The  
SCSEL input is sampled only by TXCLKA. When the charac-  
ter (accepted in the Channel-A Input Register) has passed  
through the Phase-Align Buffer and any selected parity valida-  
tion, the level captured on SCSEL is passed to the Encoder of  
the remaining channels during this same cycle.  
When the Encoder is bypassed, the character captured in the  
TXDx[7:0] and TXCTx[1:0] inputs is passed directly to the  
transmit shifter without modification. If parity checking is en-  
abled (PARCTL LOW) and a parity error is detected, the 10-  
bit character is replaced with the 1001111000 pattern (+C0.7  
character) regardless of the running disparity of the previous  
character.  
To avoid the possible ambiguities that may arise due to the  
uncontrolled arrival of SCSEL relative to the characters in the  
alternate channels, SCSEL is often used as a static configura-  
tion input.  
With the encoder bypassed, the TXCTx[1:0] inputs are consid-  
ered part of the data character and do not perform a control  
function that would otherwise modify the interpretation of the  
TXDx[7:0] bits. The bit usage and mapping of these control bits  
when the Encoder is bypassed is shown in Table 4.  
Word Sync Sequence  
When TXCTx[1:0] = 11, a 16-character sequence of K28.5  
characters, known as a Word Sync Sequence, is generated on  
the associated channel. This sequence of K28.5 characters  
may start with either a positive or negative disparity K28.5 (as  
determined by the current running disparity and the 8B/10B  
coding rules). The disparity of the second and third K28.5  
characters in this sequence are reversed from what normal  
8B/10B coding rules would generate. The remaining K28.5  
characters in the sequence follow all 8B/10B coding rules. The  
disparity of the generated K28.5 characters in this sequence  
would follow a pattern of either ++––++++++or  
––++++++++.  
In this mode the SCSEL input is not interpreted. All clocking  
modes interpret the data the same, with no internal linking  
between channels.  
TX Modes 1 and 2—Factory Test Modes  
These modes enable specific factory test configurations. They  
are not considered normal operating modes of the device. En-  
try or configuration into these test modes will not damage the  
device.  
TX Mode 3—Atomic Word Sync andSCSEL Control of Special  
Codes  
When TXMODE[1] = M (open, TX modes 3, 4, and 5), the  
generation of this character sequence is an atomic (non-inter-  
When configured in TX Mode 3, the SCSEL input is captured  
along with the associated TXCTx[1:0] data control inputs.  
Note:  
6. LSB is shifted out first.  
Document #: 38-02002 Rev. *B  
Page 17 of 48  
PRELIMINARY  
CYP15G0401DXA  
ruptible) operation. Once it has been successfully started, it  
cannot be stopped until all 16 characters have been generat-  
ed. The content of the associated input register(s) is ignored  
for the duration of this 16-character sequence. At the end of  
this sequence, if the TXCTx[1:0] = 11 condition is sampled  
again, the sequence restarts and remains uninterruptible for  
the following 15 character clocks.  
Table 6. TX Modes 4 and 7 Encoding  
Characters Generated  
Encoded data character  
X
0
0
1
X
0
1
X
0
1
1
1
If parity checking is enabled, the character used to start the  
Word Sync Sequence must also have correct ODD parity. This  
is true even though the contents of the TXDx[7:0] bits do not  
directly control the generation of characters during the Word  
Sync Sequence. Once the sequence is started, parity is not  
checked on the following 15 characters in the Word Sync Se-  
quence.  
K28.5 fill character  
Special character code  
16-character Word Sync Sequence  
alternate channels, SCSEL is often used as a static configura-  
tion input.  
When TXMODE[1] = H (TX modes 6, 7, and 8), the generation  
of the Word Sync Sequence becomes an interruptible opera-  
tion. In TX Mode 6, this sequence is started as soon as the  
TXCTx[1:0] = 11 condition is detected on a channel. In order  
for the sequence to continue on that channel, the TXCTx[1:0]  
inputs must be sampled as 00 for the remaining 15 characters  
of the sequence.  
TX Mode 4 also supports an Atomic Word Sync Sequence.  
Unlike TX Mode 3, this sequence is started when both SCSEL  
and TXCTx[0] are sampled HIGH. With the exception of the  
combination of control bits used to initiate the sequence, the  
generation and operation of this Word Sync Sequence is the  
same as that documented for TX Mode 3.  
TX Mode 5Atomic Word Sync, No SCSEL  
If at any time a sample period exists where TXCTx[1:0] 00,  
the Word Sync Sequence is terminated, and a character rep-  
resenting the associated data and control bits is generated by  
the Encoder. This resets the Word Sync Sequence state ma-  
chine such that it will start at the beginning of the sequence at  
the next occurrence of TXCTx[1:0] = 11.  
When configured in TX Mode 5, the SCSEL signal is not used.  
In addition to the standard character encodings, both with and  
without atomic Word Sync Sequence generation, two addition-  
al encoding mappings are controlled by the Channel Bonding  
selection made through the RXMODE[1:0] inputs.  
For non-bonded operation, the TXCTx[1:0] inputs for each  
channel control the characters generated by that channel. The  
specific characters generated by these bits are listed in  
Table 7.  
When parity checking is enabled and TXMODE[1] = H, all  
characters (including those in the middle of a Word Sync Se-  
quence) must have correct parity. The detection of a character  
with incorrect parity during a Word Sync Sequence (regard-  
less of the state of TXCTx[1:0]) will interrupt that sequence  
and force generation of a C0.7 SVS character. Any interruption  
of the Word Sync Sequence causes the sequence to termi-  
nate.  
Table 7. TX Modes 5 and 8 Encoding, Non-Bonded  
When TXCKSEL = L, the input registers for all four transmit  
channels are clocked by REFCLK [1]. When TXCKSEL = H,  
the input registers for all four transmit channels are clocked  
with TXCLKA. In these clock modes all four sets of  
Characters Generated  
X
X
X
X
0
0
1
1
0
1
0
1
Encoded data character  
K28.5 fill character  
TXCTx[1:0] inputs operate synchronous to the SCSEL input.  
NOTE: When operated in any configuration where receive  
channels are bonded together, TXCKSEL must be either  
LOW or HIGH (nor MID) to ensure that associated charac-  
ters are transmitted in the same character cycle.  
Special character code  
16-character Word Sync Sequence  
TX Mode 5 also has the capability of generating an Atomic  
Word Sync Sequence. For the sequence to be started, the  
TXCTx[1:0] inputs must both be sampled HIGH. With the ex-  
ception of the combination of control bits used to initiate the  
sequence, the generation and operation of this Word Sync Se-  
quence is the same as that documented for TX Mode 3.  
TX Mode 4Atomic Word Sync and SCSEL Control of  
Word Sync Sequence Generation  
When configured in TX Mode 4, the SCSEL input is captured  
along with the associated TXCTx[1:0] data control inputs.  
These bits combine to control the interpretation of the  
TXDx[7:0] bits and the characters generated by them. These  
bits are interpreted as listed in Table 6.  
Two additional encoding maps are provided for use when re-  
ceive channel bonding is enabled. When dual-channel bond-  
ing is enabled (RXMODE[1] = M), the CYP15G0401DXA is  
configured such that channels A and B are bonded together to  
form a two-character-wide path, and channels C and D are  
bonded together to form a second two-character-wide path.  
When TXCKSEL = M, all transmit channels operate indepen-  
dently. The SCSEL input is sampled only by TXCKA. When  
the character accepted in the Channel-A Input Register has  
passed any selected validation and is ready to be passed to  
the Encoder, the level captured on SCSEL is passed to the  
encoders of the remaining channels during this same cycle.  
When operated in this two-channel bonded mode, the  
TXCTA[0] and TXCTB[0] inputs control the interpretation of the  
data on both the A and B channels, while the TXCTC[0] and  
TXCTD[0] inputs control the interpretation of the data on both  
the C and D channels. The characters on each half of these  
bonded channels are controlled by the associated TXCTx[1]  
To avoid the possible ambiguities that may arise due to the  
uncontrolled arrival of SCSEL relative to the characters in the  
Document #: 38-02002 Rev. *B  
Page 18 of 48  
PRELIMINARY  
CYP15G0401DXA  
bit. The specific characters generated by these control bit com-  
binations are listed in Table 8.  
Table 8. TX Modes 5 and 8, Dual-Channel Bonded  
Characters Generated  
Encoded data character on channel A  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
1
X
X
X
X
0
0
0
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
1
K28.5 fill character on channel A  
1
0
0
Special character code on channel A  
16-character word sync on channel A  
Encoded data character on channel B  
K28.5 fill character on channel B  
1
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
0
0
0
1
0
Special character code on channel B  
16-character word sync on channel B  
1
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
16-character word sync on channels A and B  
Encoded data character on channel C  
K28.5 fill character on channel C  
X
X
X
X
X
X
X
X
X
0
1
1
0
Special character code on channel C  
16-character word sync on channel C  
Encoded data character on channel D  
K28.5 fill character on channel D  
1
1
X
X
X
X
X
0
1
0
0
1
Special character code on channel D  
16-character word sync on channel D  
16-character word sync on channels C and D  
1
1
X
X
Note especially that any time TXCTB[0] is sampled HIGH, both  
channels A and B start generating an Atomic Word Sync Se-  
quence, regardless of the state of any of the other bits in the  
A or B input registers (with the exception of any enabled parity  
checking). In a similar fashion, anytime TXCTD[0] is sampled  
HIGH, both the C and D channels start generation of an Atom-  
ic Word Sync Sequence.  
tion symbols. This provides a predictable yet pseudo-random  
sequence that can be matched to an identical LFSR in the  
attached Receiver(s).  
When the BISTLE signal is HIGH, any BOE[x] input that is  
LOW enables the BIST generator in the associated transmit  
channel (or the BIST checker in the associated receive chan-  
nel). When BISTLE returns LOW, the values of all BOE[x] sig-  
nals are captured in the BIST Enable Latch. These values re-  
main in the BIST Enable Latch until BISTLE is returned high  
to open the latch again. All captured signals in the BIST Enable  
Latch are set HIGH (i.e., BIST is disabled) following a a device  
reset (TRSTZ is sampled LOW).  
When RXMODE[1] = H, the CYP15G0401DXA is configured  
for quad-channel bonding, such that channels A, B, C, and D  
are bonded together to form a four-character-wide path. When  
operated in this mode, the TXCTA[0] and TXCTB[0] inputs  
control the interpretation of the data on all four channels. The  
characters generated on these bonded channels are con-  
trolled by the associated TXCTx[1] bit. The specific characters  
generated by these bits are listed in Table 9.  
All data and data-control information present at the associated  
TXDx[7:0] and TXCTx[1:0] inputs are ignored when BIST is  
active on that channel. If the receive channels are configured  
for common clock operation (RXCKSEL MID) each pass is  
preceded by a 16-character Word Sync Sequence to allow  
Elasticity Buffer alignment and management of clock-frequen-  
cy variations.  
Unlike dual-channel modes, when all four channels are bond-  
ed together, the TXCTC[0] and TXCTD[0] inputs are not inter-  
preted.  
Transmit BIST  
Serial Output Drivers  
The transmitter interfaces contain internal pattern generators  
that can be used to validate both device and link operation.  
These generators are enabled by the associated BOE[x] sig-  
nals listed in Table 10 (when the BISTLE latch enable input is  
HIGH). When enabled, a register in the associated transmit  
channel becomes a signature pattern generator by logically  
converting to a Linear Feedback Shift Register (LFSR). This  
LFSR generates a 511-character sequence that includes all  
Data and Special Character codes, including the explicit viola-  
The serial interface Output Drivers make use of high-perfor-  
mance differential CML (Current Mode Logic) to provide a  
source-matched driver for the transmission lines. These driv-  
ers accept data from the Transmit Shifters. These outputs  
have signal swings equivalent to that of standard PECL driv-  
ers, and are capable of driving AC-coupled optical modules or  
AC-coupled transmission lines.  
Document #: 38-02002 Rev. *B  
Page 19 of 48  
PRELIMINARY  
CYP15G0401DXA  
Table 9. TX Modes 5 and 8, Quad-Channel Bonded  
Characters Generated  
Encoded data character on channel A  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
K28.5 fill character on channel A  
1
Special character code on channel A  
16-character word sync on channel A  
Encoded data character on channel B  
K28.5 fill character on channel B  
1
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
Special character code on channel B  
16-character word sync on channel B  
Encoded data character on channel C  
K28.5 fill character on channel C  
1
X
X
X
X
X
X
X
X
X
0
1
Special character code on channel C  
16-character word sync on channel C  
Encoded data character on channel D  
K28.5 fill character on channel D  
1
X
X
X
X
X
0
1
Special character code on channel D  
16-character word sync on channel D  
1
X
16-character word sync on channels A, B, C, and D  
When configured for local loopback (LPEN = HIGH), the output  
drivers for all enabled ports are configured to drive a static  
differential logic-1.  
the associated internal logic for that channel is also configured  
for lowest power operation. When OELE returns LOW, the val-  
ues present on the BOE[7:0] inputs are latched in the Output  
Enable Latch, and remain there until OELE returns HIGH to  
opened the latch again.  
Each output can be enabled or disabled separately through the  
BOE[7:0] inputs, as controlled by the OELE latch-enable sig-  
nal. When OELE is HIGH, the signals present on the BOE[7:0]  
inputs are passed through the Serial Output Enable latch to  
control the serial output drivers. The BOE[7:0] input associat-  
ed with a specific OUTxy± driver is listed in Table 10.  
Note: When a disabled transmit channel (i.e., both outputs  
disabled) is re-enabled, the data on the serial outputs may  
not meet all timing specifications for up to 10 ms.  
Transmit PLL Clock Multiplier  
Table 10. Output Enable, BIST, and Receive Channel  
Enable Signal Map  
The Transmit PLL Clock Multiplier accepts a character-rate or  
half-character-rate external clock at the REFCLK input, and  
multiples that clock by 10 or 20 (as selected by TXRATE) to  
generate a bit-rate clock for use by the transmit shifter. It also  
provides a character-rate clock used by the transmit paths.  
BIST  
ReceivePLL  
Channel  
Enable  
Output  
Controlled  
(OELE)  
Channel  
Enable  
BOE  
Input  
(BISTLE)  
(RXLE)  
The clock multiplier PLL can accept a REFCLK input between  
10 MHz and 150 MHz, however, this clock range is limited by  
the operating mode of the CYP15G0401DXA clock multiplier  
(controlled by TXRATE) and by the level on the SPDSEL input.  
SPDSEL is a 3-level select[2] (ternary) input that selects one  
of three operating ranges for the serial data outputs and in-  
puts. The operating serial signaling-rate and allowable range  
of REFCLK frequencies are listed in Table 11.  
BOE[7]  
BOE[6]  
BOE[5]  
BOE[4]  
BOE[3]  
BOE[2]  
BOE[1]  
BOE[0]  
OUTD2±  
OUTD1±  
OUTC2±  
OUTC1±  
OUTB2±  
OUTB1±  
OUTA2±  
OUTA1±  
Transmit D  
Receive D  
Transmit C  
Receive C  
Transmit B  
Receive B  
Transmit A  
Receive A  
X
Receive D  
X
Receive C  
X
Receive B  
X
The REFCLK± input is a non-standard input. It is implemented  
as a differential input with each input internally biased to  
VCC/2. If the REFCLK+ input is connected to a TTL, LVTTL, or  
LVCMOS clock source, the input signal is recognized when it  
passes through the internally biased reference point.  
Receive A  
When OELE is HIGH and BOE[x] is HIGH, the associated se-  
rial driver is enabled to drive any attached transmission line.  
When OELE is HIGH and BOE[x] is LOW, the associated driv-  
er is disabled and internally configured for minimum power dis-  
sipation. If both outputs for a channel are in this disabled state,  
When both the REFCLK+ and REFCLKinputs are connect-  
ed, the clock source must be a differential clock. This can be  
Document #: 38-02002 Rev. *B  
Page 20 of 48  
PRELIMINARY  
CYP15G0401DXA  
Table 11. Operating Speed Settings  
REFCLK  
Table 12. Analog Amplitude Detect Valid Signal Levels  
Signaling  
Rate  
SDASEL  
Typical signal with peak amplitudes above  
Frequency  
LOW  
140 mV p-p differential  
SPDSEL  
TXRATE  
(MHz)  
1020  
2040  
2040  
4080  
4075  
80150  
(MBaud)  
MID (Open) 280 mV p-p differential  
HIGH 420 mV p-p differential  
LOW  
1
0
1
0
1
0
200400  
400800  
8001500  
MID (Open)  
HIGH  
Analog Amplitude  
While the majority of these signal monitors are based on fixed  
constants, the analog amplitude level detection is adjustable  
to allow operation with highly attenuated signals, or in high-  
noise environments. This adjustment is made through the  
SDASEL signal, a 3-level select[2] (ternary) input, which sets  
the trip point for the detection of a valid signal at one of three  
levels, as listed in Table 12. This control input effects the ana-  
log monitors for all receive channels.  
either a differential LVPECL clock that is DC-or AC-coupled, or  
a differential LVTTL or LVCMOS clock.  
By connecting the REFCLKinput to an external voltage  
source or resistive voltage divider, it is possible to adjust the  
reference point of the REFCLK+ input for alternate logic levels.  
When doing so it is necessary to ensure that the 0V-differential  
crossing point remain within the parametric range supported  
by the input.  
The Signal Detect monitors are active for the present line re-  
ceiver, as selected by the associated INSELx input. When con-  
figured for local loopback (LPEN = HIGH), no line receivers are  
selected, and the LFI output for each channel reports only the  
receive VCO frequency out-of-range and transition density  
status of the associated transmit signal. When local loopback  
is active, the analog amplitude monitors are disabled.  
CYP15G0401DXA Receive Data Path  
Transition Density  
Serial Line Receivers  
The transition detection logic checks for the absence of any  
transitions spanning greater than six transmission characters  
(60 bits). If no transitions are present in the data received on  
a channel (within the referenced period), the transition detec-  
tion logic for that channel will assert LFIx. The LFIx output  
remains asserted until at least one transition is detected in  
each of three adjacent received characters.  
Two differential line receivers, INx1± and INx2± , are available  
on each channel for accepting serial data streams. The active  
line receiver on a channel is selected using the associated  
INSELx input. The serial line receiver inputs are all differential,  
and can accommodate wire interconnect and filtering losses  
or transmission line attenuation greater than 16 dB  
(VDIF > 100 mV, or 200 mV peak-to-peak differential) or can be  
DC- or AC-coupled to +3.3V powered fiber-optic interface  
modules (any ECL/PECL logic family, not limited to 100K  
PECL) or AC-coupled to +5V powered optical modules. The  
common-mode tolerance of these line receivers accommo-  
dates a wide range of signal termination voltages. Each receiv-  
er provides internal DC-restoration, to the center of the receiv-  
ers common mode range, for AC-coupled signals.  
Range Controls  
The receive-VCO range-control monitors do more than just  
report the frequency status of the received signal. They also  
determine if the receive Clock/Data Recovery circuits (CDR)  
should align the receive VCO clock to the data stream or to the  
local REFCLK input. This function prevents the receive VCO  
from tracking an out-of-specification received signal.  
The local loopback input (LPEN) allows the serial transmit data  
outputs to be routed internally back to the Clock and Data Re-  
covery circuit associated with each channel. When configured  
for local loopback, all transmit serial driver outputs are forced  
to output a differential logic-1. This prevents local diagnostic  
patterns from being broadcast to attached remote receivers.  
When the range-control monitor for a channel indicates that  
the signaling rate is within specification, the phase detector in  
the receive PLL is configured to track the transitions in the  
received data stream. In this mode the LFIx output for the as-  
sociated channel is HIGH (unless one of the other status mon-  
itors indicates that the received signal is out of specification).  
If the range-control monitor indicates that the received data  
stream signaling-rate is out of specification, the phase detector  
is configured to track the local REFCLK input, and the associ-  
ated LFIx output is asserted LOW.  
Signal Detect / Link Fault  
Each selected Line Receiver (i.e., that routed to the Clock and  
Data Recovery PLL) is simultaneously monitored for  
analog amplitude  
transition density  
range controls report the received data stream inside nor-  
mal frequency range (± 200 ppm)  
The specific trip points for this compare function are listed in  
Table 13. Because the compare function operates with two  
asynchronous clocks, there is a small uncertainty in the mea-  
surement. The switch points are asymmetric to provide hyster-  
esis to the operation.  
receive channel enabled  
All of these conditions must be valid for the Signal Detect block  
to indicate a valid signal is present. This status is presented on  
the LFIx (Link Fault Indicator) output associated with each re-  
ceive channel, which changes synchronous to the selected  
receive interface clock.  
Receive Channel Enabled  
The CYP15G0401DXA contains four receive channels that  
can be independently enabled and disabled. Each channel  
can be enabled or disabled separately through the BOE[7:0]  
inputs, as controlled by the RXLE latch-enable signal. When  
RXLE is HIGH, the signals present on the BOE[7:0] inputs are  
Document #: 38-02002 Rev. *B  
Page 21 of 48  
PRELIMINARY  
CYP15G0401DXA  
Table 13. Receive Signaling Rate Range Control criteria  
monitors, the CDR PLL will track REFCLK instead of the data  
stream. When the frequency of the selected data stream re-  
turns to a valid frequency, the CDR PLL is allowed to track the  
received data stream. The frequency of REFCLK is required  
to be within ± 200 ppm of the frequency of the clock that drives  
the REFCLK input of the remote transmitter to ensure a lock  
to the incoming data stream.  
Frequency  
Difference  
Between  
Next RX PLL  
Tracking  
Source  
Current RX PLL TransmitCharacter  
Tracking Source  
Clock & RX VCO  
Selected data  
stream  
(LFIx = HIGH)  
<1708 ppm  
Data Stream  
Indeterminate  
REFCLK  
For systems using multiple or redundant connections, the LFIx  
output can be used to select an alternate data stream. When  
an LFIx indication is detected, external logic can toggle selec-  
tion of the associated INx1± and INx2± inputs through the as-  
sociated INSELx input. When a port switch takes place, it is  
necessary for the receive PLL for that channel to reacquire the  
new serial stream and frame to the incoming character bound-  
aries. If channel bonding is also enabled, a channel alignment  
event is also required before the output data may be consid-  
ered usable.  
17081953 ppm  
>1953 ppm  
REFCLK  
(LFIx = LOW)  
<488 ppm  
Data Stream  
Indeterminate  
REFCLK  
488732 ppm  
>732 ppm  
passed through the Receive Channel Enable latch to control  
the PLLs and logic of the associated receive channel. The  
BOE[7:0] input associated with a specific receive channel is  
listed in Table 10.  
Deserializer/Framer  
Each CDR circuit extracts bits from the associated serial data  
stream and clocks these bits into the Shifter/Framer at the bit-  
clock rate. When enabled, the Framer examines the data  
stream looking for one or more COMMA or K28.5 characters  
at all possible bit positions. The location of this character in the  
data stream is used to determine the character boundaries of  
all following characters.  
When RXLE is HIGH and BOE[x] is HIGH, the associated re-  
ceive channel enabled to receive and decode a serial stream  
from the selected line receiver. When RXLE is HIGH and  
BOE[x] is LOW, the associated receive channel is disabled and  
internally configured for minimum power dissipation. If a single  
channel of a bonded-pair or bonded-quad is disabled, this will  
impact the ability of the receive channels to bond correctly. In  
addition, if the disabled channel is selected as the master  
channel for insert/delete functions, or for recovered clock se-  
lect, these functions will not work correctly. Any disabled chan-  
nel will indicate a constant /LFIx output. When RXLE returns  
LOW, the values present on the BOE[7:0] inputs are latched in  
the Receive Channel Enable Latch, and remain there until  
RXLE returns HIGH to opened the latch again.  
Framing Character  
The CYP15G0401DXA allows selection of one of three com-  
binations of framing characters to support requirements of dif-  
ferent interfaces. The selection of the framing character is  
made through the FRAMCHAR input.  
FRAMCHAR is a 3-level select [2] input that allows selection of  
one of three different framing characters or character combi-  
nations. The specific bit combinations of these framing char-  
acters are listed in Table 14. When the specific bit combination  
of the selected framing character is detected by the framer, the  
boundaries of the characters present in the received data  
stream are known.  
Note: When a disabled receive channel is re-enabled, the  
status of the associated LFIx output and data on the parallel  
outputs for the associated channel may be indeterminate  
for up to 10 ms.  
Clock/Data Recovery  
The extraction of a bit-rate clock and recovery of bits from each  
received serial stream is performed by a separate Clock/Data  
Recovery (CDR) block within each receive channel. The clock  
extraction function is performed by high-performance embed-  
ded phase-locked loops (PLLs) that track the frequency of the  
transitions in the incoming bit streams and align the phase of  
their internal bit-rate clocks to the transitions in the selected  
serial data streams.  
Table 14. Framing Character Selector  
Bits detected in framer  
FRAMCHAR  
LOW  
Character Name  
Bits Detected  
00111110XX[7]  
COMMA+  
MID (Open)  
COMMA+  
COMMA−  
00111110XX[7]  
or 11000001XX  
Each CDR accepts a character-rate (bit-rate ÷ 10) or half-  
character-rate (bit-rate ÷ 20) reference clock from the  
REFCLK input. This REFCLK input is used to  
HIGH  
K28.5  
+K28.5  
0011111010 or  
1100000101  
Framer  
ensure that the VCO (within each CDR) is operating at the  
correct frequency (rather than some harmonic of the bit-  
rate)  
The framer on each channel operates in one of three different  
modes, as selected by the RFMODE input. In addition, the  
framer itself may be enabled or disabled through the RFEN  
input. When RFEN = LOW, the framers in all four receive paths  
are disabled, and no combination of bits in a received data  
stream will alter the character boundaries. When RFEN =  
HIGH, the framer selected by RFMODE is enabled on all four  
channels.  
to improve PLL acquisition time  
andto limitunlocked frequency excursions oftheCDR VCO  
when no data is present at the selected serial inputs.  
Regardless of the type of signal present, the CDR will attempt  
to recover a data stream from it. If the frequency of the recov-  
ered data stream is outside the limits set by the range control  
Note:  
7. The standard definition of a COMMA contains only seven bits. However, since all valid COMMA characters within the 8B/10B character set also have the 8th  
bit as an inversion of the 7th bit, the compare pattern is extended to a full eight bits to reduce the possibility of a framing error.  
Document #: 38-02002 Rev. *B  
Page 22 of 48  
PRELIMINARY  
CYP15G0401DXA  
When RFMODE = LOW, the low-latency framer is selected.  
This framer operates by stretching the recovered character  
clock until it aligns with the received character boundaries. In  
this mode the framer starts its alignment process on the first  
detection of the selected framing character. To reduce the im-  
pact on external circuits that make use of a recovered clock,  
the clock period is not stretched by more than two bit-periods  
in any one clock cycle. When operated in with a character-rate  
output clock (RXRATE = LOW), the output of properly framed  
characters may be delayed by up to nine character-clock  
cycles from the detection of the selected framing character.  
When operated with a half-character-rate output clock  
(RXRATE = HIGH), the output of properly framed characters  
may be delayed by up to 14 character-clock cycles from the  
detection of the selected framing character.  
and generation of ODD parity on the decoded characters.  
10B/8B Decoder  
The framed parallel output of each deserializer shifter is  
passed to the 10B/8B Decoder where, if the Decoder is en-  
abled (DECMODE LOW), it is transformed from a 10-bit  
transmission character back to the original Data and Special  
Character codes. This block uses the 10B/8B decoder pat-  
terns in Table 24 and Table 25 of this data sheet. Valid data  
characters are indicated by a 000b bit-combination on the as-  
sociated RXSTx[2:0] status bits, and Special Character codes  
are indicated by a 001b bit-combination on these same status  
outputs. Framing characters, Invalid patterns, disparity errors, and  
synchronization status are presented as alternate combinations of  
these status bits.  
When RFMODE is MID (open) the Cypress-mode multi-byte  
framer is selected. The required detection of multiple framing  
characters makes the associated link much more robust to in-  
correct framing due to aliased SYNC characters in the data  
stream. In this mode, the framer does not adjust the character  
clock boundary, but instead aligns the character to the already  
recovered character clock. This ensures that the recovered  
clock will not contain any significant phase changes or hops  
during normal operation or framing, and allows the recovered  
clock to be replicated and distributed to other external circuits  
or components using PLL-based clock distribution elements.  
In this framing mode the character boundaries are only adjust-  
ed if the selected framing character is detected at least twice  
within a span of 50 bits, with both instances on identical 10-bit  
character boundaries.  
The 10B/8B decoder operates in two normal modes, and can  
also be bypassed. The operating mode for the decoder is con-  
trolled by the DECMODE input.  
When DECMODE = LOW, the decoder is bypassed and raw  
10-bit characters are passed to the output register. In this  
mode, channel bonding is not possible, the receive Elasticity  
Buffers are bypassed, and RXCKSEL must be MID. This clock  
mode generates separate RXCLKx± outputs for each receive  
channel.  
When DECMODE is MID (or open), the 10-bit transmission  
characters are decoded using Tables 24 and 25. Received  
Special Code characters are decoded using the Cypress col-  
umn of Table 25.  
When DECMODE = HIGH, the 10-bit transmission characters  
are decoded using Table 24 and Table 25. Received Special  
Code characters are decoded using the Alternate column of  
Table 25.  
When RFMODE = HIGH, the alternate-mode multi-byte framer  
is enabled. Like the Cypress-mode multi-byte framer, multiple  
framing characters must be detected before the character  
boundary is adjusted. In this mode, the data stream must con-  
tain a minimum of four of the selected framing characters, re-  
ceived as consecutive characters, on identical 10-bit bound-  
aries, before character framing is adjusted.  
In all settings where the decoder is enabled, the receive paths  
may be operated as separate channels or bonded to form var-  
ious multi-channel buses.  
Receive BIST Operation  
NOTE: Except for the K29.7 character, the 8B/10B running  
disparity rules prohibit the presence of multiple COMMA+  
characters as consecutive characters. Because of this, the  
combination of FRAMCHAR LOW and RFMODE = HIGH is  
not recommended. While framing can still take place while  
following all 8B/10B coding rules, this configuration pre-  
vents framing to the K28.5 character.  
The receiver interfaces contain internal pattern generators that  
can be used to validate both device and link operation. These  
generators are enabled by the associated BOE[x] signals list-  
ed in Table 10 (when the BISTLE latch enable input is HIGH).  
When enabled, a register in the associated receive channel  
becomes a signature pattern generator and checker by logi-  
cally converting to a Linear Feedback Shift Register (LFSR).  
This LFSR generates a 511-character sequence that includes  
all Data and Special Character codes, including the explicit  
violation symbols. This provides a predictable yet pseudo-ran-  
dom sequence that can be matched to an identical LFSR in  
the attached Transmitter(s). When synchronized with the re-  
ceived data stream, the associated receiver checks each char-  
acter in the Decoder with each character generated by the  
LFSR and indicates compare errors and BIST status at the  
RXSTx[2:0] bits of the output register.  
NOTE: The receive Elasticity Buffers require detection of  
four of the selected framing character to enable buffer align-  
ment and centering. Because these characters must occur  
as consecutive characters, the combination of FRAMCHAR  
LOW and RFMODE = HIGH is not recommended for re-  
ceive modes that use the Elasticity Buffers.  
Framing for all channels is enabled when RFEN = HIGH. If  
RFEN = LOW, the framer for each channel is disabled. When  
the framers are disabled, no changes are made to the recov-  
ered character boundaries on any channel, regardless of the  
presence of framing characters in the data stream.  
When the BISTLE signal is HIGH, any BOE[x] input that is  
LOW enables the BIST generator/checker in the associated  
receive channel (or the BIST generator in the associated trans-  
mit channel). When BISTLE returns LOW, the values of all  
BOE[x] signals are captured in the BIST Enable Latch. These  
values remain in the BIST Enable Latch until BISTLE is re-  
turned high to open the latch again. All captured signals in the  
BIST Enable Latch are set HIGH (i.e., BIST is disabled) follow-  
ing a device reset (TRSTZ is sampled LOW).  
10B/8B Decoder Block  
The decoder logic block performs three primary functions:  
decoding the received transmission characters back into  
Data and Special Character codes,  
comparing generated BIST patterns with received charac-  
ters to permit at-speed link and device testing,  
Document #: 38-02002 Rev. *B  
Page 23 of 48  
PRELIMINARY  
CYP15G0401DXA  
The LFSR is initialized by the BIST hardware once the BIST  
enable for that receive channel is present at the output of the  
BIST Enable Latch, and is recognized. This sets the BIST  
LFSR to the BIST-loop start-code of D0.0 (D0.0 is sent only  
once per BIST loop). The status of the BIST progress and any  
character mismatches is presented on the RXSTx[2:0] status  
outputs.  
character-rate REFCLK↑  
recovered clock from the same receive channel  
recovered clock from an alternate receive channel  
These Elasticity Buffers are also used to align the output data  
streams when multiple channels are bonded together.  
Receive Modes  
Code rule violations or running disparity errors that occur as  
part of the BIST loop do not cause an error indication.  
RXSTx[2:0] indicates 010b or 100b for one character period per  
BIST loop to indicate loop completion. This status can be used to  
check test pattern progress. These same status values are present-  
ed when the decoder is bypassed and BIST is enabled on a receive  
channel.  
The operating mode of the receive path is set through the  
RXMODE[1:0] inputs. These RXMODE[1:0] inputs are only in-  
terpreted when the decoder is enabled (DECMODE LOW).  
These modes determine the type (if any) of channel bonding  
and status reporting. The different receive modes are listed in  
Table 15.  
Table 15. Receive Operating Modes  
RX Mode Operating Mode  
The specific status reported by the BIST state machine are  
listed in Table 21. These same codes are reported on the re-  
ceive status outputs regardless of the state of DECMODE.  
The specific patterns checked by each receiver are described  
in detail in the Cypress application note HOTLink Built-In Self-  
Test.The sequence compared by the CYP15G0401DXA is  
identical to that in the CY7B933 and CY7C924DX, allowing  
interoperable systems to be built when used at compatible se-  
rial signaling rates.  
Channel  
Bonding  
RXSTx Status Reporting  
Status A  
0
1
2
3
4
5
6
7
8
LL  
LM  
LH  
Independent  
Reserved for test  
Status B  
If the number of invalid characters received ever exceeds the  
number of valid characters by 16, the receive BIST state ma-  
chine aborts the compare operations and resets the LFSR to  
the D0.0 state to look for the start of the BIST sequence again.  
Independent  
Dual  
ML  
MM  
MH  
HL  
Status A  
Reserved for test  
Status B  
When the receive paths are configured for common clock op-  
eration (RXCKSEL MID) each pass must be preceded by a  
16-character Word Sync Sequence to allow output buffer  
alignment and management of clock frequency variations.  
This is automatically generated by the transmitter when its lo-  
cal RXCKSEL MID.  
Dual  
Quad  
Status A  
HM  
HH  
Reserved for test  
Status B  
Quad  
The BIST state machine requires the characters to be correctly  
framed for it to detect the BIST sequence. If the framer is en-  
abled and configured for low-latency operation (RFMODE =  
LOW), the framer can align to characters within the BIST se-  
quence. If either of the multi-byte framers are enabled  
(RFMODE LOW), it is generally necessary to frame the re-  
ceiver before BIST is enabled. If the receive outputs are  
clocked relative to REFCLK (RXCKSEL = LOW), the transmit-  
ter precedes every 511 character BIST sequence with a 16-  
character Word Sync Sequence. This sequence will frame the  
receiver regardless of the setting of RFMODE.  
Independent Channel Modes  
In independent channel modes (RX Modes 0 and 2, where  
RXMODE[1] = LOW), all four receive paths may be clocked in  
any clock mode selected by RXCKSEL.  
When RXCKSEL = LOW, all four receive channels are clocked  
by REFCLK. RXCLKB± and RXCLKD± outputs are disabled  
(High-Z), and the RXCLKA± and RXCLKC± outputs present a  
buffered and delayed form of REFCLK. In this mode, the re-  
ceive Elasticity Buffers are enabled. For REFCLKclocking,  
the Elasticity Buffers must be able to insert K28.5 characters  
and delete framing characters as appropriate.  
Receive Elasticity Buffer  
The insertion of a K28.5 or deletion of a framing character can  
occur at any time on any channel, however, the actual timing  
on these insertions and deletions is controlled in part by the  
how the transmitter sends its data. Insertion of a K28.5 char-  
acter can only occur when the receiver has a framing character  
in the Elasticity Buffer. Likewise, to delete a framing character,  
one must also be in the Elasticity Buffer. To prevent a receive  
buffer overflow or underflow on a receive channel, a minimum  
density of framing characters must be present in the received  
data streams.  
Each receive channel contains an Elasticity Buffer that is de-  
signed to support multiple clocking modes. These buffers allow  
data to be read using an Elasticity Buffer read-clock that is  
asynchronous in both frequency and phase from the Elasticity  
Buffer write clock, or to use a read clock that is frequency co-  
herent but with uncontrolled phase relative to the Elasticity  
Buffer write clock.  
Each Elasticity Buffer is a minimum of 10-characters deep, and  
supports a 12-bit wide data path. It is capable of supporting a  
decoded character, three status bits, and a parity bit for each  
character present in the buffer. The write clock for these buffers  
is always the recovered clock for the associated read channel.  
Prior to reception of valid data, at least one Word Sync Se-  
quence (or that portion of one necessary to align the receive  
buffers) must be received to allow the receive Elasticity Buffer  
to be centered. The Elasticity buffer may also be set by a de-  
vice reset operation initiated through the TRSTZ input, howev-  
er, following such an event the CYP15G0401DX will normally  
The read clock for the Elasticity Buffers may come from one of  
three selectable sources. It may be a  
Document #: 38-02002 Rev. *B  
Page 24 of 48  
PRELIMINARY  
CYP15G0401DXA  
require a framing event before it will correctly decode charac-  
ters.  
Buffers must be able to insert K28.5 characters and delete  
framing characters as appropriate. While these insertions and  
deletions can take place at any time, they must occur at the  
same time on both channels that are bonded together. This is  
necessary to keep the data in the bonded channel-pairs prop-  
erly aligned. This insert and delete process is controlled by the  
channel selected using the RXCLKB+ and RXCLKD+ inputs  
using the decodes listed in Table 17.  
When RXCKSEL is MID (or open), each received channel out-  
put register is clocked by the recovered clock for that channel.  
Since no characters may be added or deleted, the receiver  
Elasticity Buffer is bypassed.  
When RXCKSEL = HIGH, all channels are clocked by the se-  
lected recovered clock. This selection is made using the  
RXCLKB+ and RXCLKD+ signals as inputs per Table 16. This  
selected clock is always output on RXCLKA± and RXCLKC± .  
In this mode the receive Elasticity Buffers are enabled. When  
data is output using a recovered clock (RXCKSEL = HIGH),  
receive channels are not allowed to insert and delete charac-  
ters, except as necessary for Elasticity Buffer alignment.  
When RXCKSEL = HIGH, the A and B channels are clocked  
by the selected recovered clock, and the C and D channels are  
clocked by the selected recovered clock, as shown in  
Table 17. The output clock for the channel A/B bonded-pair is  
output continuously on RXCLKA± . The clock source for this  
output is selected from the recovered clock for channel A or  
channel B using the RXCLKB+ input. The output clock for the  
channel C/D bonded-pair is output continuously on RXCLKC± .  
The clock source for this output is selected from recovered  
clock for channel C or channel D using the RXCLKD+ input.  
Table 16. Independent and Quad Channel Bonded  
Recovered Clock Select  
RXCLKA± /RXCLKC±  
RXCLKB+  
RXCLKD+  
Clock Source  
RXCLKA  
Table 17. Dual-Channel Bonded Recovered Clock Select  
Clock Source  
0
0
1
1
0
1
0
1
RXCLKB  
RXCLKB+  
RXCLKD+  
RXCLKA±  
RXCLKA  
RXCLKB  
RXCLKC±  
RXCLKC  
0
1
X
X
0
1
RXCLKD  
X
X
RXCLKC  
RXCLKD  
Prior to reception of valid data, at least one Word Sync Se-  
quence (or that portion of one necessary to align the receive  
buffers) must be received to allow the receive Elasticity Buffers  
to be centered. The Elasticity buffer may also be set by a de-  
vice reset operation initiated through the TRSTZ input, howev-  
er, following such an event the CYP15G0401DXA will normally  
require a framing event before it will correctly decode charac-  
ters. Since the Elasticity buffer is not allowed to insert or delete  
framing characters, the transmit clocks on the channels must  
all be from a common source.  
When data is output using a recovered clock (RXCKSEL =  
HIGH), receive channels are not allowed to insert and delete  
characters, except as necessary for Elasticity Buffer align-  
ment.  
Quad Channel Modes  
In quad-channel modes (RX modes 6 and 7, where  
RXMODE[1] = HIGH), all four receive channel output registers  
must be clocked by a common clock. This mode does not op-  
erate when RXCKSEL = MID.  
Dual-Channel Bonded Modes  
In dual-channel bonded modes (RX Modes 3 and 5, where  
RXMODE[1] = MID or open), the associated receive channel  
pair output registers must be clocked by a common clock. This  
mode does not operate when RXCKSEL = MID.  
Proper operation in this mode requires that the four transmit  
data streams are clocked from a common reference with no  
long-term character slippage between the bonded channels.  
In quad-channel modes this means that the transmit channels  
A, B, C, and D must all be clocked from a common reference.  
Proper operation in this mode requires that the associated  
transmit data streams are clocked from a common reference  
with no long-term character slippage between the bonded  
channels. In dual-channel mode this means that channels A  
and B must be clocked from a common reference, and chan-  
nels C and D must be clocked from a common reference  
(all four transmit channels may be clocked from the same  
source, but that is not a requirement).  
Prior to reception of valid data, at least one Word Sync Se-  
quence (or that portion of one necessary to align the receive  
buffers) must be received on all four bonded channels (within  
the allowable inter-channel skew window) to allow the receive  
Elasticity Buffers to be centered and aligned.  
When RXCKSEL = LOW, all four receive channels are clocked  
by the internal derivative of REFCLK. RXCLKB± and  
Prior to reception of valid characters, at least one Word Sync  
Sequence (or that portion of one necessary to align the receive  
buffers) must be received on the bonded channels (within the  
allowable inter-channel skew window) to allow the receive  
Elasticity Buffers to be centered. While normal characters may  
be output prior to this alignment event, they are not necessarily  
aligned within the same boundaries that they were transmitted.  
RXCLKD± outputs are disabled (High-Z), and RXCLKA± and  
RXCLKC± present a buffered and delayed form of REFCLK.  
In this mode the receive Elasticity Buffers are enabled. For  
REFCLK clocking, the Elasticity Buffers must be able to insert  
K28.5 characters and delete framing characters as appropri-  
ate. While these insertions and deletions can take place at any  
time, they must occur at the same time on all four channels.  
This is necessary to keep the data in the four bonded channels  
properly aligned. This insert and delete process is controlled  
by the channel selected using the RXCLKB+ and RXCLKD+  
inputs using the decode listed in Table 16.  
When RXCKSEL = LOW, all four receive channels are clocked  
by REFCLK. RXCLKB± and RXCLKD± outputs are disabled  
(High-Z), and RXCLKA± and RXCLKC± present a buffered  
and delayed form of REFCLK. In this mode, the receive Elas-  
ticity Buffers are enabled. For REFCLK clocking, the Elasticity  
Document #: 38-02002 Rev. *B  
Page 25 of 48  
PRELIMINARY  
CYP15G0401DXA  
When RXCKSEL = HIGH, all four receive-channel output reg-  
isters are clocked by the selected recovered clock. The clock  
select for quad channel mode is the same as that for indepen-  
dent channel operation. This selection is made using the  
RXCLKB+ and RXCLKD+ inputs, as shown in Table 16. The  
output clock for the four bonded channels is output continu-  
ously on RXCLKA± and RXCLKC± .  
Table 18. Output Register Bit Assignments[8]  
DECMODE = MID  
or HIGH  
Signal Name  
RXSTx[2] (LSB)  
RXSTx[1]  
RXSTx[0]  
RXDx[0]  
DECMODE = LOW  
COMDETx  
DOUTx[0]  
DOUTx[1]  
DOUTx[2]  
DOUTx[3]  
DOUTx[4]  
DOUTx[5]  
DOUTx[6]  
DOUTx[7]  
DOUTx[8]  
DOUTx[9]  
RXSTx[2]  
RXSTx[1]  
RXSTx[0]  
RXDx[0]  
RXDx[1]  
RXDx[2]  
RXDx[3]  
RXDx[4]  
RXDx[5]  
RXDx[6]  
RXDx[7]  
When data is output using a recovered clock (RXCKSEL =  
HIGH), receive channels are not allowed to insert and delete  
characters, except as necessary for Elasticity Buffer align-  
ment.  
RXDx[1]  
RXDx[2]  
Multi-Device Bonding  
RXDx[3]  
When configured for quad-channel bonding (RXMODE[1] =  
HIGH) it is also possible to bond channels across multiple de-  
vices. This form of channel bonding is only possible when  
RXCKSEL = LOW, selecting REFCLK as the output clock for  
all channels on all devices.  
RXDx[4]  
RXDx[5]  
RXDx[6]  
RXDx[7] (MSB)  
In this mode, the BONDST[1:0] signals are used to pass chan-  
nel bonding status between the different devices. This is nec-  
essary to keep the data on all bonded devices in common  
alignment. One device must be selected as the controlling de-  
vice by driving the MASTER pin on that device LOW. All other  
devices must have their MASTER pin HIGH to prevent having  
multiple active drivers on the BONDST bus. Within the master  
device, a single receive channel is selected as the controlling  
channel for generation of the different BONDST[1:0] status.  
This selection is made using the RXCLKB+ and RXCLKD+  
inputs, as shown in Table 16. This allows the master channel  
selection to be dynamically changed through external control  
of the MASTER, RXCLKB+, and RXCLKD+ inputs.  
Table 19. Decoder Bypass Mode (DECMODE = LOW)  
Signal Name  
RXSTx[2] (LSB)  
RXSTx[1]  
RXSTx[0]  
RXDx[0]  
Bus Weight  
10B Name  
COMDETx  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
a
b
c
d
e
i
RXDx[1]  
RXDx[2]  
RXDx[3]  
NOTE: Any change in master device or channel should be  
followed by assertion of TRSTZ to properly initialize the de-  
vices.  
RXDx[4]  
f
RXDx[5]  
g
h
j
RXDx[6]  
Output Bus  
RXDx[7] (MSB)  
Each receive channel presents a 12-signal output bus consist-  
ing of  
RXCKSEL LOW), the framer will stretch the recovered clock  
to the nearest 20-bit boundary such that the rising edge of  
RXCLKx+ occurs when COMDETx is present on the associat-  
ed output bus.  
an 8-bit data bus  
a 3-bit status bus  
a parity bit  
When the standard framer is enabled and half-rate receive  
port clocking are also enabled (RFMODE LOW and RXRATE  
= HIGH), the output clock is not modified when framing is de-  
tected, but a single pipeline stage may be added or subtracted  
from the data stream by the framer logic such that the rising  
edge of RXCLKx+ occurs when COMDET is present on the  
associated output bus.  
The signals present on this output bus are modified by the  
present operating mode of the CYP15G0401DXA as selected  
by DECMODE. This mapping is shown in Table 18.  
When the 10B/8B decoder is bypassed (DECMODE = LOW),  
the framed 10-bit value is presented to the associated output  
register, along with a status output indicating if the character  
in the output register is one of the selected framing characters.  
The bit usage and mapping of the external signals to the raw  
10B coded character is shown in Table 19.  
This adjustment only occurs when the framer is enabled  
(RFEN = HIGH). When the framer is disabled, the clock bound-  
aries are not adjusted, and COMDETx may be active during  
the rising edge of RXCLKx(if an odd number of characters  
were received following the initial framing).  
The COMDETx status outputs operate the same regardless of  
the bit combination selected for character framing by the  
FRAMCHAR input. They are HIGH when the character in the  
output register contains the selected framing character at the  
proper character boundary, and LOW for all other bit combina-  
tions.  
Parity Generation  
In addition to the eleven data and status bits that are presented  
by each channel, an RXOPx parity output is also available on  
each channel. This allows the CYP15G0401DXA to support  
ODD parity generation for each channel. To handle a wide  
When the low-latency framer and half-rate receive port clock-  
ing are also enabled (RFMODE = LOW, RXRATE = HIGH, and  
Note:  
8. The RXOPx outputs are also driven from the associated output register, but their interpretation is under the separate control of PARCTL.  
Document #: 38-02002 Rev. *B  
Page 26 of 48  
PRELIMINARY  
CYP15G0401DXA  
range of system environments, the CYP15G0401DXA sup-  
ports multiple different forms of parity generation (in addition  
to no parity). When the decoders are enabled (DECMODE ≠  
LOW), parity can be generated on  
Receive Status Bits  
When the 10B/8B decoder is enabled (DECMODE LOW),  
each character presented at the output register includes three  
associated status bits. These bits are used to identify  
the RXDx[7:0] character  
the RXDx[7:0] character and RXSTx[2:0] status  
if the contents of the data bus are valid,  
the type of character present,  
the state of receive BIST operations (regardlessof the state  
of DECMODE),  
When the decoders are bypassed (DECMODE = LOW), parity  
can be generated on  
the RXDx[7:0] and RXSTx[1:0] bits  
the RXDx[7:0] and RXSTx[2:0] bits  
character violations,  
and channel bonding status.  
These modes differ in the number bits which are included in  
the parity calculation. For all cases, only ODD parity is provid-  
ed which ensures that at least one bit of the data bus is always  
a logic-1. Those bits covered by parity generation are listed in  
Table 20.  
These conditions normally overlap; i.e., a valid data character  
received with incorrect running disparity is not reported as a  
valid data character. It is instead reported as a decoder viola-  
tion of some specific type. This implies a hierarchy or priority  
level to the various status bit combinations. The hierarchy and  
value of each status is listed in Table 21.  
Parity generation is enabled through the 3-level select  
PARCTL input. When PARCTL = LOW, parity checking is dis-  
abled, and the RXOPx outputs are all disabled (High-Z).  
Table 20. Output Register Parity Generation  
Receive Parity Generate Mode (PARCTL)  
MID  
When PARCTL is MID (open) and the decoders are enabled  
(DECMODE LOW), ODD parity is generated for the received  
and decoded character in the RXDx[7:0] signals and is pre-  
sented on the associated RXOPx output. When PARCTL is  
MID (open) and the decoders are bypassed  
(DECMODE = LOW), ODD parity is generated for the received  
and decoded character in the RXDx[7:0] and RXSTx[1:0] bit  
positions.  
Signal  
Name  
DECMODE  
= LOW  
DECMODE  
LOW[9]  
LOW  
HIGH  
X[10]  
X
RXSTx[2]  
RXSTx[1]  
RXSTx[0]  
RXDx[0]  
RXDx[1]  
RXDx[2]  
RXDx[3]  
RXDx[4]  
RXDx[5]  
RXDx[6]  
RXDx[7]  
X
X
X
X
X
X
X
X
X
X
X
When PARCTL = HIGH with the decoder enabled (or by-  
passed), ODD parity is generated for both the received and  
decoded character, and for the associated RXSTx[2:0] status  
bits.  
X
X
X
X
X
X
X
X
X
X
X
When interface clocking is such that the decoded character is  
passed through the receive Elasticity Buffer prior to the addi-  
tion of the RXSTx[2:0] status bits, the generation of output  
parity becomes a two-step process. The first parity calculation  
takes place as soon as the character is framed and decoded.  
This generates proper parity for the data portion of the decod-  
ed character which is then written to the Elasticity Buffer. When  
the parity calculation also includes the associated RXSTx[2:0]  
status bits (PARCTL = HIGH), a second parity calculation is  
made prior to loading the data and status bits into the receive  
Output Register. This is necessary because the status bits as-  
sociated with a character in the Output Register are not nec-  
essarily determined until after the character is read from the  
receive Elasticity Buffer.  
X
X
X
X
X
Within these status decodes, there are three forms of status  
reporting. The two normal or data status reporting modes  
(Type A and Type B) are selectable through the RXMODE[0]  
input. These status types allow compatibility with legacy sys-  
tems, while allowing full reporting in new systems. The third  
status type is used for reporting receive BIST status and  
progress. These status values are generated in part by the  
Receive Synchronization State Machine, and are listed in  
Table 21.  
This second parity calculation is based only on the content of  
the status bits, and the singular parity bit associated with the  
character read from the Elasticity Buffer.  
Notes:  
9. Receive path parity output drivers (RXOPx) are disabled (High-Z) when PARCTL = LOW  
10. When the decoder is bypassed (DECMODE = LOW) and BIST is not enabled (Receive BIST Latch output is HIGH), RXSTx[2] is driven to a logic-0, except  
when the character in the output buffer is a framing character.  
Document #: 38-02002 Rev. *B  
Page 27 of 48  
PRELIMINARY  
CYP15G0401DXA  
Table 21. Receive Character Status Bits  
Description  
Receive BIST Status  
(Receive BIST = Enabled)  
RXSTx[2:0] Priority Type-A Status  
Type-B Status  
000  
7
Normal Character Received. The valid Data character on the output BIST Data Compare. Charac-  
bus meets all the formatting requirements of Data characters listed in ter compared correctly  
Table 24.  
001  
7
Special Code Detected. The valid special character on the output bus BIST Command Compare.  
meets all the formatting requirements of Special Code characters listed Character compared correctly  
in Table 25, but is not the presently selected framing character or a de-  
coder violation indication.  
010  
011  
2
5
Receive Elasticity Buffer Under- Channel Lock Detected. Asserts BIST Last Good. Last Charac-  
run/Overrun Error. The receive when the bonded channels have ter of BIST sequence detected  
buffer was not able to add/drop a detected RESYNC within the allot- and valid.  
K28.5 or framing character.  
ted window. Presented only on the  
last cycle before aligned data is pre-  
sented.  
Framing Character detected. This indicates that a character matching  
the patterns identified as a framing character (as selected by  
FRAMCHAR) was detected. The decoded value of this character is  
present in the associated output bus.  
100  
101  
4
1
Codeword Violation. The character on the output bus is a C0.7. This BIST Last Bad. Last Character  
indicates that the received character cannot be decoded into any valid of BIST sequence detected in-  
character.  
valid.  
Loss of Sync. The character on Loss of Sync. The character on BIST Start. Receive BIST is en-  
the bus is invalid, due to an event the bus is invalid, due to an event abled on this channel, but char-  
that has caused the receive chan- that has caused the receive chan- acter compares have not yet  
nels to lose synchronization. When nels to lose synchronization. When commenced. This also indi-  
channel bonding is enabled, this in- channel bonding is enabled, this in- cates a PLL Out of Lock condi-  
dicates that one or more channels dicates that one or more channels tion, and Elasticity Buffer over-  
have either lost bit synchronization have either lost bit synchronization flow/underflow conditions.  
(loss of character framing), or that (loss of character framing), or that  
the bonded channels are no longer the bonded channels are no longer  
in proper character alignment. in proper character alignment.  
When the channels are operated in- When the channels are operated in-  
dependently (with the decoder en- dependently (with the decoder en-  
abled), this indicates a PLL Out of abled), this indicates a loss of char-  
Lock condition.  
acter framing. Also used to indicate  
receive Elasticity Buffer under-  
flow/overflow errors.  
110  
111  
6
3
Running Disparity Error. The character on the output bus is a C4.7, BIST Error. While comparing  
C1.7, or C2.7.  
characters, a mismatch was  
found in one or more of the de-  
coded character bits.  
Resync. The receiver state machine is in the Resynchronization state. BIST Wait. The receiver is com-  
In this state the data on the output bus reflects the presently decoded paring characters. but has not  
FRAMCHAR.  
yet found the start of BIST char-  
acter to enable the LFSR.  
Receive Synchronization State Machine  
When operated without channel bonding (RXMODE[1] = LOW,  
RX Modes 0 and 2), these state machines are disabled and  
characters are decoded directly. In RX Mode 0 the  
RESYNC (111b) status is never reported. In RX Mode 2, nei-  
ther the RESYNC (111b) or Channel Lock Detected (010b)  
status are reported.  
Each receive channel contains a Receive Synchronization  
state machine. This machine handles loss and recovery of bit,  
channel, and word framing, and part of the control for channel  
bonding. This state machine is enabled whenever the receive  
channels are configured for channel bonding (RXMODE[1] ≠  
LOW). Separate forms of the state machine exist for the two  
different types of status reporting.  
Document #: 38-02002 Rev. *B  
Page 28 of 48  
PRELIMINARY  
CYP15G0401DXA  
Reset  
NO_SYNC  
IN_SYNC  
5
RXSTx=101  
4
6
3
4
COULD_NOT_BOND  
RESYNC  
1
RXSTx=101  
RXSTx=111  
2
#
1
2
3
4
5
State Transition Conditions  
(BOND_INH = LOW) AND (Deskew Window Expired)  
FRAMCHAR Detected  
(Elasticity Buffer Under/Overrun) OR (RX PLL Loss of Lock) OR (Any Decoder Error)  
Four Consecutive FRAMCHAR Detected  
(Elasticity Buffer Under/Overrun) OR (RX PLL Loss of Lock) OR (Four Consecutive Decoder Errors) OR  
(Invalid Minus Valid = 4)  
6
Valid Character other than a FRAMCHAR  
Figure 2. Status Type-A Receive State Machine  
Status Type-A Receive State Machine  
The IN_SYNC state can respond with multiple status types,  
while others can respond with only one type.  
This machine has four primary states: NO_SYNC, RESYNC,  
COULD_NOT_BOND, and IN_SYNC, as shown in Figure 2.  
Document #: 38-02002 Rev. *B  
Page 29 of 48  
PRELIMINARY  
CYP15G0401DXA  
Reset  
RXSTx = 101  
IN_SYNC  
5
NO_SYNC  
RXSTx = 010  
6
7
8
6
1
4
3
4
RXSTx = 101  
RXSTx = 010  
RXSTx = 111  
RESYNC_IN_SYNC  
RESYNC  
RXSTx=011  
RXSTx=111  
2
2
#
Condition  
1
2
3
(BOND_INH = LOW OR Master Channel Did Not Bond) AND Deskew Window Expired  
FRAMCHAR Detected  
(Elasticity Buffer Under/Overrun) OR (RX PLL Loss of Lock) OR (Any Decoder Error) OR ((BOND_INH = LOW  
OR Master Channel Did Not Bond) AND (Deskew Window Expired))  
4
5
Four Consecutive FRAMCHAR Detected  
(Elasticity Buffer Under/Overrun) OR (RX PLL Loss of Lock) OR (Four Consecutive Decoder Errors) OR (Invalid  
Minus Valid = 4)  
6
7
8
Last FRAMCHAR Before a Valid Character AND Bonded to Master Channel  
(Elasticity Buffer Under/Overrun) OR (RX PLL Loss of Lock)  
Decoder Error  
Figure 3. Status Type-B Receive State Machine  
Status Type-B Receive State Machine  
terface for the first character of the next BIST sequence (D0.0).  
Also, if the Elasticity Buffer ever hits and overflow/underflow  
condition, the status is forced to the BIST_START until the  
buffer is recentered (approximately nine character periods).  
This machine has four primary states: NO_SYNC, RESYNC,  
IN_SYNC, and COULD_NOT_BOND, as shown in Figure 3.  
Some of these state can respond with only one status value,  
while others can respond with multiple status types.  
To ensure compatibility between the source and destination  
BIST operating modes, the sending and receiving ends of the  
BIST sequence must both have RXCKSEL = MID or both have  
RXCKSEL MID.  
BIST Status State Machine  
When a receive path is enabled to look for and compare the  
received data stream with the BIST pattern, the RXSTx[2:0]  
bits identify the present state of the BIST compare operation.  
JTAG Support  
The CYP15G0401DXA contains a JTAG port to allow system  
level diagnosis of device interconnect. Of the available JTAG  
modes, only boundary scan is supported. This capability is  
present only on the LVTTL inputs and outputs and the  
REFCLK± clock input. The high-speed serial inputs and out-  
puts are not part of the JTAG test chain.  
The BIST state machine has multiple states, as shown in  
Figure 4 and Table 21. When the receive PLL detects an out-  
of-lock condition, the BIST state is forced to the Start-of-BIST  
state, regardless of the present state of the BIST state ma-  
chine. If the number of detected errors ever exceeds the num-  
ber of valid matches by greater than 16, the state machine is  
forced to the WAIT_FOR_BIST state where it monitors the in-  
Document #: 38-02002 Rev. *B  
Page 30 of 48  
PRELIMINARY  
CYP15G0401DXA  
JTAG ID  
The JTAG device ID for the CYP15G0401DXA is 0C800069x.  
3-Level Select Inputs  
Each 3-Level select inputs reports as two bits in the scan reg-  
ister. These bits report the LOW, MID, and HIGH state of the  
associated input as 00, 10, and 11 respectively.  
Monitor Data  
Received  
Receive BIST  
Detected LOW  
RXSTx =  
BIST_START (101)  
RX PLL  
Out of Lock  
RXSTx =  
BIST_START (101)  
RXSTx =  
BIST_WAIT (111)  
Elasticity  
Buffer Error  
Yes  
Start of  
BIST Detected  
No  
No  
Yes, RXSTx =  
BIST_DATA_COMPARE (000)/ BIST_COMMAND_COMPARE(001)  
Compare  
Next Character  
RXSTx =  
Mismatch  
BIST_COMMAND_COMPARE (001)  
Match  
Command  
Data or  
Command  
Auto-Abort  
Condition  
Yes  
RXSTx =  
BIST_DATA_COMPARE (000)  
No  
Data  
End-of-BIST  
State  
End-of-BIST  
State  
No  
Yes, RXSTx =  
BIST_LAST_BAD (100)  
Yes, RXSTx =  
BIST_LAST_GOOD (010)  
No, RXSTx =  
BIST_ERROR (110)  
Figure 4. Receive BIST State Machine  
Document #: 38-02002 Rev. *B  
Page 31 of 48  
PRELIMINARY  
CYP15G0401DXA  
CYP15G0401DXA DC Electrical Characteristics Over the Operating Range  
Parameter  
Description  
Test Conditions  
Min.  
Max.  
Unit  
LVTTL Compatible Outputs  
VOHT  
VOLT  
IOST  
IOZL  
Output HIGH Voltage  
IOH = 4 mA, VCC = Min.  
IOL = 4 mA, VCC = Min.  
VOUT = 0V[11]  
2.4  
0
VCC  
0.4  
V
V
Output LOW Voltage  
Output Short Circuit Current  
High-Z Output Leakage Current  
30  
20  
100  
20  
mA  
µA  
LVTTL Compatible Inputs  
VIHT  
VILT  
IIHT  
Input HIGH Voltage  
2.0  
VCC+0.3  
0.8  
V
Input LOW Voltage  
Input HIGH Current  
0.5  
V
REFCLK Input, VIN = VCC  
Other Inputs, VIN = VCC  
REFCLK Input, VIN = 0.0V  
Other Inputs, VIN = 0.0V  
+40  
µA  
µA  
µA  
µA  
µA  
µA  
+40  
IILT  
Input LOW Current  
500  
40  
IIHPDT  
IILPUT  
Input HIGH Current with internal pull-down VIN = VCC  
+200  
Input LOW Current with internal pull-up  
VIN = 0.0V  
200  
LVDIFF Inputs: REFCLK±  
[12]  
VDIFF  
VIHHP  
VILLP  
VCOM  
Input Differential Voltage  
400  
1.0  
VCC  
mV  
V
Highest Input HIGH Voltage  
Lowest Input LOW voltage  
Common Mode Range  
VCC  
GND  
1.0  
VCC0.4V  
VCC1.2V  
V
[13]  
V
3-Level Inputs  
VIHH  
VIMM  
VILL  
IIHH  
Three-Level Input HIGH Voltage  
Min. VCC Max.  
Min. VCC Max.  
Min. VCC Max.  
VIN = VCC  
0.87 * VCC  
VCC  
V
V
Three-Level Input MID Voltage  
Three-Level Input LOW Voltage  
Input HIGH Current  
0.47 * VCC 0.53 * VCC  
0.0  
0.13 * VCC  
200  
V
µA  
µA  
µA  
IIMM  
IILL  
Input MID current  
VIN = VCC/2  
50  
50  
Input LOW current  
VIN = GND  
200  
Differential CML Serial Outputs: OUTA1± , OUTA2± , OUTB1± , OUTB2± ± OUTC1± , OUTC2± , OUTD1± , OUTD2±  
VOHC  
VOLC  
VODIF  
Output HIGH Voltage  
(VCC referenced)  
100differential load  
150differential load  
100differential load  
150differential load  
100differential load  
150differential load  
VCC0.5  
VCC0.5  
VCC1.1  
VCC1.1  
560  
VCC0.2  
VCC0.2  
VCC0.7  
VCC0.7  
800  
V
V
Output LOW Voltage  
(VCC referenced)  
V
V
Output Differential Voltage  
|(OUT+) (OUT)|  
mV  
mV  
840  
1200  
Differential Serial Line Receiver Inputs: INA1± , INA2± , INB1± , INB2± , INC1± , INC2± , IND1± , IND2±  
VDIFF  
Input Differential Voltage  
|(IN+) (IN)|  
100  
1200  
mV  
VIHE  
VILE  
IIHE  
IILE  
Highest Input HIGH Voltage  
Lowest Input LOW Voltage  
Input HIGH Current  
VCC1.2  
VCC2.0  
VCC  
VCC1.45  
750  
V
V
VIN = VIHE Max.  
VIN = VILE Min.  
µA  
µA  
Input LOW Current  
200  
Typ.  
850  
Miscellaneous  
Max.  
1000  
TBD  
[14]  
ICC  
Power Supply Current  
Freq. = Max. Commercial  
Industrial  
mA  
mA  
TBD  
Document #: 38-02002 Rev. *B  
Page 32 of 48  
PRELIMINARY  
CYP15G0401DXA  
CYP15G0401DXA DC Electrical Characteristics Over the Operating Range (continued)  
Parameter  
Description  
Test Conditions  
Min.  
Max.  
Unit  
Note:  
11. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle.  
12. This is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 or logic-0  
13. The common mode range defines the allowable range of REFCLK+ and REFCLK(relative to the associated power rail) when  
|(REFCLK+) (REFCLK)| = 0V. This marks the zero-crossing between the true and complement inputs as the signal switches between HIGH and LOW.  
14. Maximum ICC is measured with VCC = MAX, RFEN = LOW, with all serial channels sending a constant alternating 01 pattern, and outputs unloaded. Typical  
ICC is measured under similar conditions except with VCC = 3.3V, TA = 25°C.  
AC Test Loads and Waveforms  
3.3V  
R1  
R2  
OUTPUT  
R1=365Ω  
R2=267Ω  
R =100Ω  
L
(Includes fixture and  
probe capacitance)  
C
L
L
C < 5 pF  
C 7 pF  
L
C
L
R
L
(Includes fixture and  
probe capacitance)  
[15]  
[15]  
(a) LVTTL AC Test Load  
(b) CML AC Test Load  
V
IHE  
3.0V  
Note 16  
V
V
IHE  
3.0V  
2.0V  
0.8V  
2.0V  
0.8V  
80%  
80%  
V =1.4V  
V =1.4V  
th  
th  
20%  
250 ps  
20%  
250 ps  
GND  
ILE  
V
ILE  
< 1 ns  
< 1 ns  
(c) LVTTL Input Test Waveform  
(d) PECL Input Test Waveform  
Notes:  
15. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.  
16. The LVTTL switching threshold is 1.4V. All timing references are made relative to the point where the respective rising or falling signal edge crosses this  
threshold voltage.  
Document #: 38-02002 Rev. *B  
Page 33 of 48  
PRELIMINARY  
CYP15G0401DXA  
CYP15G0401DXA Transmitter LVTTL Switching Characteristics Over the Operating Range  
Parameter  
fTS  
Description  
TXCLKx Clock Cycle Frequency  
Min.  
20  
Max.  
150  
50  
Unit  
MHz  
ns  
tTXCLK  
tTXCLKH  
tTXCLKL  
tTXCLKR  
tTXCLKF  
tTXDS  
TXCLKx Period  
6.66  
2.2  
2.2  
0.7  
0.7  
1.5  
1
TXCLKx HIGH Time  
ns  
TXCLKx LOW Time  
ns  
[17, 18, 19]  
[17, 18, 19]  
TXCLKx Rise Time  
5
5
ns  
TXCLKx Fall Time  
ns  
Transmit Data Set-Up Time to TXCLKx(TXCKSEL LOW)  
Transmit Data Hold Time from TXCLKx(TXCKSEL LOW)  
TXCLKO Clock Cycle Frequency (=1x or 2x REFCLK Frequency)  
TXCLKO Period  
ns  
tTXDH  
ns  
fTOS  
20  
150  
50  
MHz  
ns  
tTXCLKO  
6.66  
47  
tTXCLKOD  
tTXOH  
TXCLKO Duty Cycle  
53  
%
TXCLKO HIGH Time  
1.5  
1.5  
ns  
tTXOL  
TXCLKO LOW Time  
ns  
CYP15G0401DXA Receiver LVTTL Switching Characteristics Over the Operating Range  
Parameter  
fRS  
tRXCLKP  
tRXCLKH  
Description  
RXCLKx Clock Output Frequency  
Min.  
10  
Max.  
150  
100  
51  
Unit  
MHz  
ns  
RXCLKx Period  
6.66  
1.5  
5
RXCLKx HIGH Time (RXRATE = LOW)  
RXCLKx HIGH Time (RXRATE = HIGH)  
RXCLKx LOW Time (RXRATE = LOW)  
RXCLKx HIGH Time (RXRATE = HIGH)  
RXCLKx Duty Cycle  
ns  
25  
ns  
tRXCLKL  
1.5  
5
51  
ns  
25  
ns  
tRXCLKD  
47  
53  
%
[17]  
tRXCLKR  
RXCLKx Rise Time  
0.5  
0.5  
2.0  
1.0  
1.2  
1.2  
ns  
[17]  
tRXCLKF  
RXCLKx Fall Time  
ns  
[20]  
tRXDS  
Status and Data Setup Time From RXCLKx↑  
Status and Data Hold Time From RXCLKx↑  
ns  
[20]  
tRXDH  
ns  
Notes:  
17. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.  
18. The ratio of rise time to falling time must not vary by greater than 2:1.  
19. For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time.  
20. Parallel data output specifications are only valid if all outputs are loaded with similar DC and AC loads.  
Document #: 38-02002 Rev. *B  
Page 34 of 48  
PRELIMINARY  
CYP15G0401DXA  
CYP15G0401DXA REFCLK Switching Characteristics Over the Operating Range  
Parameter  
fREF  
tREFCLK  
tREFH  
Description  
Min.  
10  
Max.  
150  
100  
70  
Unit  
MHz  
ns  
ns  
ns  
ns  
ns  
%
REFCLK Clock Frequency  
REFCLK Period  
6.6  
5.9  
2.9  
5.9  
2.9  
30  
REFCLK HIGH Time (TXRATE = HIGH)  
REFCLK HIGH Time (TXRATE = LOW)  
35  
tREFL  
REFCLK LOW Time (TXRATE = HIGH)  
70  
REFCLK LOW Time (TXRATE = LOW)  
35  
[21]  
tREFD  
REFCLK Duty Cycle  
70  
[17, 18, 19]  
tREFR  
REFCLK Rise Time (20%-80%)  
0.3  
0.3  
1.5  
1
5
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
%
[17, 18, 19]  
tREFF  
REFCLK Fall Time (20%-80%)  
5
tTREFDS  
tTREFDH  
tRREFDA  
tRREFDH  
tREFADS  
tREFADH  
tREFCDS  
tREFCDH  
tREFRX  
Transmit Data or TXRST Setup Time to REFCLK (TXCKSEL = LOW)  
Transmit Data or TXRST Hold Time from REFCLK (TXCKSEL = LOW)  
Receive Data Access Time from REFCLK (RXCKSEL = LOW)  
Receive Data Hold Time from REFCLK (RXCKSEL = LOW)  
Received Data Setup Time to RXCLKA (RXCKSEL = LOW)  
Received Data Hold Time from RXCLKA (RXCKSEL = LOW)  
Received Data Setup Time to RXCLKC (RXCKSEL = LOW)  
Received Data Hold Time from RXCLKC (RXCKSEL = LOW)  
REFCLK Frequency Referenced to Received Clock Period[22]  
9.5  
4.0  
2
1.5  
3
0.5  
0.02  
+0.02  
CYP15G0401DXA Transmit Serial Outputs and TX PLL Characteristics Over the Operating Range  
Parameter  
tB  
tRISE  
Description  
Condition  
Min.  
5000  
50  
Max.  
660  
250  
500  
1000  
250  
500  
1000  
35  
Unit  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
Bit Time  
CML Output Rise Time 2080% (CML Test Load)[17]  
CML Output Fall Time 8020% (CML Test Load)[17]  
SPDSEL = HIGH  
SPDSEL = MID  
SPDSEL = LOW  
SPDSEL = HIGH  
SPDSEL = MID  
SPDSEL = LOW  
100  
200  
50  
tFALL  
100  
200  
tDJ  
tRJ  
Deterministic Jitter (peak-peak)[17, 23]  
Random Jitter (σ)[17, 24]  
8
tTXLOCK  
Transmit PLL lock to REFCLK  
TBD  
TBD  
ns  
Notes:  
21. The duty cycle specification is a simultaneous condition with the tREFH and tREFL parameters. This means that at faster character rates the REFCLK duty  
cycle cannot be as large as 30%-70%,  
22. REFCLK has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time.  
REFCLK must be within ± 200 PPM (± 0.02%) of the transmitter PLL reference (REFCLK) frequency, necessitating a ± 100-PPM crystal.  
23. While sending continuous K28.5s, outputs loaded to a balanced 100load, over the operating range.  
24. While sending continuous K28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to REFCLK input, over the  
operating range.  
Document #: 38-02002 Rev. *B  
Page 35 of 48  
PRELIMINARY  
CYP15G0401DXA  
CYP15G0401DXA Receive Serial Inputs and CDR PLL Characteristics Over the Operating Range  
Parameter  
Description  
Receive PLL lock to input data stream (cold start)  
Receive PLL lock to input data stream  
Receive PLL Unlock Rate  
Min.  
Max.  
10  
Unit  
ms  
UI  
tRXLOCK  
2500  
TBD  
tRXUNLOCK  
tSA  
TBD  
0.75  
ns  
Static Alignment[17, 25]  
ps  
tEFW  
Error Free Window [17, 26, 27]  
UI  
Capacitance[17]  
Parameter  
Description  
TTL Input Capacitance  
PECL input Capacitance  
Test Conditions  
TA = 25°C, f0 = 1 MHz, VCC = 3.3V  
TA = 25°C, f0 = 1 MHz, VCC = 3.3V  
Max.  
Unit  
CINTTL  
7
4
pF  
pF  
CINPECL  
Notes:  
25. Static alignment is a measure of the alignment of the Receiver sampling point to the center of a bit. Static alignment is measured by sliding one bit edge in  
3,000 nominal transitions until a character error occurs.  
26. Receiver UI (Unit Interval) iscalculatedas1/(fREF * 20) (when RXRATE = HIGH) or 1/(fREF * 10) (whenRXRATE= LOW) if no data is being received, or 1/(fREF * 20)  
(when RXRATE = HIGH) or 1/(fREF * 10) (when RXRATE = LOW) of the remote transmitter if data is being received. In an operating link this is equivalent to tB.  
27. Error Free Window is a measure of the time window between bit centers where a transition may occur without causing a bit sampling error. EFW is measured  
over the operating range, input jitter < 50% Dj.  
Document #: 38-02002 Rev. *B  
Page 36 of 48  
PRELIMINARY  
CYP15G0401DXA  
CYP15G0401DXA HOTLink II Transmitter Switching Waveforms  
Transmit Interface  
Write Timing  
tTXCLK  
TXCKSEL LOW  
tTXCLKH  
tTXCLKL  
TXCLKx  
tTXDS  
tTXDH  
TXDx[7:0],  
TXCTx[1:0],  
TXOPx,  
SCSEL  
Transmit Interface  
Write Timing  
TXCKSEL = LOW  
TXRATE = LOW  
tREFCLK  
tREFH  
tREFL  
REFCLK  
tTREFDS  
tTREFDH  
TXDx[7:0],  
TXCTx[1:0],  
TXOPx,  
SCSEL  
Transmit Interface  
Write Timing  
TXCKSEL = LOW  
TXRATE = HIGH  
tREFCLK  
tREFH  
tREFL  
REFCLK  
Note  
tTREFDS  
tTREFDS  
tTREFDH  
TXDx[7:0],  
TXCTx[1:0],  
TXOPx,  
SCSEL  
Transmit Interface  
TXCLKO Timing  
tREFCLK  
tREFH  
tREFL  
TXCKSEL = LOW  
TXRATE = HIGH  
REFCLK  
Note  
tTXCLKO  
tTXOH  
tTXOL  
Note  
TXCLKO  
(internal)  
Notes:  
28. When REFCLK is configured for half-rate operation (TXRATE = HIGH) and data is captured using REFCLK instead of a TXCLKx clock (TXCKSEL = LOW),  
data is captured using both the rising and falling edges of REFCLK.  
29. The TXCLKO output remains at the character rate regardless of the state of TXRATE and does not follow the duty cycle of REFCLK.  
30. The rising edge of TXCLKO output has no direct phase relationship to the REFCLK input.  
Document #: 38-02002 Rev. *B  
Page 37 of 48  
PRELIMINARY  
CYP15G0401DXA  
CYP15G0401DXA HOTLink II Transmitter Switching Waveforms (continued)  
Transmit Interface  
TXCLKO Timing  
tREFCLK  
tREFH  
TXCKSEL = LOW  
TXRATE = LOW  
tREFL  
Note  
REFCLK  
tTXCLKO  
tTXOH  
tTXOL  
Note 30  
TXCLKO  
Switching Waveforms for the CYP15G0401DXA HOTLink II Receiver  
Receive Interface  
tREFCLK  
Read Timing  
RXCKSEL = LOW  
TXRATE = LOW  
tREFH  
tREFL  
REFCLK  
tRREFDA  
tRREFDH  
RXDx[7:0],  
RXSTx[2:0],  
RXOPx  
tREFADH  
tREFCDH  
tREFADS  
tREFCDS  
RXCLKA  
RXCLKC  
Note  
Receive Interface  
Read Timing  
RXCKSEL = LOW  
TXRATE = HIGH  
tREFCLK  
tREFH  
tREFL  
REFCLK  
tRREFDA  
tRREFDH  
tRREFDA  
RXDx[7:0],  
RXSTx[2:0],  
RXOPx  
tREFADH  
tREFCDH  
tREFADS  
tREFCDS  
RXCLKA  
RXCLKC  
Note  
Note  
Notes:  
31. RXCLKA and RXCLKC are delayed in phase from REFCLK, and are different in phase from each other.  
32. When operated with a half-rate REFCLK, the setup and hold specifications for data relative to RXCLKA and RXCLKC are relative to both rising and falling  
edges of the respective clock output  
Document #: 38-02002 Rev. *B  
Page 38 of 48  
PRELIMINARY  
CYP15G0401DXA  
Switching Waveforms for the CYP15G0401DXA HOTLink II Receiver  
Receive Interface  
tRXCLKP  
Read Timing  
RXCKSEL = HIGH or MID  
RXRATE = LOW  
tRXCLKH  
tRXCLKL  
RXCLKx+  
RXCLKx-  
tRXDS  
RXDx[7:0],  
RXSTx[2:0],  
RXOPx  
tRXDH  
Receive Interface  
Read Timing  
RXCKSEL = HIGH or MID  
RXRATE = HIGH  
tRXCLKP  
tRXCLKH  
tRXCLKL  
RXCLKx+  
RXCLKx-  
tRXDS  
RXDx[7:0],  
RXSTx[2:0],  
RXOPx  
tRXDH  
Static Alignment  
Error-Free Window  
t /2t  
B
SA  
t /2t  
B
SA  
t
EFW  
INA±  
INB±  
INA± ,  
INB±  
t
B
BIT CENTER  
BIT CENTER  
SAMPLE WINDOW  
Document #: 38-02002 Rev. *B  
Page 39 of 48  
PRELIMINARY  
CYP15G0401DXA  
the bits E, D, C, B, and A in that order, and the y is the decimal value  
of the binary number composed of the bits H, G, and F in that order.  
When c is set to K, xx and y are derived by comparing the encoded  
bit patterns of the Special Character to those patterns derived from  
encoded Valid Data bytes and selecting the names of the patterns  
most similar to the encoded bit patterns of the Special Character.  
X3.230 Codes and Notation Conventions  
Information to be transmitted over a serial link is encoded eight  
bits at a time into a 10-bit Transmission Character and then  
sent serially, bit by bit. Information received over a serial link is  
collected ten bits at a time, and those Transmission Characters  
that are used for data (Data Characters) are decoded into the  
correct eight-bit codes. The 10-bit Transmission Code sup-  
ports all 256 8-bit combinations. Some of the remaining Trans-  
mission Characters (Special Characters) are used for func-  
tions other than data transmission.  
Under the above conventions, the Transmission Character  
used for the examples above, is referred to by the name D5.2.  
The Special Character K29.7 is so named because the first six  
bits (abcdei) of this character make up a bit pattern similar to  
that resulting from the encoding of the unencoded 11101 pat-  
tern (29), and because the second four bits (fghj) make up a  
bit pattern similar to that resulting from the encoding of the  
unencoded 111 pattern (7).  
The primary rationale for use of a Transmission Code is to  
improve the transmission characteristics of a serial link. The  
encoding defined by the Transmission Code ensures that suf-  
ficient transitions are present in the serial bit stream to make  
clock recovery possible at the Receiver. Such encoding also  
greatly increases the likelihood of detecting any single or mul-  
tiple bit errors that may occur during transmission and recep-  
tion of information. In addition, some Special Characters of the  
Transmission Code selected by Fibre Channel Standard con-  
sist of a distinct and easily recognizable bit pattern (the Special  
Character COMMA) that assists a Receiver in achieving word  
alignment on the incoming bit stream.  
Note: This definition of the 10-bit Transmission Code is based  
on (and is in basic agreement with) the following references,  
which describe the same 10-bit transmission code.  
A.X. Widmer and P.A. Franaszek. A DC-Balanced, Parti-  
tioned-Block, 8B/10B Transmission CodeIBM Journal of Re-  
search and Development, 27, No. 5: 440451 (September, 1983).  
U.S. Patent 4,486,739. Peter A. Franaszek and Albert X. Wid-  
mer. Byte-Oriented DC Balanced (0.4) 8B/10B Partitioned  
Block Transmission Code(December 4, 1984).  
Notation Conventions  
Fibre Channel Physical and Signaling Interface (ANS X3.230−  
1994 ANSI FCPH Standard).  
IBM Enterprise Systems Architecture/390 ESCON I/O Inter-  
The documentation for the 8B/10B Transmission Code uses  
letter notation for the bits in an 8-bit byte. Fibre Channel Stan-  
dard notation uses a bit notation of A, B, C, D, E, F, G, H for  
the 8-bit byte for the raw 8-bit data, and the letters a, b, c, d, e,  
i, f, g, h, j for encoded 10-bit data. There is a correspondence  
between bit A and bit a, B and b, C and c, D and d, E and e, F  
and f, G and g, and H and h. Bits i and j are derived, respec-  
tively, from (A,B,C,D,E) and (F,G,H).  
face (document number SA227202).  
8B/10B Transmission Code  
The following information describes how the tables shall be  
used for both generating valid Transmission Characters (en-  
coding) and checking the validity of received Transmission  
Characters (decoding). It also specifies the ordering rules to  
be followed when transmitting the bits within a character and  
the characters within the higher-level constructs specified by  
the standard.  
The bit labeled A in the description of the 8B/10B Transmission  
Code corresponds to bit 0 in the numbering scheme of the FC-  
2 specification, B corresponds to bit 1, as shown below.  
FC-2 bit designation—  
HOTLink D/Q designation7  
8B/10B bit designation—  
7
6
6
G F  
5
5
4
4
E
3
3
D
2
2
C
1
1
B
0
0
A
H
Transmission Order  
To clarify this correspondence, the following example shows  
the conversion from an FC-2 Valid Data Byte to a Transmission  
Character (using 8B/10B Transmission Code notation)  
Within the definition of the 8B/10B Transmission Code, the bit  
positions of the Transmission Characters are labeled a, b, c, d,  
e, i, f, g, h, j. Bit ashall be transmitted first followed by bits b,  
c, d, e, i, f, g, h, and j in that order. (Note that bit i shall be  
transmitted between bit e and bit f, rather than in alphabetical  
order.)  
FC-2 45  
Bits: 7654 3210  
0100 0101  
Converted to 8B/10B notation (note carefully that the order of  
bits is reversed):  
Valid and Invalid Transmission Characters  
The following tables define the valid Data Characters and valid  
Special Characters (K characters), respectively. The tables are  
used for both generating valid Transmission Characters (en-  
coding) and checking the validity of received Transmission  
Characters (decoding). In the tables, each Valid-Data-byte or  
Special-Character-code entry has two columns that represent  
two (not necessarily different) Transmission Characters. The  
two columns correspond to the current value of the running  
disparity (Current RDor Current RD+). Running disparity  
is a binary parameter with either the value negative () or the  
value positive (+).  
Data Byte Name  
D5.2  
Bits:ABCDEFGH  
10100 010  
Translated to a transmission Character in the 8B/10B Trans-  
mission Code:  
Bits: abcdeifghj  
1010010101  
Each valid Transmission Character of the 8B/10B Transmis-  
sion Code has been given a name using the following conven-  
tion: cxx.y, where c is used to show whether the Transmission  
Character is a Data Character (c is set to D, and SC/D = LOW)  
or a Special Character (c is set to K, and SC/D = HIGH). When c is  
set to D, xx is the decimal value of the binary number composed of  
After powering on, the Transmitter may assume either a posi-  
tive or negative value for its initial running disparity. Upon  
transmission of any Transmission Character, the transmitter  
will select the proper version of the Transmission Character  
Document #: 38-02002 Rev. *B  
Page 40 of 48  
PRELIMINARY  
CYP15G0401DXA  
based on the current running disparity value, and the Trans-  
mitter shall calculate a new value for its running disparity  
based on the contents of the transmitted character. Special  
Character codes C1.7 and C2.7 can be used to force the trans-  
mission of a specific Special Character with a specific running  
disparity as required for some special sequences in X3.230.  
be used as the Transmitters current running disparity for the  
next Valid Data byte or Special Character byte to be encoded  
and transmitted. Table 22 shows naming notations and examples  
of valid transmission characters.  
Use of the Tables for Checking the Validity of Received  
Transmission Characters  
After powering on, the Receiver may assume either a positive  
or negative value for its initial running disparity. Upon reception  
of any Transmission Character, the Receiver shall decide  
whether the Transmission Character is valid or invalid accord-  
ing to the following rules and tables and shall calculate a new  
value for its Running Disparity based on the contents of the  
received character.  
The column corresponding to the current value of the Receiv-  
ers running disparity shall be searched for the received Trans-  
mission Character. If the received Transmission Character is  
found in the proper column, then the Transmission Character  
is valid and the associated Data byte or Special Character  
code is determined (decoded). If the received Transmission  
Character is not found in that column, then the Transmission  
Character is invalid. This is called a code violation. Indepen-  
dent of the Transmission Characters validity, the received  
Transmission Character shall be used to calculate a new value  
of running disparity. The new value shall be used as the Re-  
ceivers current running disparity for the next received Trans-  
mission Character.  
The following rules for running disparity shall be used to cal-  
culate the new running-disparity value for Transmission Char-  
acters that have been transmitted (Transmitters running dis-  
parity) and that have been received (Receivers running  
disparity).  
Running disparity for a Transmission Character shall be calcu-  
lated from sub-blocks, where the first six bits (abcdei) form one  
sub-block and the second four bits (fghj) form the other sub-  
block. Running disparity at the beginning of the 6-bit sub-block  
is the running disparity at the end of the previous Transmission  
Character. Running disparity at the beginning of the 4-bit sub-  
block is the running disparity at the end of the 6-bit sub-block.  
Running disparity at the end of the Transmission Character is  
the running disparity at the end of the 4-bit sub-block.  
Table 22. Valid Transmission Characters  
Data  
DIN or QOUT  
Byte Name  
765  
43210  
Hex Value  
D0.0  
000  
00000  
00  
Running disparity for the sub-blocks shall be calculated as fol-  
lows:  
D1.0  
D2.0  
000  
000  
00001  
00010  
01  
02  
1. Running disparity at the end of any sub-block is positive if  
the sub-block contains more ones than zeros. It is also pos-  
itive at the end of the 6-bit sub-block if the 6-bit sub-block is  
000111, and it is positive at the end of the 4-bit sub-block if  
the 4-bit sub-block is 0011.  
.
.
.
.
.
.
.
.
D5.2  
010  
00010  
1
45  
2. Running disparity at the end of any sub-block is negative if  
the sub-block contains more zeros than ones. It is also neg-  
ative at the end of the 6-bit sub-block if the 6-bit sub-block  
is 111000, and it is negative at the end of the 4-bit sub-block  
if the 4-bit sub-block is 1100.  
.
.
.
.
.
.
.
.
D30.7  
D31.7  
111  
111  
11110  
11111  
FE  
FF  
3. Otherwise, running disparity at the end of the sub-block is  
the same as at the beginning of the sub-block.  
Use of the Tables for Generating Transmission Characters  
Detection of a code violation does not necessarily show that  
the Transmission Character in which the code violation was  
detected is in error. Code violations may result from a prior  
error that altered the running disparity of the bit stream which  
did not result in a detectable error at the Transmission Char-  
acter in which the error occurred. Table 23 shows an example  
of this behavior.  
The appropriate entry in the table shall be found for the Valid  
Data byte or the Special Character byte for which a Transmis-  
sion Character is to be generated (encoded). The current val-  
ue of the Transmitters running disparity shall be used to select  
the Transmission Character from its corresponding column.  
For each Transmission Character transmitted, a new value of  
the running disparity shall be calculated. This new value shall  
Table 23. Code Violations Resulting from Prior Errors  
RD  
Character  
D21.1  
RD  
Character  
D10.2  
RD  
Character  
D23.5  
RD  
+
Transmitted data character  
Transmitted bit stream  
Bit stream after error  
101010 1001  
101010 1011  
D21.0  
010101 0101  
010101 0101  
D10.2  
111010 1010  
111010 1010  
Code Violation  
+
+
+
+
Decoded data character  
+
+
+
Document #: 38-02002 Rev. *B  
Page 41 of 48  
PRELIMINARY  
CYP15G0401DXA  
Table 24. Valid Data Characters (TXCTx[0] = 0, RXSTx[2:0] = 000)  
Data  
Byte  
Data  
Byte  
Name HGF EDCBA  
Bits  
Current RD−  
Current RD+  
abcdei fghj  
Bits  
Current RD−  
abcdei fghj  
Current RD+  
abcdei fghj  
Name HGF EDCBA  
abcdei fghj  
D0.0  
D1.0  
000 00000  
000 00001  
000 00010  
000 00011  
000 00100  
000 00101  
000 00110  
000 00111  
000 01000  
000 01001  
000 01010  
000 01011  
000 01100  
000 01101  
000 01110  
000 01111  
000 10000  
000 10001  
000 10010  
000 10011  
000 10100  
000 10101  
000 10110  
000 10111  
000 11000  
000 11001  
000 11010  
000 11011  
000 11100  
000 11101  
000 11110  
000 11111  
100111 0100 011000 1011  
011101 0100 100010 1011  
101101 0100 010010 1011  
110001 1011 110001 0100  
110101 0100 001010 1011  
101001 1011 101001 0100  
011001 1011 011001 0100  
111000 1011 000111 0100  
111001 0100 000110 1011  
100101 1011 100101 0100  
010101 1011 010101 0100  
110100 1011 110100 0100  
001101 1011 001101 0100  
101100 1011 101100 0100  
011100 1011 011100 0100  
010111 0100 101000 1011  
011011 0100 100100 1011  
100011 1011 100011 0100  
010011 1011 010011 0100  
110010 1011 110010 0100  
001011 1011 001011 0100  
101010 1011 101010 0100  
011010 1011 011010 0100  
111010 0100 000101 1011  
110011 0100 001100 1011  
100110 1011 100110 0100  
010110 1011 010110 0100  
110110 0100 001001 1011  
001110 1011 001110 0100  
101110 0100 010001 1011  
011110 0100 100001 1011  
101011 0100 010100 1011  
D0.1  
D1.1  
001 00000  
001 00001  
001 00010  
001 00011  
001 00100  
001 00101  
001 00110  
001 00111  
001 01000  
001 01001  
001 01010  
001 01011  
001 01100  
001 01101  
001 01110  
001 01111  
001 10000  
001 10001  
001 10010  
001 10011  
001 10100  
001 10101  
001 10110  
001 10111  
001 11000  
001 11001  
001 11010  
001 11011  
001 11100  
001 11101  
001 11110  
001 11111  
100111 1001 011000 1001  
011101 1001 100010 1001  
101101 1001 010010 1001  
110001 1001 110001 1001  
110101 1001 001010 1001  
101001 1001 101001 1001  
011001 1001 011001 1001  
111000 1001 000111 1001  
111001 1001 000110 1001  
100101 1001 100101 1001  
010101 1001 010101 1001  
110100 1001 110100 1001  
001101 1001 001101 1001  
101100 1001 101100 1001  
011100 1001 011100 1001  
010111 1001 101000 1001  
011011 1001 100100 1001  
100011 1001 100011 1001  
010011 1001 010011 1001  
110010 1001 110010 1001  
001011 1001 001011 1001  
101010 1001 101010 1001  
011010 1001 011010 1001  
111010 1001 000101 1001  
110011 1001 001100 1001  
100110 1001 100110 1001  
010110 1001 010110 1001  
110110 1001 001001 1001  
001110 1001 001110 1001  
101110 1001 010001 1001  
011110 1001 100001 1001  
101011 1001 010100 1001  
D2.0  
D2.1  
D3.0  
D3.1  
D4.0  
D4.1  
D5.0  
D5.1  
D6.0  
D6.1  
D7.0  
D7.1  
D8.0  
D8.1  
D9.0  
D9.1  
D10.0  
D11.0  
D12.0  
D13.0  
D14.0  
D15.0  
D16.0  
D17.0  
D18.0  
D19.0  
D20.0  
D21.0  
D22.0  
D23.0  
D24.0  
D25.0  
D26.0  
D27.0  
D28.0  
D29.0  
D30.0  
D31.0  
D10.1  
D11.1  
D12.1  
D13.1  
D14.1  
D15.1  
D16.1  
D17.1  
D18.1  
D19.1  
D20.1  
D21.1  
D22.1  
D23.1  
D24.1  
D25.1  
D26.1  
D27.1  
D28.1  
D29.1  
D30.1  
D31.1  
Document #: 38-02002 Rev. *B  
Page 42 of 48  
PRELIMINARY  
CYP15G0401DXA  
Table 24. Valid Data Characters (TXCTx[0] = 0, RXSTx[2:0] = 000) (continued)  
Data  
Byte  
Data  
Byte  
Bits  
Current RD−  
Current RD+  
abcdei fghj  
Bits  
Current RD−  
abcdei fghj  
Current RD+  
abcdei fghj  
Name HGF EDCBA  
abcdei fghj  
Name HGF EDCBA  
D0.2  
D1.2  
010 00000  
010 00001  
010 00010  
010 00011  
010 00100  
010 00101  
010 00110  
010 00111  
010 01000  
010 01001  
010 01010  
010 01011  
010 01100  
010 01101  
010 01110  
010 01111  
010 10000  
010 10001  
010 10010  
010 10011  
010 10100  
010 10101  
010 10110  
010 10111  
010 11000  
010 11001  
010 11010  
010 11011  
010 11100  
010 11101  
010 11110  
010 11111  
100111 0101 011000 0101  
011101 0101 100010 0101  
101101 0101 010010 0101  
110001 0101 110001 0101  
110101 0101 001010 0101  
101001 0101 101001 0101  
011001 0101 011001 0101  
111000 0101 000111 0101  
111001 0101 000110 0101  
100101 0101 100101 0101  
010101 0101 010101 0101  
110100 0101 110100 0101  
001101 0101 001101 0101  
101100 0101 101100 0101  
011100 0101 011100 0101  
010111 0101 101000 0101  
011011 0101 100100 0101  
100011 0101 100011 0101  
010011 0101 010011 0101  
110010 0101 110010 0101  
001011 0101 001011 0101  
101010 0101 101010 0101  
011010 0101 011010 0101  
111010 0101 000101 0101  
110011 0101 001100 0101  
100110 0101 100110 0101  
010110 0101 010110 0101  
110110 0101 001001 0101  
001110 0101 001110 0101  
101110 0101 010001 0101  
011110 0101 100001 0101  
101011 0101 010100 0101  
D0.3  
D1.3  
011 00000  
011 00001  
011 00010  
011 00011  
011 00100  
011 00101  
011 00110  
011 00111  
011 01000  
011 01001  
011 01010  
011 01011  
011 01100  
011 01101  
011 01110  
011 01111  
011 10000  
011 10001  
011 10010  
011 10011  
011 10100  
011 10101  
011 10110  
011 10111  
011 11000  
011 11001  
011 11010  
011 11011  
011 11100  
011 11101  
011 11110  
011 11111  
100111 0011 011000 1100  
011101 0011 100010 1100  
101101 0011 010010 1100  
110001 1100 110001 0011  
110101 0011 001010 1100  
101001 1100 101001 0011  
011001 1100 011001 0011  
111000 1100 000111 0011  
111001 0011 000110 1100  
100101 1100 100101 0011  
010101 1100 010101 0011  
110100 1100 110100 0011  
001101 1100 001101 0011  
101100 1100 101100 0011  
011100 1100 011100 0011  
010111 0011 101000 1100  
011011 0011 100100 1100  
100011 1100 100011 0011  
010011 1100 010011 0011  
110010 1100 110010 0011  
001011 1100 001011 0011  
101010 1100 101010 0011  
011010 1100 011010 0011  
111010 0011 000101 1100  
110011 0011 001100 1100  
100110 1100 100110 0011  
010110 1100 010110 0011  
110110 0011 001001 1100  
001110 1100 001110 0011  
101110 0011 010001 1100  
011110 0011 100001 1100  
101011 0011 010100 1100  
D2.2  
D2.3  
D3.2  
D3.3  
D4.2  
D4.3  
D5.2  
D5.3  
D6.2  
D6.3  
D7.2  
D7.3  
D8.2  
D8.3  
D9.2  
D9.3  
D10.2  
D11.2  
D12.2  
D13.2  
D14.2  
D15.2  
D16.2  
D17.2  
D18.2  
D19.2  
D20.2  
D21.2  
D22.2  
D23.2  
D24.2  
D25.2  
D26.2  
D27.2  
D28.2  
D29.2  
D30.2  
D31.2  
D10.3  
D11.3  
D12.3  
D13.3  
D14.3  
D15.3  
D16.3  
D17.3  
D18.3  
D19.3  
D20.3  
D21.3  
D22.3  
D23.3  
D24.3  
D25.3  
D26.3  
D27.3  
D28.3  
D29.3  
D30.3  
D31.3  
Document #: 38-02002 Rev. *B  
Page 43 of 48  
PRELIMINARY  
CYP15G0401DXA  
Table 24. Valid Data Characters (TXCTx[0] = 0, RXSTx[2:0] = 000) (continued)  
Data  
Byte  
Data  
Byte  
Bits  
Current RD−  
Current RD+  
abcdei fghj  
Bits  
Current RD−  
abcdei fghj  
Current RD+  
abcdei fghj  
Name HGF EDCBA  
abcdei fghj  
Name HGF EDCBA  
D0.4  
D1.4  
100 00000  
100 00001  
100 00010  
100 00011  
100 00100  
100 00101  
100 00110  
100 00111  
100 01000  
100 01001  
100 01010  
100 01011  
100 01100  
100 01101  
100 01110  
100 01111  
100 10000  
100 10001  
100 10010  
100 10011  
100 10100  
100 10101  
100 10110  
100 10111  
100 11000  
100 11001  
100 11010  
100 11011  
100 11100  
100 11101  
100 11110  
100 11111  
100111 0010 011000 1101  
011101 0010 100010 1101  
101101 0010 010010 1101  
110001 1101 110001 0010  
110101 0010 001010 1101  
101001 1101 101001 0010  
011001 1101 011001 0010  
111000 1101 000111 0010  
111001 0010 000110 1101  
100101 1101 100101 0010  
010101 1101 010101 0010  
110100 1101 110100 0010  
001101 1101 001101 0010  
101100 1101 101100 0010  
011100 1101 011100 0010  
010111 0010 101000 1101  
011011 0010 100100 1101  
100011 1101 100011 0010  
010011 1101 010011 0010  
110010 1101 110010 0010  
001011 1101 001011 0010  
101010 1101 101010 0010  
011010 1101 011010 0010  
111010 0010 000101 1101  
110011 0010 001100 1101  
100110 1101 100110 0010  
010110 1101 010110 0010  
110110 0010 001001 1101  
001110 1101 001110 0010  
101110 0010 010001 1101  
011110 0010 100001 1101  
101011 0010 010100 1101  
D0.5  
D1.5  
101 00000  
101 00001  
101 00010  
101 00011  
101 00100  
101 00101  
101 00110  
101 00111  
101 01000  
101 01001  
101 01010  
101 01011  
101 01100  
101 01101  
101 01110  
101 01111  
101 10000  
101 10001  
101 10010  
101 10011  
101 10100  
101 10101  
101 10110  
101 10111  
101 11000  
101 11001  
101 11010  
101 11011  
101 11100  
101 11101  
101 11110  
101 11111  
100111 1010 011000 1010  
011101 1010 100010 1010  
101101 1010 010010 1010  
110001 1010 110001 1010  
110101 1010 001010 1010  
101001 1010 101001 1010  
011001 1010 011001 1010  
111000 1010 000111 1010  
111001 1010 000110 1010  
100101 1010 100101 1010  
010101 1010 010101 1010  
110100 1010 110100 1010  
001101 1010 001101 1010  
101100 1010 101100 1010  
011100 1010 011100 1010  
010111 1010 101000 1010  
011011 1010 100100 1010  
100011 1010 100011 1010  
010011 1010 010011 1010  
110010 1010 110010 1010  
001011 1010 001011 1010  
101010 1010 101010 1010  
011010 1010 011010 1010  
111010 1010 000101 1010  
110011 1010 001100 1010  
100110 1010 100110 1010  
010110 1010 010110 1010  
110110 1010 001001 1010  
001110 1010 001110 1010  
101110 1010 010001 1010  
011110 1010 100001 1010  
101011 1010 010100 1010  
D2.4  
D2.5  
D3.4  
D3.5  
D4.4  
D4.5  
D5.4  
D5.5  
D6.4  
D6.5  
D7.4  
D7.5  
D8.4  
D8.5  
D9.4  
D9.5  
D10.4  
D11.4  
D12.4  
D13.4  
D14.4  
D15.4  
D16.4  
D17.4  
D18.4  
D19.4  
D20.4  
D21.4  
D22.4  
D23.4  
D24.4  
D25.4  
D26.4  
D27.4  
D28.4  
D29.4  
D30.4  
D31.4  
D10.5  
D11.5  
D12.5  
D13.5  
D14.5  
D15.5  
D16.5  
D17.5  
D18.5  
D19.5  
D20.5  
D21.5  
D22.5  
D23.5  
D24.5  
D25.5  
D26.5  
D27.5  
D28.5  
D29.5  
D30.5  
D31.5  
Document #: 38-02002 Rev. *B  
Page 44 of 48  
PRELIMINARY  
CYP15G0401DXA  
Table 24. Valid Data Characters (TXCTx[0] = 0, RXSTx[2:0] = 000) (continued)  
Data  
Byte  
Data  
Byte  
Bits  
Current RD−  
Current RD+  
abcdei fghj  
Bits  
Current RD−  
abcdei fghj  
Current RD+  
abcdei fghj  
Name HGF EDCBA  
abcdei fghj  
Name HGF EDCBA  
D0.6  
D1.6  
110 00000  
110 00001  
110 00010  
110 00011  
110 00100  
110 00101  
110 00110  
110 00111  
110 01000  
110 01001  
110 01010  
110 01011  
110 01100  
110 01101  
110 01110  
110 01111  
110 10000  
110 10001  
110 10010  
110 10011  
110 10100  
110 10101  
110 10110  
110 10111  
110 11000  
110 11001  
110 11010  
110 11011  
110 11100  
110 11101  
110 11110  
110 11111  
100111 0110 011000 0110  
011101 0110 100010 0110  
101101 0110 010010 0110  
110001 0110 110001 0110  
110101 0110 001010 0110  
101001 0110 101001 0110  
011001 0110 011001 0110  
111000 0110 000111 0110  
111001 0110 000110 0110  
100101 0110 100101 0110  
010101 0110 010101 0110  
110100 0110 110100 0110  
001101 0110 001101 0110  
101100 0110 101100 0110  
011100 0110 011100 0110  
010111 0110 101000 0110  
011011 0110 100100 0110  
100011 0110 100011 0110  
010011 0110 010011 0110  
110010 0110 110010 0110  
001011 0110 001011 0110  
101010 0110 101010 0110  
011010 0110 011010 0110  
111010 0110 000101 0110  
110011 0110 001100 0110  
100110 0110 100110 0110  
010110 0110 010110 0110  
110110 0110 001001 0110  
001110 0110 001110 0110  
101110 0110 010001 0110  
011110 0110 100001 0110  
101011 0110 010100 0110  
D0.7  
D1.7  
111 00000  
111 00001  
111 00010  
111 00011  
111 00100  
111 00101  
111 00110  
111 00111  
111 01000  
111 01001  
111 01010  
111 01011  
111 01100  
111 01101  
111 01110  
111 01111  
111 10000  
111 10001  
111 10010  
111 10011  
111 10100  
111 10101  
111 10110  
111 10111  
111 11000  
111 11001  
111 11010  
111 11011  
111 11100  
111 11101  
111 11110  
111 11111  
100111 0001 011000 1110  
011101 0001 100010 1110  
101101 0001 010010 1110  
110001 1110 110001 0001  
110101 0001 001010 1110  
101001 1110 101001 0001  
011001 1110 011001 0001  
111000 1110 000111 0001  
111001 0001 000110 1110  
100101 1110 100101 0001  
010101 1110 010101 0001  
110100 1110 110100 1000  
001101 1110 001101 0001  
101100 1110 101100 1000  
011100 1110 011100 1000  
010111 0001 101000 1110  
011011 0001 100100 1110  
100011 0111 100011 0001  
010011 0111 010011 0001  
110010 1110 110010 0001  
001011 0111 001011 0001  
101010 1110 101010 0001  
011010 1110 011010 0001  
111010 0001 000101 1110  
110011 0001 001100 1110  
100110 1110 100110 0001  
010110 1110 010110 0001  
110110 0001 001001 1110  
001110 1110 001110 0001  
101110 0001 010001 1110  
011110 0001 100001 1110  
101011 0001 010100 1110  
D2.6  
D2.7  
D3.6  
D3.7  
D4.6  
D4.7  
D5.6  
D5.7  
D6.6  
D6.7  
D7.6  
D7.7  
D8.6  
D8.7  
D9.6  
D9.7  
D10.6  
D11.6  
D12.6  
D13.6  
D14.6  
D15.6  
D16.6  
D17.6  
D18.6  
D19.6  
D20.6  
D21.6  
D22.6  
D23.6  
D24.6  
D25.6  
D26.6  
D27.6  
D28.6  
D29.6  
D30.6  
D31.6  
D10.7  
D11.7  
D12.7  
D13.7  
D14.7  
D15.7  
D16.7  
D17.7  
D18.7  
D19.7  
D20.7  
D21.7  
D22.7  
D23.7  
D24.7  
D25.7  
D26.7  
D27.7  
D28.7  
D29.7  
D30.7  
D31.7  
Document #: 38-02002 Rev. *B  
Page 45 of 48  
PRELIMINARY  
CYP15G0401DXA  
Table 25. Valid Special Character Codes and Sequences (TXCTx = special character code or RXSTx[2:0] = 001)[33, 34]  
S.C. Byte Name  
Cypress  
S.C. Byte  
Alternate  
S.C. Code  
Name  
Bits  
HGF EDCBA  
S.C. Byte  
Bits  
Current RD−  
Current RD+  
abcdei fghj  
Name[35]  
C0.0  
Name[35]  
HGF EDCBA  
abcdei fghj  
K28.0  
(C00)  
(C01)  
(C02)  
(C03)  
(C04)  
(C05)  
(C06)  
(C07)  
(C08)  
(C09)  
000 00000  
000 00001  
000 00010  
000 00011  
000 00100  
000 00101  
000 00110  
000 00111  
000 01000  
000 01001  
000 01010  
000 01011  
C28.0 (C1C)  
C28.1 (C3C)  
C28.2 (C5C)  
C28.3 (C7C)  
C28.4 (C9C)  
C28.5 (CBC)  
C28.6 (CDC)  
C28.7 (CFC)  
C23.7 (CF7)  
C27.7 (CFB)  
C29.7 (CFD)  
C30.7 (CFE)  
000 11100  
001 11100  
010 11100  
011 11100  
100 11100  
101 11100  
110 11100  
111 11100  
111 10111  
111 11011  
111 11101  
111 11110  
001111 0100  
001111 1001  
001111 0101  
001111 0011  
001111 0010  
001111 1010  
001111 0110  
001111 1000  
111010 1000  
110110 1000  
101110 1000  
011110 1000  
110000 1011  
110000 0110  
110000 1010  
110000 1100  
110000 1101  
110000 0101  
110000 1001  
110000 0111  
000101 0111  
001001 0111  
010001 0111  
100001 0111  
K28.1 [36]  
K28.2 [36]  
K28.3  
K28.4 [36]  
K28.5 [36, 37]  
K28.6 [36]  
K28.7 [36, 38]  
K23.7  
C1.0  
C2.0  
C3.0  
C4.0  
C5.0  
C6.0  
C7.0  
C8.0  
C9.0  
K27.7  
K29.7  
C10.0 (C0A)  
C11.0 (C0B)  
K30.7  
End of Frame Sequence  
EOFxx C2.1  
(C22)  
001 00010  
C2.1  
(C22)  
001 00010  
K28.5,Dn.xxx0[39] +K28.5,Dn.xxx1[39  
]
Code Rule Violation and SVS Tx Pattern  
Exception [38, 40] C0.7  
(CE0)  
(CE1)  
(CE2)  
111 00000  
111 00001  
111 00010  
C0.7  
C1.7  
C2.7  
(CE0) 111 00000 [44]  
(CE1) 111 00001 [44]  
(CE2) 111 00010 [44]  
100111 1000  
001111 1010  
110000 0101  
011000 0111  
001111 1010  
110000 0101  
K28.5[41]  
C1.7  
C2.7  
+K28.5 [42]  
Running Disparity Violation Pattern  
Exception [43]  
C4.7  
(CE4)  
111 00100  
C4.7  
(CE4) 111 00100 [44]  
110111 0101  
001000 1010  
Notes:  
33. All codes not shown are reserved.  
34. Notation for Special Character Code Name is consistent with Fibre Channel and ESCON naming conventions. Special Character Code Name is intended to  
describe binary information present on I/O pins. Common usage for the name can either be in the form used for describing Data patterns (i.e., C0.0 through  
C31.7), or in hex notation (i.e., Cnn where nn = the specified value between 00 and FF).  
35. Both the Cypress and alternate encodings may be used for data transmission to generate specific Special Character Codes. The decoding process for received  
characters generates Cypress codes or Alternate codes as selected by the RXMODE[1:0] configuration inputs.  
36. These characters are used for control of ESCON interfaces. They can be sent as embedded commands or other markers when not operating using ESCON  
protocols.  
37. The K28.5 character is used for framing operations by the receiver. It is also the pad or fill character transmitted to maintain the serial link when no user data  
is available.  
38. Care must be taken when using this Special Character code. When a C7.0 is followed by a D11.x or D20.x, or when an SVS (C0.7) is followed by a D11.x,  
an alias K28.5 sync character is created. These sequences can cause erroneous framing and should be avoided while RFEN = HIGH.  
39. C2.1 = Transmit either K28.5+ or +K28.5as determined by Current RD and modify the Transmission Character that follows, by setting its least significant  
bit to 1 or 0. If Current RD at the start of the following character is plus (+) the LSB is set to 0, and if Current RD is minus () the LSB becomes 1. This  
modification allows construction of X3.230 EOFframe delimiters wherein the second data byte is determined by the Current RD.  
For example, to send EOFdtthe controller could issue the sequence C2.1D21.4D21.4D21.4, and the HOTLink Transmitter will send either K28.5D21.4−  
D21.4D21.4 or K28.5D21.5D21.4D21.4 based on Current RD. Likewise to send EOFdtithe controller could issue the sequence C2.1D10.4D21.4−  
D21.4, and the HOTLink Transmitter will send either K28.5D10.4D21.4D21.4 or K28.5D10.5D21.4D21.4 based on Current RD.  
The receiver will never output this Special Character, since K28.5 is decoded as C5.0, C1.7, or C2.7, and the subsequent bytes are decoded as data.  
40. C0.7 = Transmit a deliberate code rule violation. The code chosen for this function follows the normal Running Disparity rules. Transmission of this Special  
Character has the same effect as asserting TXSVS = HIGH. The receiver will only output this Special Character if the Transmission Character being decoded  
is not found in the tables.  
41. C1.7 = Transmit Negative K28.5 (K28.5+) disregarding Current RD. The receiver will only output this Special Character if K28.5 is received with the wrong  
running disparity. The receiver will output C1.7 if K28.5 is received with RD+, otherwise K28.5 is decoded as C5.0 or C2.7.  
42. C2.7 = Transmit Positive K28.5 (+K28.5) disregarding Current RD. The receiver will only output this Special Character if K28.5 is received with the wrong  
running disparity. The receiver will output C2.7 if +K28.5 is received with RD, otherwise K28.5 is decoded as C5.0 or C1.7.  
43. C4.7 = Transmit a deliberate code rule violation to indicate a Running Disparity violation. The receiver will only output this Special Character if the Transmission  
Character being decoded is found in the tables, but Running Disparity does not match. This might indicate that an error occurred in a prior byte.  
44. Supported only for data transmission. The receive status for these conditions will be reported by specific combinations of receive status bits.  
Document #: 38-02002 Rev. *B  
Page 46 of 48  
PRELIMINARY  
CYP15G0401DXA  
Ordering Information  
Operating  
Range  
Speed  
Standard  
Standard  
Ordering Code  
Package Name  
Package Type  
CYP15G0401DXA-BGC  
CYP15G0401DXA-BGI  
BL256  
BL256  
256-Ball Thermally Enhanced Ball Grid Array Commercial  
256-Ball Thermally Enhanced Ball Grid Array Industrial  
HOTLink II, and MultiFrame are trademarks of Cypress Semiconductor Corporation.  
IBM is a registered trademark of International Business Machines.  
ESCON is a registered trademark of International Business Machines.  
FICON is a trademark of International Business Machines.  
Package Diagram  
256-Lead Thermally Enhanced L2BGA (27 x 27 x 1.52 mm) BL256  
51-85123  
Document #: 38-02002 Rev. *B  
Page 47 of 48  
PRELIMINARY  
CYP15G0401DXA  
Revision History  
Document Title: CYP15G0401DXA Quad HOTLink IITransceiver (Preliminary)  
Document Number: 38-02002  
ISSUE  
ORIG. OF  
REV.  
**  
ECN NO. DATE  
CHANGE DESCRIPTION OF CHANGE  
105840  
108025  
108437  
03/21/01  
06/20/01  
07/19/01  
SZV  
AMV  
TME  
Change from Spec number: 38-00876 to 38-02002  
Changed Marketing part number  
Change Marketing part number from CYP15G0401DX to CYP15G0401DXA  
*A  
*B  
Document #: 38-02002 Rev. *B  
Page 48 of 48  
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
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