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HYS64T32020HDL-2.5-A

型号：

HYS64T32020HDL-2.5-A

品牌：

INFINEON[ Infineon ]

页数：

46 页

PDF大小：

820 K

下载PDF手册
Data Sheet, Rev. 1.1, Jun 2005  
HYS64T16000HDL–[2.5/3.7/5]–A  
HYS64T32020HDL–2.5–A  
HYS64T64021HDL–2.5–A  
200-Pin Small-Outline-DDR2-SDRAM Modules  
SO-DIMM  
DDR2 SDRAM  
RoHS Compliant  
Memory Products  
N e v e r s t o p t h i n k i n g .  
Edition 2005-06  
Published by Infineon Technologies AG,  
St.-Martin-Strasse 53,  
81669 München, Germany  
© Infineon Technologies AG 2005.  
All Rights Reserved.  
Attention please!  
The information herein is given to describe certain components and shall not be considered as a guarantee of  
characteristics.  
Terms of delivery and rights to technical change reserved.  
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding  
circuits, descriptions and charts stated herein.  
Information  
For further information on technology, delivery terms and conditions and prices please contact your nearest  
Infineon Technologies Office (www.infineon.com).  
Warnings  
Due to technical requirements components may contain dangerous substances. For information on the types in  
question please contact your nearest Infineon Technologies Office.  
Infineon Technologies Components may only be used in life-support devices or systems with the express written  
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure  
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support  
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain  
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may  
be endangered.  
HYS64T16000HDL–[2.5/3.7/5]–A, HYS64T32020HDL–2.5–A, HYS64T64021HDL–2.5–A  
Revision History: 2005-05, Rev. 1.1  
Page  
Subjects (major changes since last revision)  
Extend product definition including DDR2-800  
Chapter 3 Update of IDD Currents  
Chapter 4 Update of SPD Codes  
Previous Version: 2004-04, Rev. 1.01  
Only green products included  
IDD currents updated  
We Listen to Your Comments  
Any information within this document that you feel is wrong, unclear or missing at all?  
Your feedback will help us to continuously improve the quality of this document.  
Please send us your proposal (including a reference to this document) to:  
techdoc.mp@infineon.com  
Template: mp_a4_s_rev314 / 3 / 2005-05-02  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
Table of Contents  
Table of Contents  
1
1.1  
1.2  
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
2
2.1  
2.2  
Pin Configuration and Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
3
3.1  
3.2  
3.3  
3.3.1  
3.3.2  
3.3.3  
3.4  
3.4.1  
3.4.2  
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
I
DD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
DD Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
On Die Termination (ODT) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
I
4
5
6
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39  
Product Type Nomenclature (DDR2 DRAMs and DIMMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42  
Data Sheet  
1
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
200-Pin Small-Outline-DDR2-SDRAM Modules  
SO-DIMM  
HYS64T16000HDL–[2.5/3.7/5]–A  
HYS64T32020HDL–2.5–A  
HYS64T64021HDL–2.5–A  
1
Overview  
This chapter gives an overview of the 200-Pin Small-Outline-DDR2-SDRAM Modules product family and  
describes its main characteristics.  
1.1  
Features  
•
200-pin PC2-6400, PC2-4200 and PC2-3200  
DDR2 SDRAM memory modules for use as main  
memory when installed in systems such as mobile  
personal computers.  
16M × 64, 32M × 64, 64Mx64 module organization,  
and 16M × 16, 32M × 8 chip organization  
128, 256 and 512 MByte modules built with 256-  
Mbit DDR2 SDRAMs in P-TFBGA-60 and P-  
TFBGA-84 chipsize packages  
•
Programmable CAS Latencies (3, 4, 5 and 6), Burst  
Length (8 & 4) and Burst Type  
•
•
•
Auto Refresh (CBR) and Self Refresh  
All inputs and outputs SSTL_18 compatible  
Off-Chip Driver Impedance Adjustment (OCD) and  
On-Die Termination (ODT)  
Serial Presence Detect with E2PROM  
SO-DIMM Dimensions (nominal) :  
30 mm high, 133.35 mm wide  
•
•
•
•
•
•
Standard DDR2 Synchronous DRAMs (DDR2  
SDRAM) with a single + 1.8 V (± 0.1 V) power  
supply  
All speed grades faster than DDR2-400 comply with  
DDR2-400 timing specifications  
•
•
Based on standard reference layouts Raw Card “A”,  
“C“ and “F”  
RoHS compliant products1)  
Table 1  
Performance for DDR2-800  
Product Type Speed Code  
Speed Grade  
–2.5  
Unit  
—
PC2–6400 6–6–6  
max. Clock Frequency  
@CL6  
@CL5  
@CL4  
@CL3  
fCK6  
fCK5  
fCK4  
fCK3  
tRCD  
tRP  
400  
333  
333  
200  
15  
MHz  
MHz  
MHz  
ns  
min. RAS-CAS-Delay  
min. Row Precharge Time  
min. Row Active Time  
min. Row Cycle Time  
15  
ns  
tRAS  
tRC  
45  
ns  
60  
ns  
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic  
equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January  
2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and  
polybrominated biphenyl ethers.  
Data Sheet  
2
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
Overview  
Table 2  
Performance for DDR2-533 and DDR2-400  
Product Type Speed Code  
Speed Grade  
–3.7  
–5  
Units  
—
PC2–4200 4–4–4  
PC2–3200 3–3–3  
Max. Clock Frequency  
@CL5  
@CL4  
@CL3  
fCK5 266  
200  
200  
200  
15  
MHz  
MHz  
MHz  
ns  
fCK4 266  
fCK3 200  
tRCD 15  
Min. RAS-CAS-Delay  
Min. Row Precharge Time  
Min. Row Active Time  
Min. Row Cycle Time  
tRP  
tRAS 45  
tRC 60  
15  
15  
ns  
40  
ns  
55  
ns  
1.2  
Description  
The INFINEON HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A module family are Small Outline modules “SO-DIMMs”  
with 30.0-mm height based on DDR2 technology. DIMMs are available as non-ECC modules in 16M × 64  
(128 MB), 32M × 64 (256 MB) and 64Mx64 (512 MB) organization and density, intended for mounting into 200-pin  
connector sockets.  
The memory array is designed with 256-Mbit Double-Data-Rate-Two (DDR2) Synchronous DRAMs. Decoupling  
capacitors are mounted on the PCB. The DIMMs feature serial presence detect based on a serial E2PROM device  
using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and are write protected;  
the second 128 bytes are available to the customer.  
Table 3  
Ordering Information for RoHS Compliant Products  
Product Type1)  
Compliance Code2)  
Description  
SDRAM Technology  
PC2-6400  
HYS64T16000HDL–2.5–A 128MB 1Rx16 PC2–6400S–666–12–C0 1 Rank, Non-ECC 256 Mbit (×16)  
HYS64T32020HDL–2.5–A 256MB 2Rx16 PC2–6400S–666–12–A0 2 Ranks, Non-ECC 256 Mbit (×16)  
HYS64T64021HDL–2.5–A 512MB 2Rξ8 PC2–6400S–666–12–F0 2 Ranks, Non-ECC 256 Mbit (×8)  
PC2-4200  
HYS64T16000HDL–3.7–A 128MB 1Rx16 PC2–4200S–444–11–C0 1 Rank, Non-ECC 256 Mbit (×16)  
PC2-3200  
HYS64T16000HDL–5–A  
128MB 1Rx16 PC2–3200S–333–11–C0 1 Rank, Non-ECC 256 Mbit (×16)  
1) All product types end with a place code, designating the silicon die revision. Example: HYS64T16000HDL–5–A, indicating  
Rev. “A” dies are used for DDR2 SDRAM components. For all INFINEON DDR2 module and component nomenclature see  
Chapter 6 of this data sheet.  
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200S–444–  
11–C0”, where 4200S means SO-DIMM with 4.26 GB/sec Module Bandwidth and “444-11” means Column Address  
Strobe (CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest  
JEDEC SPD Revision 1.1 and produced on the Raw Card “C”.  
Data Sheet  
3
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
Overview  
Table 4  
Address Format  
DIMM  
Density  
Module  
Organization  
Memory  
Ranks  
ECC/  
Non-ECC  
# of  
SDRAMs  
# of row/bank/column Raw  
bits  
Card  
128 MByte  
256 MByte  
512 MByte  
16M × 64  
32M × 64  
64M × 64  
1
2
2
Non-ECC  
Non-ECC  
Non-ECC  
4
13/2/9  
13/2/9  
13/2/9  
C
A
F
8
16  
Table 5  
Components on Modules1)  
Product Type  
DRAM Component2)  
DRAM Density  
256 Mbit  
DRAM Organisation  
16M × 16  
HYS64T16000HDL  
HYS64T32020HDL  
HYS64T64021HDL  
HYB18T256160AF  
HYB18T256160AF  
HYB18T256800AF  
256 Mbit  
16M × 16  
256 Mbit  
32M × 8  
1) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.  
2) Green Product  
Data Sheet  
4
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
Pin Configuration and Block Diagrams  
2
Pin Configuration and Block Diagrams  
2.1  
Pin Configuration  
The pin configuration of the Small Outline DDR2 SDRAM DIMM is listed by function in Table 6 (200 pins). The  
abbreviations used in columns Pin and Buffer Type are explained in Table 7 and Table 8 respectively. The pin  
numbering is depicted in Figure 1  
Table 6  
Pin Configuration of SO-DIMM  
Pin or Ball No.  
Name Pin  
Buffer Function  
Type Type  
Clock Signals  
30  
CK0  
CK1  
CK0  
CK1  
I
I
I
I
SSTL  
SSTL  
SSTL  
SSTL  
Clock Signals 2:0, Complement Clock Signals 2:0  
The system clock inputs. All address and command  
lines are sampled on the cross point of the rising edge  
of CK and the falling edge of CK. A Delay Locked  
Loop (DLL) circuit is driven from the clock inputs and  
output timing for read operations is synchronized to  
the input clock.  
164  
32  
166  
79  
80  
CKE0  
CKE1  
I
I
SSTL  
SSTL  
Clock Enable Rank 1:0  
Activates the DDR2 SDRAM CK signal when HIGH  
and deactivates the CK signal when LOW. By  
deactivating the clocks, CKE LOW initiates the Power  
Down Mode or the Self Refresh Mode.  
Note:2 Ranks module  
Not Connected  
NC  
NC  
—
Note:1-rank module  
Control Signals  
110  
115  
S0  
S1  
I
I
SSTL  
SSTL  
Chip Select Rank 1:0  
Enables the associated DDR2 SDRAM command  
decoder when LOW and disables the command  
decoder when HIGH. When the command decoder is  
disabled, new commands are ignored but previous  
operations continue. Rank 0 is selected by S0; Rank  
1 is selected by S1. Ranks are also called "Physical  
banks".2 Ranks module  
NC  
NC  
I
—
Not Connected  
Note:1-rank module  
108  
RAS  
SSTL  
Row Address Strobe  
When sampled at the cross point of the rising edge of  
CK,and falling edge of CK, RAS, CAS and WE define  
the operation to be executed by the SDRAM.  
113  
109  
CAS  
WE  
I
I
SSTL  
SSTL  
Column Address Strobe  
Write Enable  
Data Sheet  
5
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
Pin Configuration and Block Diagrams  
Table 6  
Pin Configuration of SO-DIMM (cont’d)  
Pin or Ball No.  
Name Pin  
Buffer Function  
Type Type  
Address Signals  
107  
106  
BA0  
BA1  
I
SSTL  
SSTL  
Bank Address Bus 2:0  
Selects which DDR2 SDRAM internal bank of four or  
eight is activated.  
I
85  
BA2  
I
SSTL  
Bank Address Bus 2  
Greater than 512Mb DDR2 SDRAMS  
NC  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
A10  
AP  
A11  
NC  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Less than 1Gb DDR2 SDRAMS  
102  
101  
100  
99  
I
I
I
I
I
I
I
I
I
I
I
I
I
Address Bus 12:0  
During a Bank Activate command cycle, defines the  
row address when sampled at the crosspoint of the  
rising edge of CK and falling edge of CK. During a  
Read or Write command cycle, defines the column  
address when sampled at the cross point of the rising  
edge of CK and falling edge of CK. In addition to the  
column address, AP is used to invoke autoprecharge  
operation at the end of the burst read or write cycle. If  
AP is HIGH, autoprecharge is selected and BA0-BAn  
defines the bank to be precharged. If AP is LOW,  
autoprecharge is disabled. During a Precharge  
command cycle, AP is used in conjunction with BA0-  
BAn to control which bank(s) to precharge. If AP is  
HIGH, all banks will be precharged regardless of the  
state of BA0-BAn inputs. If AP is LOW, then BA0-BAn  
are used to define which bank to precharge.  
98  
97  
94  
92  
93  
91  
105  
90  
89  
A12  
A13  
NC  
I
SSTL  
SSTL  
—
Address Signal 12  
Note:Module based on 256 Mbit or larger dies  
Address Signal 13  
116  
I
Note:1 Gbit based module  
NC  
Not Connected  
Note:Module based on 512 Mbit or smaller dies  
Data Signals  
5
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
DQ8  
DQ9  
DQ10  
DQ11  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Data Bus 63:0  
7
Note:Data Input/Output pins  
17  
19  
4
6
14  
16  
23  
25  
35  
37  
Data Sheet  
6
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
Pin Configuration and Block Diagrams  
Table 6  
Pin Configuration of SO-DIMM (cont’d)  
Pin or Ball No.  
Name Pin  
Type Type  
I/O SSTL  
I/O SSTL  
Buffer Function  
20  
DQ12  
DQ13  
DQ14  
DQ15  
DQ16  
DQ17  
DQ18  
DQ19  
DQ20  
DQ21  
DQ22  
DQ23  
DQ24  
DQ25  
DQ26  
DQ27  
DQ28  
DQ29  
DQ30  
DQ31  
DQ32  
DQ33  
DQ34  
DQ35  
DQ36  
DQ37  
DQ38  
DQ39  
DQ40  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
DQ46  
DQ47  
DQ48  
DQ49  
DQ50  
DQ51  
Data Bus 63:0  
Data Input/Output pins  
22  
36  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
38  
43  
45  
55  
57  
44  
46  
56  
58  
61  
63  
73  
75  
62  
64  
74  
76  
123  
125  
135  
137  
124  
126  
134  
136  
141  
143  
151  
153  
140  
142  
152  
154  
157  
159  
173  
175  
Data Sheet  
7
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
Pin Configuration and Block Diagrams  
Table 6  
Pin Configuration of SO-DIMM (cont’d)  
Pin or Ball No.  
Name Pin  
Type Type  
I/O SSTL  
I/O SSTL  
Buffer Function  
158  
DQ52  
DQ53  
DQ54  
DQ55  
DQ56  
DQ57  
DQ58  
DQ59  
DQ60  
DQ61  
DQ62  
DQ63  
Data Bus 63:0  
160  
174  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
176  
179  
181  
189  
191  
180  
182  
192  
194  
Data Strobe Signals  
13  
DQS0 I/O  
DQS0 I/O  
DQS1 I/O  
DQS1 I/O  
DQS2 I/O  
DQS2 I/O  
DQS3 I/O  
DQS3 I/O  
DQS4 I/O  
DQS4 I/O  
DQS5 I/O  
DQS5 I/O  
DQS6 I/O  
DQS6 I/O  
DQS7 I/O  
DQS7 I/O  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Data Strobe Bus 7:0  
The data strobes, associated with one data byte,  
sourced with data transfers. In Write mode, the data  
strobe is sourced by the controller and is centered in  
the data window. In Read mode the data strobe is  
sourced by the DDR2 SDRAM and is sent at the  
leading edge of the data window. DQS signals are  
complements, and timing is relative to the crosspoint  
of respective DQS and DQS. If the module is to be  
operated in single ended strobe mode, all DQS  
signals must be tied on the system board to VSS and  
DDR2 SDRAM mode registers programmed  
appropriately.  
11  
31  
29  
51  
49  
70  
68  
131  
129  
148  
146  
169  
167  
188  
186  
Data Mask Signals  
10  
DM0  
DM1  
DM2  
DM3  
DM4  
DM5  
DM6  
DM7  
I
I
I
I
I
I
I
I
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Data Mask Bus 7:0  
The data write masks, associated with one data byte.  
In Write mode, DM operates as a byte mask by  
allowing input data to be written if it is LOW but blocks  
the write operation if it is HIGH. In Read mode, DM  
lines have no effect.  
26  
52  
67  
130  
147  
170  
185  
EEPROM  
Data Sheet  
8
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
Pin Configuration and Block Diagrams  
Table 6  
Pin Configuration of SO-DIMM (cont’d)  
Pin or Ball No.  
Name Pin  
Buffer Function  
Type Type  
197  
SCL  
SDA  
I
CMOS Serial Bus Clock  
This signal is used to clock data into and out of the  
SPD EEPROM.  
195  
I/O  
OD  
Serial Bus Data  
This is a bidirectional pin used to transfer data into or  
out of the SPD EEPROM. A resistor must be  
connected from SDA to VDDSPD on the motherboard to  
act as a pull-up.  
198  
200  
SA0  
SA1  
I
I
CMOS Serial Address Select Bus 2:0  
Address pins used to select the Serial Presence  
Detect base address.  
CMOS  
Power Supplies  
1
VREF  
AI  
—
—
I/O Reference Voltage  
Reference voltage for the SSTL-18 inputs.  
199  
VDDSPD PWR  
EEPROM Power Supply  
Power supplies for core, I/O, Serial Presence Detect,  
and ground for the module.  
81,82,87,88,95,96,103,104,  
111,112,117,118  
VDD  
PWR  
GND  
—
—
Power Supply  
Power supplies for core, I/O, Serial Presence Detect,  
and ground for the module.  
2,3,8,9,12,15,18,21,24,27,28, VSS  
33,34,39,40,41,42,47,48,53,  
54,59,60,65,66,71,72,77,78,  
121,122,127,128,132,133,138,  
139,144,145,149,150,155,156,  
, 161,162,165,171,172,177,  
178,183,184,187,190,193,196  
Ground Plane  
Power supplies for core, I/O, Serial Presence Detect,  
and ground for the module.  
Other Pins  
114  
119  
ODT0  
I
I
SSTL  
SSTL  
On-Die Termination Control 1:0  
ODT1  
On-Die Termination Control 1  
Asserts on-die termination for DQ, DM, DQS, and  
DQS signals if enabled via the DDR2 SDRAM mode  
register.  
Note:2 Rank modules  
Not Connected  
NC  
NC  
NC  
NC  
—
—
Note:1 Rank modules  
50,69,83,84,120,163,168  
Not connected  
Pins not connected on Infineon SO-DIMMs  
Table 7  
Abbreviations for Pin Type  
Abbreviation  
Description  
I
Standard input-only pin. Digital levels.  
Output. Digital levels.  
O
I/O  
I/O is a bidirectional input/output signal.  
Data Sheet  
9
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
Pin Configuration and Block Diagrams  
Table 7  
Abbreviations for Pin Type (cont’d)  
Abbreviation  
Description  
Input. Analog levels.  
Power  
AI  
PWR  
GND  
NC  
Ground  
Not Connected  
Table 8  
Abbreviation  
SSTL  
Abbreviations for Buffer Type  
Description  
Serial Stub Terminated Logic (SSTL_18)  
Low Voltage CMOS  
LV-CMOS  
CMOS  
CMOS Levels  
OD  
Open Drain. The corresponding pin has 2 operational states, active low and  
tristate, and allows multiple devices to share as a wire-OR.  
Data Sheet  
10  
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
Pin Configuration and Block Diagrams  
62%& ꢇ 0IN ꢀꢀꢁ  
$1ꢀ ꢇ 0IN ꢀꢀꢈ  
633 ꢇ 0IN ꢀꢀꢊ  
0IN ꢀꢀꢃ ꢇ  
0IN ꢀꢀꢄ ꢇ  
0IN ꢀꢁꢀ ꢇ  
0IN ꢀꢁꢂ ꢇ  
0IN ꢀꢁꢅ ꢇ  
0IN ꢀꢃꢃ ꢇ  
0IN ꢀꢃꢄ ꢇ  
0IN ꢀꢆꢀ ꢇ  
0IN ꢀꢆꢂ ꢇ  
0IN ꢀꢆꢅ ꢇ  
633  
633 ꢇ 0IN ꢀꢀꢆ  
$1ꢁ ꢇ 0IN ꢀꢀꢉ  
$13ꢀ ꢇ 0IN ꢀꢁꢁ  
633 ꢇ 0IN ꢀꢁꢈ  
0IN ꢀꢀꢂ ꢇ  
$1ꢂ  
$1ꢈ  
$-ꢀ  
$1ꢄ  
633  
0IN ꢀꢀꢅ ꢇ 633  
0IN ꢀꢁꢃ ꢇ 633  
0IN ꢀꢁꢄ ꢇ $1ꢉ  
0IN ꢀꢃꢀ ꢇ $1ꢁꢃ  
0IN ꢀꢃꢂ ꢇ 633  
0IN ꢀꢃꢅ ꢇ 633  
0IN ꢀꢆꢃ ꢇ #+ꢀ  
0IN ꢀꢆꢄ ꢇ $1ꢁꢂ  
0IN ꢀꢂꢀ ꢇ 633  
$13ꢀ ꢇ 0IN ꢀꢁꢆ  
$1ꢃ ꢇ 0IN ꢀꢁꢉ  
633 ꢇ 0IN ꢀꢃꢁ  
$1ꢆ ꢇ 0IN ꢀꢁꢊ  
$1ꢅ ꢇ 0IN ꢀꢃꢆ  
633 ꢇ 0IN ꢀꢃꢉ  
$1ꢁꢆ  
$-ꢁ  
#+ꢀ  
633  
$1ꢊ ꢇ 0IN ꢀꢃꢈ  
$13ꢁ ꢇ 0IN ꢀꢃꢊ  
633 ꢇ 0IN ꢀꢆꢆ  
$13ꢁ ꢇ 0IN ꢀꢆꢁ  
$1ꢁꢀ ꢇ 0IN ꢀꢆꢈ  
633 ꢇ 0IN ꢀꢆꢊ  
$1ꢁꢁ ꢇ 0IN ꢀꢆꢉ  
$1ꢁꢈ  
633 ꢇ 0IN ꢀꢂꢁ  
$1ꢁꢉ ꢇ 0IN ꢀꢂꢈ  
$13ꢃ ꢇ 0IN ꢀꢂꢊ  
633 ꢇ 0IN ꢀꢈꢆ  
0IN ꢀꢂꢃ ꢇ 633  
0IN ꢀꢂꢄ ꢇ $1ꢃꢁ  
0IN ꢀꢈꢀ ꢇ .#  
$1ꢁꢄ ꢇ 0IN ꢀꢂꢆ  
633 ꢇ 0IN ꢀꢂꢉ  
$13ꢃ ꢇ 0IN ꢀꢈꢁ  
$1ꢁꢅ ꢇ 0IN ꢀꢈꢈ  
633 ꢇ 0IN ꢀꢈꢊ  
$1ꢃꢈ ꢇ 0IN ꢀꢄꢆ  
$-ꢆ ꢇ 0IN ꢀꢄꢉ  
633 ꢇ 0IN ꢀꢉꢁ  
$1ꢃꢉ ꢇ 0IN ꢀꢉꢈ  
#+%ꢀ ꢇ 0IN ꢀꢉꢊ  
.# ꢇ 0IN ꢀꢅꢆ  
0IN ꢀꢂꢂ ꢇ $1ꢃꢀ  
0IN ꢀꢂꢅ ꢇ 633  
0IN ꢀꢈꢃ ꢇ $-ꢃ  
0IN ꢀꢈꢄ ꢇ $1ꢃꢃ  
0IN ꢀꢄꢀ ꢇ 633  
0IN ꢀꢈꢂ ꢇ 633  
0IN ꢀꢈꢅ ꢇ $1ꢃꢆ  
0IN ꢀꢄꢃ ꢇ $1ꢃꢅ  
0IN ꢀꢄꢄ ꢇ 633  
0IN ꢀꢉꢀ ꢇ $13ꢆ  
0IN ꢀꢉꢂ ꢇ $1ꢆꢀ  
0IN ꢀꢉꢅ ꢇ 633  
$1ꢁꢊ ꢇ 0IN ꢀꢈꢉ  
$1ꢃꢂ ꢇ 0IN ꢀꢄꢁ  
633 ꢇ 0IN ꢀꢄꢈ  
0IN ꢀꢄꢂ ꢇ $1ꢃꢊ  
0IN ꢀꢄꢅ ꢇ $13ꢆ  
0IN ꢀꢉꢃ ꢇ 633  
.# ꢇ 0IN ꢀꢄꢊ  
$1ꢃꢄ ꢇ 0IN ꢀꢉꢆ  
633 ꢇ 0IN ꢀꢉꢉ  
0IN ꢀꢉꢄ ꢇ $1ꢆꢁ  
0IN ꢀꢅꢀ ꢇ .#ꢋ#+%ꢁ  
0IN ꢀꢅꢂ ꢇ .#  
0IN ꢀꢅꢅ ꢇ 6$$  
0IN ꢀꢊꢃ ꢇ !ꢉ  
6$$ ꢇ 0IN ꢀꢅꢁ  
.#ꢋ"!ꢃ ꢇ 0IN ꢀꢅꢈ  
0IN ꢀꢅꢃ ꢇ 6$$  
0IN ꢀꢅꢄ ꢇ .#ꢋ!ꢁꢂ  
6$$ ꢇ 0IN ꢀꢅꢉ  
!ꢊ ꢇ 0IN ꢀꢊꢁ  
!ꢁꢃ ꢇ 0IN ꢀꢅꢊ  
!ꢅ ꢇ 0IN ꢀꢊꢆ  
0IN ꢀꢊꢀ ꢇ !ꢁꢁ  
0IN ꢀꢊꢂ ꢇ !ꢄ  
6$$ ꢇ 0IN ꢀꢊꢈ  
!ꢆ ꢇ 0IN ꢀꢊꢊ  
0IN ꢀꢊꢄ ꢇ 6$$  
0IN ꢁꢀꢀ ꢇ !ꢃ  
!ꢈ ꢇ 0IN ꢀꢊꢉ  
!ꢁ ꢇ 0IN ꢁꢀꢁ  
0IN ꢀꢊꢅ ꢇ !ꢂ  
0IN ꢁꢀꢃ ꢇ !ꢀ  
6$$ ꢇ 0IN ꢁꢀꢆ  
"!ꢀ ꢇ 0IN ꢁꢀꢉ  
6$$ ꢇ 0IN ꢁꢁꢁ  
0IN ꢁꢀꢂ ꢇ 6$$  
0IN ꢁꢀꢅ ꢇ 2!3  
0IN ꢁꢁꢃ ꢇ 6$$  
0IN ꢁꢁꢄ ꢇ .#ꢋ!ꢁꢆ  
0IN ꢁꢃꢀ ꢇ .#  
!ꢁꢀꢋ!0 ꢇ 0IN ꢁꢀꢈ  
7% ꢇ 0IN ꢁꢀꢊ  
#!3 ꢇ 0IN ꢁꢁꢆ  
6$$ ꢇ 0IN ꢁꢁꢉ  
633 ꢇ 0IN ꢁꢃꢁ  
0IN ꢁꢀꢄ ꢇ "!ꢁ  
0IN ꢁꢁꢀ ꢇ 3ꢀ  
0IN ꢁꢁꢂ ꢇ /$4ꢀ  
0IN ꢁꢁꢅ ꢇ 6$$  
0IN ꢁꢃꢃ ꢇ 633  
0IN ꢁꢃꢄ ꢇ $1ꢆꢉ  
0IN ꢁꢆꢀ ꢇ $-ꢂ  
0IN ꢁꢆꢂ ꢇ $1ꢆꢅ  
0IN ꢁꢆꢅ ꢇ 633  
0IN ꢁꢂꢃ ꢇ $1ꢂꢈ  
0IN ꢁꢂꢄ ꢇ $13ꢈ  
0IN ꢁꢈꢀ ꢇ 633  
0IN ꢁꢈꢂ ꢇ $1ꢂꢉ  
0IN ꢁꢈꢅ ꢇ $1ꢈꢃ  
0IN ꢁꢄꢃ ꢇ 633  
0IN ꢁꢄꢄ ꢇ #+ꢁ  
0IN ꢁꢉꢀ ꢇ $-ꢄ  
0IN ꢁꢉꢂ ꢇ $1ꢈꢂ  
.#ꢋ3ꢁ ꢇ 0IN ꢁꢁꢈ  
.#ꢋ/$4ꢁ ꢇ 0IN ꢁꢁꢊ  
$1ꢆꢃ ꢇ 0IN ꢁꢃꢆ  
633 ꢇ 0IN ꢁꢃꢉ  
0IN ꢁꢃꢂ ꢇ $1ꢆꢄ  
0IN ꢁꢃꢅ ꢇ 633  
0IN ꢁꢆꢃ ꢇ 633  
0IN ꢁꢆꢄ ꢇ $1ꢆꢊ  
0IN ꢁꢂꢀ ꢇ $1ꢂꢂ  
0IN ꢁꢂꢂ ꢇ 633  
0IN ꢁꢂꢅ ꢇ $13ꢈ  
0IN ꢁꢈꢃ ꢇ $1ꢂꢄ  
0IN ꢁꢈꢄ ꢇ 633  
0IN ꢁꢄꢀ ꢇ $1ꢈꢆ  
0IN ꢁꢄꢂ ꢇ #+ꢁ  
0IN ꢁꢄꢅ ꢇ 633  
0IN ꢁꢉꢃ ꢇ 633  
0IN ꢁꢉꢄ ꢇ $1ꢈꢈ  
$1ꢆꢆ ꢇ 0IN ꢁꢃꢈ  
$13ꢂ ꢇ 0IN ꢁꢃꢊ  
633 ꢇ 0IN ꢁꢆꢆ  
$13ꢂ ꢇ 0IN ꢁꢆꢁ  
$1ꢆꢂ ꢇ 0IN ꢁꢆꢈ  
633 ꢇ 0IN ꢁꢆꢊ  
$1ꢆꢈ ꢇ 0IN ꢁꢆꢉ  
$1ꢂꢀ ꢇ 0IN ꢁꢂꢁ  
633 ꢇ 0IN ꢁꢂꢈ  
$1ꢂꢁ ꢇ 0IN ꢁꢂꢆ  
$-ꢈ ꢇ 0IN ꢁꢂꢉ  
$1ꢂꢃ ꢇ 0IN ꢁꢈꢁ  
633 ꢇ 0IN ꢁꢈꢈ  
633 ꢇ 0IN ꢁꢂꢊ  
$1ꢂꢆ ꢇ 0IN ꢁꢈꢆ  
$1ꢂꢅ ꢇ 0IN ꢁꢈꢉ  
633 ꢇ 0IN ꢁꢄꢁ  
$1ꢂꢊ ꢇ 0IN ꢁꢈꢊ  
.# ꢇ 0IN ꢁꢄꢆ  
633 ꢇ 0IN ꢁꢄꢈ  
$13ꢄ ꢇ 0IN ꢁꢄꢉ  
633 ꢇ 0IN ꢁꢉꢁ  
$13ꢄ ꢇ 0IN ꢁꢄꢊ  
$1ꢈꢀ ꢇ 0IN ꢁꢉꢆ  
$1ꢈꢁ ꢇ 0IN ꢁꢉꢈ  
633 ꢇ 0IN ꢁꢉꢉ  
$1ꢈꢉ ꢇ 0IN ꢁꢅꢁ  
0IN ꢁꢉꢅ ꢇ 633  
0IN ꢁꢅꢃ ꢇ $1ꢄꢁ  
$1ꢈꢄ ꢇ 0IN ꢁꢉꢊ  
633 ꢇ 0IN ꢁꢅꢆ  
0IN ꢁꢅꢀ ꢇ $1ꢄꢀ  
0IN ꢁꢅꢂ ꢇ 633  
$-ꢉ ꢇ 0IN ꢁꢅꢈ  
$1ꢈꢅ ꢇ 0IN ꢁꢅꢊ  
633 ꢇ 0IN ꢁꢊꢆ  
0IN ꢁꢅꢄ ꢇ $13ꢉ  
0IN ꢁꢊꢀ ꢇ 633  
633 ꢇ 0IN ꢁꢅꢉ  
$1ꢈꢊ ꢇ 0IN ꢁꢊꢁ  
3$! ꢇ 0IN ꢁꢊꢈ  
0IN ꢁꢅꢅ ꢇ $13ꢉ  
0IN ꢁꢊꢃ ꢇ $1ꢄꢃ  
0IN ꢁꢊꢄ ꢇ 633  
0IN ꢁꢊꢂ ꢇ $1ꢄꢆ  
0IN ꢁꢊꢅ ꢇ 3!ꢀ  
3#, ꢇ 0IN ꢁꢊꢉ  
6$$ 30$ ꢇ 0IN ꢁꢊꢊ  
0IN ꢃꢀꢀ ꢇ 3!ꢁ  
-004ꢀꢁꢂꢀ  
Figure 1  
Pin Configuration SO-DIMM (200 Pin)  
Data Sheet  
11  
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
Pin Configuration and Block Diagrams  
2.2  
Block Diagrams  
"!ꢀ ꢋ "!ꢁ  
"!ꢀ ꢋ "!ꢁꢌ 3$2!-S $ꢀ ꢋ $ꢇ  
6$$ꢍ30$  
6$$ꢊ6$$1  
6$$ꢌ 30$ %%02/- %ꢀ  
6$$ꢊ6$$1ꢌ 3$2!-S $ꢀ ꢋ $ꢇ  
62%&ꢌ 3$2!-S $ꢀ ꢋ $ꢇ  
633ꢌ 3$2!-S $ꢀ ꢋ $ꢇ  
!ꢀ ꢋ !N  
2!3  
#!3  
7%  
!ꢀ ꢋ !Nꢌ 3$2!-S $ꢀ ꢋ $ꢇ  
2!3ꢌ 3$2!-S $ꢀ ꢋ $ꢇ  
#!3ꢌ 3$2!-S $ꢀ ꢋ $ꢇ  
7%ꢌ 3$2!-S $ꢀ ꢋ $ꢇ  
62%&  
633  
#+%ꢀ  
#+%ꢁ  
/$4ꢀ  
/$4ꢁ  
#+ꢀ  
#+ꢀ  
#+ꢁ  
#+ꢁ  
#+%ꢀꢌ 3$2!-S $ꢀ ꢋ $ꢄ  
#+%ꢁꢌ 3$2!-S $ꢅ ꢋ $ꢇ  
/$4ꢀꢌ 3$2!-S $ꢀ ꢋ $ꢄ  
/$4ꢁꢌ 3$2!-S $ꢅ ꢋ $ꢇ  
%ꢀ  
3#,  
3$!  
!ꢀ  
3#,  
3$!  
3!ꢀ  
3!ꢁ  
!ꢁ  
ꢅ LOADS  
ꢅ LOADS  
!ꢃ  
70  
6SS  
3ꢀ  
3ꢁ  
$ꢃ  
$ꢀ  
$ꢅ  
$ꢂ  
$-ꢀ  
$13ꢀ  
$13ꢀ  
$1ꢀ  
,$- #3  
,$13  
,$13  
)ꢊ/ ꢀ  
,$- #3  
,$13  
,$13  
)ꢊ/ ꢀ  
$-ꢅ  
$13ꢅ  
$13ꢅ  
$1ꢄꢃ  
$1ꢄꢄ  
$1ꢄꢅ  
$1ꢄꢆ  
$1ꢄꢂ  
$1ꢄꢇ  
$1ꢄꢈ  
$1ꢄꢉ  
$-ꢆ  
$13ꢆ  
$13ꢆ  
$1ꢅꢀ  
$1ꢅꢁ  
$1ꢅꢃ  
$1ꢅꢄ  
$1ꢅꢅ  
$1ꢅꢆ  
$1ꢅꢂ  
$1ꢅꢇ  
,$- #3  
,$- #3  
,$13  
,$13  
)ꢊ/ ꢀ  
,$13  
,$13  
)ꢊ/ ꢀ  
)ꢊ/ ꢁ  
)ꢊ/ ꢃ  
)ꢊ/ ꢄ  
)ꢊ/ ꢅ  
)ꢊ/ ꢆ  
)ꢊ/ ꢂ  
)ꢊ/ ꢇ  
5$-  
5$13  
5$13  
)ꢊ/ꢈ  
$1ꢁ  
)ꢊ/ ꢁ  
)ꢊ/ ꢁ  
)ꢊ/ ꢁ  
$1ꢃ  
)ꢊ/ ꢃ  
)ꢊ/ ꢃ  
)ꢊ/ ꢃ  
$1ꢄ  
)ꢊ/ ꢄ  
)ꢊ/ ꢄ  
)ꢊ/ ꢄ  
$1ꢅ  
)ꢊ/ ꢅ  
)ꢊ/ ꢅ  
)ꢊ/ ꢅ  
$1ꢆ  
)ꢊ/ ꢆ  
)ꢊ/ ꢆ  
)ꢊ/ ꢆ  
$1ꢂ  
)ꢊ/ ꢂ  
)ꢊ/ ꢂ  
)ꢊ/ ꢂ  
$1ꢇ  
)ꢊ/ ꢇ  
)ꢊ/ ꢇ  
)ꢊ/ ꢇ  
$-ꢁ  
5$-  
5$13  
5$13  
)ꢊ/ꢈ  
5$-  
5$13  
5$13  
)ꢊ/ꢈ  
5$-  
5$13  
5$13  
)ꢊ/ꢈ  
$13ꢁ  
$13ꢁ  
$1ꢈ  
$1ꢉ  
)ꢊ/ꢉ  
)ꢊ/ꢉ  
)ꢊ/ꢉ  
)ꢊ/ꢉ  
$1ꢁꢀ  
$1ꢁꢁ  
$1ꢁꢃ  
$1ꢁꢄ  
$1ꢁꢅ  
$1ꢁꢆ  
)ꢊ/ꢁꢀ  
)ꢊ/ꢁꢁ  
)ꢊ/ꢁꢃ  
)ꢊ/ꢁꢄ  
)ꢊ/ꢁꢅ  
)ꢊ/ꢁꢆ  
)ꢊ/ꢁꢀ  
)ꢊ/ꢁꢁ  
)ꢊ/ꢁꢃ  
)ꢊ/ꢁꢄ  
)ꢊ/ꢁꢅ  
)ꢊ/ꢁꢆ  
)ꢊ/ꢁꢀ  
)ꢊ/ꢁꢁ  
)ꢊ/ꢁꢃ  
)ꢊ/ꢁꢄ  
)ꢊ/ꢁꢅ  
)ꢊ/ꢁꢆ  
)ꢊ/ꢁꢀ  
)ꢊ/ꢁꢁ  
)ꢊ/ꢁꢃ  
)ꢊ/ꢁꢄ  
)ꢊ/ꢁꢅ  
)ꢊ/ꢁꢆ  
$ꢁ  
$ꢆ  
$ꢄ  
$ꢇ  
$-ꢃ  
$13ꢃ  
$13ꢃ  
$1ꢁꢂ  
$1ꢁꢇ  
$1ꢁꢈ  
$1ꢁꢉ  
$1ꢃꢀ  
$1ꢃꢁ  
$1ꢃꢃ  
$1ꢃꢄ  
$-ꢄ  
$13ꢄ  
$13ꢄ  
$1ꢃꢅ  
$1ꢃꢆ  
$1ꢃꢂ  
$1ꢃꢇ  
$1ꢃꢈ  
$1ꢃꢉ  
$1ꢄꢀ  
$1ꢄꢁ  
,$- #3  
,$13  
,$13  
)ꢊ/ ꢀ  
,$- #3  
,$13  
,$13  
)ꢊ/ ꢀ  
$-ꢂ  
$13ꢂ  
$13ꢂ  
$1ꢅꢈ  
$1ꢅꢉ  
$1ꢆꢀ  
$1ꢆꢁ  
$1ꢆꢃ  
$1ꢆꢄ  
$1ꢆꢅ  
$1ꢆꢆ  
$-ꢇ  
$13ꢇ  
$13ꢇ  
$1ꢆꢂ  
$1ꢆꢇ  
$1ꢆꢈ  
$1ꢆꢉ  
$1ꢂꢀ  
$1ꢂꢁ  
$1ꢂꢃ  
$1ꢂꢄ  
,$- #3  
,$13  
,$13  
)ꢊ/ ꢀ  
,$- #3  
,$13  
,$13  
)ꢊ/ ꢀ  
)ꢊ/ ꢁ  
)ꢊ/ ꢁ  
)ꢊ/ ꢁ  
)ꢊ/ ꢁ  
)ꢊ/ ꢃ  
)ꢊ/ ꢃ  
)ꢊ/ ꢃ  
)ꢊ/ ꢃ  
)ꢊ/ ꢄ  
)ꢊ/ ꢄ  
)ꢊ/ ꢄ  
)ꢊ/ ꢄ  
)ꢊ/ ꢅ  
)ꢊ/ ꢅ  
)ꢊ/ ꢅ  
)ꢊ/ ꢅ  
)ꢊ/ ꢆ  
)ꢊ/ ꢆ  
)ꢊ/ ꢆ  
)ꢊ/ ꢆ  
)ꢊ/ ꢂ  
)ꢊ/ ꢂ  
)ꢊ/ ꢂ  
)ꢊ/ ꢂ  
)ꢊ/ ꢇ  
)ꢊ/ ꢇ  
)ꢊ/ ꢇ  
)ꢊ/ ꢇ  
5$-  
5$13  
5$13  
)ꢊ/ꢈ  
5$-  
5$13  
5$13  
)ꢊ/ꢈ  
5$-  
5$13  
5$13  
)ꢊ/ꢈ  
5$-  
5$13  
5$13  
)ꢊ/ꢈ  
)ꢊ/ꢉ  
)ꢊ/ꢉ  
)ꢊ/ꢉ  
)ꢊ/ꢉ  
)ꢊ/ꢁꢀ  
)ꢊ/ꢁꢁ  
)ꢊ/ꢁꢃ  
)ꢊ/ꢁꢄ  
)ꢊ/ꢁꢅ  
)ꢊ/ꢁꢆ  
)ꢊ/ꢁꢀ  
)ꢊ/ꢁꢁ  
)ꢊ/ꢁꢃ  
)ꢊ/ꢁꢄ  
)ꢊ/ꢁꢅ  
)ꢊ/ꢁꢆ  
)ꢊ/ꢁꢀ  
)ꢊ/ꢁꢁ  
)ꢊ/ꢁꢃ  
)ꢊ/ꢁꢄ  
)ꢊ/ꢁꢅ  
)ꢊ/ꢁꢆ  
)ꢊ/ꢁꢀ  
)ꢊ/ꢁꢁ  
)ꢊ/ꢁꢃ  
)ꢊ/ꢁꢄ  
)ꢊ/ꢁꢅ  
)ꢊ/ꢁꢆ  
-0"4ꢀꢁꢂꢀ  
Figure 2  
Block Diagram Raw Card A SO-DIMM (×64, 2 Ranks, ×16)  
Notes  
2. S0, S1, BAn, An, RAS, CAS, WE, ODTO, ODT1,  
CKEO, CKE1 resistors are 3 Ω ±5 %  
1. DQ, DQS, DM resistors are 22 Ω ±5 %  
Data Sheet  
12  
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
Pin Configuration and Block Diagrams  
"!ꢀ ꢋ "!ꢂꢌ 3$2!-S $ꢀ ꢋ $ꢈ  
!ꢀ ꢋ !Nꢌ 3$2!-S $ꢀ ꢋ $ꢈ  
2!3ꢌ 3$2!-S $ꢀ ꢋ $ꢈ  
#!3ꢌ 3$2!-S $ꢀ ꢋ $ꢈ  
7%ꢌ 3$2!-S $ꢀ ꢋ $ꢈ  
#+%ꢌ 3$2!-S $ꢀ ꢋ $ꢄ  
/$4ꢌ 3$2!-S $ꢀ ꢋ $ꢄ  
"!ꢀ ꢋ "!ꢂ  
!ꢀ ꢋ !N  
2!3  
6$$ꢍ30$  
6$$ꢊ6$$1  
6$$ꢌ 30$ %%02/- %ꢀ  
6$$ꢊ6$$1ꢌ 3$2!-S $ꢀ ꢋ $ꢈ  
62%&ꢌ 3$2!-S $ꢀ ꢋ $ꢈ  
633ꢌ 3$2!-S $ꢀ ꢋ $ꢈ  
62%&  
633  
#!3  
7%  
#+%ꢀ  
/$4ꢀ  
3ꢀ  
$ꢃ  
$ꢀ  
#+ꢀ  
#+ꢀ  
#+ꢂ  
#+ꢂ  
$-ꢀ  
$13ꢀ  
$13ꢀ  
$1ꢀ  
,$- #3  
,$13  
,$13  
)ꢊ/ ꢀ  
$-ꢅ  
$13ꢅ  
$13ꢅ  
$1ꢄꢃ  
$1ꢄꢄ  
$1ꢄꢅ  
$1ꢄꢆ  
$1ꢄꢇ  
$1ꢄꢈ  
$1ꢄꢉ  
$1ꢄꢁ  
$-ꢆ  
$13ꢆ  
$13ꢆ  
$1ꢅꢀ  
$1ꢅꢂ  
$1ꢅꢃ  
$1ꢅꢄ  
$1ꢅꢅ  
$1ꢅꢆ  
$1ꢅꢇ  
$1ꢅꢈ  
,$- #3  
,$13  
,$13  
)ꢊ/ ꢀ  
ꢅ LOADS  
ꢅ LOADS  
$1ꢂ  
)ꢊ/ ꢂ  
)ꢊ/ ꢂ  
%ꢀ  
$1ꢃ  
)ꢊ/ ꢃ  
)ꢊ/ ꢃ  
3#,  
3$!  
3!ꢀ  
3!ꢂ  
3#,  
$1ꢄ  
)ꢊ/ ꢄ  
)ꢊ/ ꢄ  
3$!  
!ꢀ  
$1ꢅ  
)ꢊ/ ꢅ  
)ꢊ/ ꢅ  
$1ꢆ  
)ꢊ/ ꢆ  
)ꢊ/ ꢆ  
!ꢂ  
$1ꢇ  
)ꢊ/ ꢇ  
)ꢊ/ ꢇ  
!ꢃ  
$1ꢈ  
)ꢊ/ ꢈ  
)ꢊ/ ꢈ  
70  
$-ꢂ  
5$-  
5$13  
5$13  
)ꢊ/ꢉ  
5$-  
5$13  
5$13  
)ꢊ/ꢉ  
$13ꢂ  
$13ꢂ  
$1ꢉ  
6SS  
$1ꢁ  
)ꢊ/ꢁ  
)ꢊ/ꢁ  
$1ꢂꢀ  
$1ꢂꢂ  
$1ꢂꢃ  
$1ꢂꢄ  
$1ꢂꢅ  
$1ꢂꢆ  
)ꢊ/ꢂꢀ  
)ꢊ/ꢂꢂ  
)ꢊ/ꢂꢃ  
)ꢊ/ꢂꢄ  
)ꢊ/ꢂꢅ  
)ꢊ/ꢂꢆ  
)ꢊ/ꢂꢀ  
)ꢊ/ꢂꢂ  
)ꢊ/ꢂꢃ  
)ꢊ/ꢂꢄ  
)ꢊ/ꢂꢅ  
)ꢊ/ꢂꢆ  
$ꢂ  
$ꢄ  
$-ꢃ  
$13ꢃ  
$13ꢃ  
$1ꢂꢇ  
$1ꢂꢈ  
$1ꢂꢉ  
$1ꢂꢁ  
$1ꢃꢀ  
$1ꢃꢂ  
$1ꢃꢃ  
$1ꢃꢄ  
$-ꢄ  
$13ꢄ  
$13ꢄ  
$1ꢃꢅ  
$1ꢃꢆ  
$1ꢃꢇ  
$1ꢃꢈ  
$1ꢃꢉ  
$1ꢃꢁ  
$1ꢄꢀ  
$1ꢄꢂ  
,$- #3  
,$13  
,$13  
)ꢊ/ ꢀ  
$-ꢇ  
$13ꢇ  
$13ꢇ  
$1ꢅꢉ  
$1ꢅꢁ  
$1ꢆꢀ  
$1ꢆꢂ  
$1ꢆꢃ  
$1ꢆꢄ  
$1ꢆꢅ  
$1ꢆꢆ  
$-ꢈ  
$13ꢈ  
$13ꢈ  
$1ꢆꢇ  
$1ꢆꢈ  
$1ꢆꢉ  
$1ꢆꢁ  
$1ꢇꢀ  
$1ꢇꢂ  
$1ꢇꢃ  
$1ꢇꢄ  
,$- #3  
,$13  
,$13  
)ꢊ/ ꢀ  
)ꢊ/ ꢂ  
)ꢊ/ ꢂ  
)ꢊ/ ꢃ  
)ꢊ/ ꢃ  
)ꢊ/ ꢄ  
)ꢊ/ ꢄ  
)ꢊ/ ꢅ  
)ꢊ/ ꢅ  
)ꢊ/ ꢆ  
)ꢊ/ ꢆ  
)ꢊ/ ꢇ  
)ꢊ/ ꢇ  
)ꢊ/ ꢈ  
)ꢊ/ ꢈ  
5$-  
5$13  
5$13  
)ꢊ/ꢉ  
5$-  
5$13  
5$13  
)ꢊ/ꢉ  
)ꢊ/ꢁ  
)ꢊ/ꢁ  
)ꢊ/ꢂꢀ  
)ꢊ/ꢂꢂ  
)ꢊ/ꢂꢃ  
)ꢊ/ꢂꢄ  
)ꢊ/ꢂꢅ  
)ꢊ/ꢂꢆ  
)ꢊ/ꢂꢀ  
)ꢊ/ꢂꢂ  
)ꢊ/ꢂꢃ  
)ꢊ/ꢂꢄ  
)ꢊ/ꢂꢅ  
)ꢊ/ꢂꢆ  
-0"4ꢀꢀꢁꢀ  
Figure 3  
Block Diagram Raw Card C SO-DIMM (×64, 1Rank, ×16)  
Notes  
2. S0, S1, BAn, An, RAS, CAS, WE, ODTO, ODT1,  
CKEO, CKE1 resistors are 3 Ω ±5 %  
1. DQ, DQS, DM resistors are 22 Ω ±5 %  
Data Sheet  
13  
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
Pin Configuration and Block Diagrams  
"!ꢀ ꢃ "!ꢄꢆ 3$2!-S $ꢀ ꢃ $ꢅꢇ  
"!ꢀ ꢃ "!ꢄ  
!ꢀ ꢃ !N  
2!3  
!ꢀ ꢃ !Nꢆ 3$2!-S $ꢀ ꢃ $ꢅꢇ  
2!3ꢆ 3$2!-S $ꢀ ꢃ $ꢅꢇ  
6$$ꢈ30$  
6$$ꢍ6$$1  
62%&  
6$$ꢆ 30$ %%02/- %ꢀ  
6$$ꢍ6$$1ꢆ 3$2!-S $ꢀ ꢃ $ꢅꢇ  
62%&ꢆ 3$2!-S $ꢀ ꢃ $ꢅꢇ  
633ꢆ 3$2!-S $ꢀ ꢃ $ꢅꢇ  
#!3ꢆ 3$2!-S $ꢀ ꢃ $ꢅꢇ  
#!3  
7%ꢆ 3$2!-S $ꢀ ꢃ $ꢅꢇ  
7%  
#+% ꢀꢆ 3$2!-S $ꢀ ꢃ $ꢅꢈ $ꢉ ꢃ $ꢇꢈ $ꢅꢀ ꢃ $ꢅꢅꢈ $ꢅꢉ ꢃ $ꢅꢇ  
#+% ꢅꢆ 3$2!-S $ꢄ ꢃ $ꢁꢈ $ꢊ ꢃ $ꢋꢈ $ꢅꢄ ꢃ $ꢅꢁ  
/$4 ꢀꢆ 3$2!-S $ꢀ ꢃ $ꢅꢈ $ꢉ ꢃ $ꢇꢈ $ꢅꢀ ꢃ $ꢅꢅꢈ $ꢅꢉ ꢃ $ꢅꢇ  
/$4 ꢅꢆ 3$2!-S $ꢄ ꢃ $ꢁꢈ $ꢊ ꢃ $ꢋꢈ $ꢅꢄ ꢃ $ꢅꢁ  
#+% ꢀ  
#+% ꢅ  
/$4 ꢀ  
/$4 ꢅ  
633  
3ꢀ  
3ꢅ  
$ꢀ  
$ꢌ  
$ꢋ  
$ꢄ  
$ꢁ  
$ꢉ  
$ꢅꢄ  
$ꢅꢁ  
$ꢊ  
%ꢀ  
$-ꢉ  
$13ꢉ  
$13ꢉ  
$1ꢁꢄ  
$1ꢁꢁ  
$1ꢁꢉ  
$1ꢁꢇ  
$1ꢁꢊ  
$1ꢁꢂ  
$1ꢁꢌ  
$1ꢁꢋ  
$-ꢀ  
$13ꢀ  
$13ꢀ  
$1ꢀ  
$1ꢅ  
$1ꢄ  
$1ꢁ  
$1ꢉ  
$1ꢇ  
$1ꢊ  
$1ꢂ  
$- #3  
$13  
$13  
)ꢍ/ ꢀ  
)ꢍ/ ꢅ  
)ꢍ/ ꢄ  
)ꢍ/ ꢁ  
)ꢍ/ ꢉ  
)ꢍ/ ꢇ  
)ꢍ/ ꢊ  
)ꢍ/ ꢂ  
$- #3  
$13  
$13  
)ꢍ/ ꢀ  
)ꢍ/ ꢅ  
)ꢍ/ ꢄ  
)ꢍ/ ꢁ  
)ꢍ/ ꢉ  
)ꢍ/ ꢇ  
)ꢍ/ ꢊ  
)ꢍ/ ꢂ  
$- #3  
$13  
$13  
)ꢍ/ ꢀ  
)ꢍ/ ꢅ  
)ꢍ/ ꢄ  
)ꢍ/ ꢁ  
)ꢍ/ ꢉ  
)ꢍ/ ꢇ  
)ꢍ/ ꢊ  
)ꢍ/ ꢂ  
$- #3  
$13  
$13  
)ꢍ/ ꢀ  
)ꢍ/ ꢅ  
)ꢍ/ ꢄ  
)ꢍ/ ꢁ  
)ꢍ/ ꢉ  
)ꢍ/ ꢇ  
)ꢍ/ ꢊ  
)ꢍ/ ꢂ  
3#,  
3$!  
!ꢀ  
3#,  
3$!  
3!ꢀ  
3!ꢅ  
3!ꢄ  
633  
!ꢅ  
!ꢄ  
70  
#+ꢀ  
#+ꢀ  
ꢌ LOADS  
ꢌ LOADS  
ꢇꢎꢊ P&  
ꢇꢎꢊ P&  
$ꢅ  
$ꢇ  
#+ꢅ  
#+ꢅ  
$-ꢅ  
$13ꢅ  
$13ꢅ  
$1ꢌ  
$-ꢇ  
$13ꢇ  
$13ꢇ  
$1ꢉꢀ  
$1ꢉꢅ  
$1ꢉꢄ  
$1ꢉꢁ  
$1ꢉꢉ  
$1ꢉꢇ  
$1ꢉꢊ  
$1ꢉꢂ  
$- #3  
$13  
$13  
)ꢍ/ ꢀ  
)ꢍ/ ꢅ  
)ꢍ/ ꢄ  
)ꢍ/ ꢁ  
)ꢍ/ ꢉ  
)ꢍ/ ꢇ  
)ꢍ/ ꢊ  
)ꢍ/ ꢂ  
$- #3  
$13  
$13  
)ꢍ/ ꢀ  
)ꢍ/ ꢅ  
)ꢍ/ ꢄ  
)ꢍ/ ꢁ  
)ꢍ/ ꢉ  
)ꢍ/ ꢇ  
)ꢍ/ ꢊ  
)ꢍ/ ꢂ  
$- #3  
$13  
$13  
)ꢍ/ ꢀ  
)ꢍ/ ꢅ  
)ꢍ/ ꢄ  
)ꢍ/ ꢁ  
)ꢍ/ ꢉ  
)ꢍ/ ꢇ  
)ꢍ/ ꢊ  
)ꢍ/ ꢂ  
$- #3  
$13  
$13  
)ꢍ/ ꢀ  
)ꢍ/ ꢅ  
)ꢍ/ ꢄ  
)ꢍ/ ꢁ  
)ꢍ/ ꢉ  
)ꢍ/ ꢇ  
)ꢍ/ ꢊ  
)ꢍ/ ꢂ  
$1ꢋ  
$1ꢅꢀ  
$1ꢅꢅ  
$1ꢅꢄ  
$1ꢅꢁ  
$1ꢅꢉ  
$1ꢅꢇ  
$ꢅꢀ  
$ꢅꢉ  
$-ꢄ  
$13ꢄ  
$13ꢄ  
$1ꢅꢊ  
$1ꢅꢂ  
$1ꢅꢌ  
$1ꢅꢋ  
$1ꢄꢀ  
$1ꢄꢅ  
$1ꢄꢄ  
$1ꢄꢁ  
$-ꢊ  
$13ꢊ  
$13ꢊ  
$1ꢉꢌ  
$1ꢉꢋ  
$1ꢇꢀ  
$1ꢇꢅ  
$1ꢇꢄ  
$1ꢇꢁ  
$1ꢇꢉ  
$1ꢇꢇ  
$- #3  
$13  
$13  
)ꢍ/ ꢀ  
)ꢍ/ ꢅ  
)ꢍ/ ꢄ  
)ꢍ/ ꢁ  
)ꢍ/ ꢉ  
)ꢍ/ ꢇ  
)ꢍ/ ꢊ  
)ꢍ/ ꢂ  
$- #3  
$13  
$13  
)ꢍ/ ꢀ  
)ꢍ/ ꢅ  
)ꢍ/ ꢄ  
)ꢍ/ ꢁ  
)ꢍ/ ꢉ  
)ꢍ/ ꢇ  
)ꢍ/ ꢊ  
)ꢍ/ ꢂ  
$- #3  
$13  
$13  
)ꢍ/ ꢀ  
)ꢍ/ ꢅ  
)ꢍ/ ꢄ  
)ꢍ/ ꢁ  
)ꢍ/ ꢉ  
)ꢍ/ ꢇ  
)ꢍ/ ꢊ  
)ꢍ/ ꢂ  
$- #3  
$13  
$13  
)ꢍ/ ꢀ  
)ꢍ/ ꢅ  
)ꢍ/ ꢄ  
)ꢍ/ ꢁ  
)ꢍ/ ꢉ  
)ꢍ/ ꢇ  
)ꢍ/ ꢊ  
)ꢍ/ ꢂ  
$ꢅꢅ  
$ꢅꢇ  
$ꢂ  
$-ꢁ  
$13ꢁ  
$13ꢁ  
$1ꢄꢉ  
$1ꢄꢇ  
$1ꢄꢊ  
$1ꢄꢂ  
$1ꢄꢌ  
$1ꢄꢋ  
$1ꢁꢀ  
$1ꢁꢅ  
$-ꢂ  
$13ꢂ  
$13ꢂ  
$1ꢇꢊ  
$1ꢇꢂ  
$1ꢇꢌ  
$1ꢇꢋ  
$1ꢊꢀ  
$1ꢊꢅ  
$1ꢊꢄ  
$1ꢊꢁ  
$- #3  
$13  
$13  
)ꢍ/ ꢀ  
)ꢍ/ ꢅ  
)ꢍ/ ꢄ  
)ꢍ/ ꢁ  
)ꢍ/ ꢉ  
)ꢍ/ ꢇ  
)ꢍ/ ꢊ  
)ꢍ/ ꢂ  
$- #3  
$13  
$13  
)ꢍ/ ꢀ  
)ꢍ/ ꢅ  
)ꢍ/ ꢄ  
)ꢍ/ ꢁ  
)ꢍ/ ꢉ  
)ꢍ/ ꢇ  
)ꢍ/ ꢊ  
)ꢍ/ ꢂ  
$- #3  
$13  
$13  
)ꢍ/ ꢀ  
)ꢍ/ ꢅ  
)ꢍ/ ꢄ  
)ꢍ/ ꢁ  
)ꢍ/ ꢉ  
)ꢍ/ ꢇ  
)ꢍ/ ꢊ  
)ꢍ/ ꢂ  
$- #3  
$13  
$13  
)ꢍ/ ꢀ  
)ꢍ/ ꢅ  
)ꢍ/ ꢄ  
)ꢍ/ ꢁ  
)ꢍ/ ꢉ  
)ꢍ/ ꢇ  
)ꢍ/ ꢊ  
)ꢍ/ ꢂ  
-0"4ꢀꢁꢂꢀ  
Figure 4  
Block Diagram Raw Card F SO-DIMM (×64, 1Rank, ×8)  
Notes  
2. S0, S1, ODTO, ODT1, CKEO, CKE1 resistors are  
3 Ω ±5 %  
3. BAn, An, RAS, CAS, WE resistors are 10 Ω ±5 %  
1. DQ, DQS, DM resistors are 22 Ω ±5 %  
Data Sheet  
14  
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
Electrical Characteristics  
3
Electrical Characteristics  
3.1  
Absolute Maximum Ratings  
Table 9  
Absolute Maximum Ratings  
Symbol  
Parameter  
Values  
Min.  
– 0.5  
– 1.0  
– 0.5  
5
Unit  
Note/Test  
Condition  
1)  
Max.  
2.3  
2.3  
2.3  
95  
Voltage on any pins relative to VSS  
Voltage on VDD relative to VSS  
Voltage on VDDQ relative to VSS  
VIN, VOUT  
VDD  
V
V
V
%
1)  
1)  
1)  
VDDQ  
Storage Humidity (without condensation) HSTG  
1) Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device  
functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions  
for extended periods may affect reliability  
3.2  
DC Operating Conditions  
Table 10  
Operating Conditions  
Parameter  
Symbol  
Values  
Min.  
0
Unit  
Note  
Max.  
+65  
+95  
+100  
105  
90  
Operating temperature (ambient)  
DRAM Case Temperature  
TOPR  
TCASE  
TSTG  
°C  
°C  
°C  
kPa  
%
1)2)3)4)  
5)  
0
Storage Temperature  
– 50  
69  
Barometric Pressure (operating & storage)  
Operating Humidity (relative)  
PBar  
HOPR  
10  
1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs.  
2) Within the DRAM Component Case Temperature Range all DRAM specifications will be supported  
3) Above 85 °C DRAM Case Temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs  
4) Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below  
85 °C Case Temperature before initiating Self-Refresh operation.  
5) Up to 3000 m.  
Data Sheet  
15  
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
Electrical Characteristics  
Table 11  
Supply Voltage Levels and DC Operating Conditions  
Parameter  
Symbol  
Values  
Min.  
Unit  
Note  
Nom.  
Max.  
1.9  
Device Supply Voltage  
Output Supply Voltage  
Input Reference Voltage  
SPD Supply Voltage  
VDD  
1.7  
1.8  
V
1)  
2)  
VDDQ  
VREF  
VDDSPD  
VIH (DC)  
VIL (DC)  
IL  
1.7  
1.8  
1.9  
V
0.49 x VDDQ  
1.7  
0.5 x VDDQ  
0.51 x VDDQ  
3.6  
V
—
—
—
V
DC Input Logic High  
V
REF + 0.125  
V
V
5
DDQ + 0.3  
V
DC Input Logic Low  
– 0.30  
– 5  
REF – 0.125  
V
3)  
In / Output Leakage Current  
µA  
1)Under all conditions, VDDQ must be less than or equal to VDD  
2)Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).VREF is also expected to track noise in VDDQ  
3)Input voltage for any connector pin under test of 0 V ≤ VIN ≤ VDDQ + 0.3 V; all other pins at 0 V. Current is per pin  
.
3.3  
AC Characteristics  
3.3.1  
Speed Grade Definitions  
Table 12  
Speed Grade Definition Speed Bins DDR2-800E  
Speed Grade  
DDR2–800  
–2.5  
6–6–6  
Min.  
3.75  
3.75  
3
Unit  
Note  
IFX Sort Name  
CAS-RCD-RP latencies  
Parameter  
tCK  
—
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Symbol  
tCK  
Max.  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)5)  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)  
Clock Frequency  
@ CL = 3  
8
@ CL = 4  
@ CL = 5  
@ CL = 6  
tCK  
8
tCK  
8
tCK  
2.5  
8
Row Active Time  
Row Cycle Time  
RAS-CAS-Delay  
tRAS  
tRC  
tRCD  
tRP  
45  
70000  
—
60  
15  
—
Row Precharge Time  
15  
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a  
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are  
further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) only.  
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS,  
RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode  
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is  
recognized as low.  
4) The output timing reference voltage level is VTT.  
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is  
equal to 9 x tREFI  
.
Data Sheet  
16  
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
Electrical Characteristics  
Table 13  
Speed Grade Definition Speed Bins for DDR2-533C and DDR2-400B  
Speed Grade  
DDR2–533  
–3.7  
DDR2–400  
–5  
Unit  
Note  
IFX Sort Name  
CAS-RCD-RP latencies  
Parameter  
4–4–4  
3–3–3  
tCK  
—
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Symbol  
tCK  
Min.  
5
Max.  
Min.  
5
Max.  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)5)  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)  
Clock Frequency  
@ CL = 3  
8
8
@ CL = 4  
@ CL = 5  
tCK  
3.75  
3.75  
45  
8
5
8
tCK  
8
5
8
Row Active Time  
Row Cycle Time  
RAS-CAS-Delay  
Row Precharge Time  
tRAS  
tRC  
tRCD  
tRP  
70000  
—
40  
55  
15  
15  
70000  
—
60  
15  
—
—
15  
—
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a  
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are  
further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) only.  
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS,  
RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode  
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is  
recognized as low.  
4) The output timing reference voltage level is VTT.  
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is  
equal to 9 x tREFI  
.
Data Sheet  
17  
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
Electrical Characteristics  
3.3.2  
AC Timing Parameters  
Table 14  
Timing Parameter by Speed Grade - DDR2-800  
Parameter  
Symbol  
DDR2-800  
Min.  
Unit Note  
1)2)3)4)5)6)  
Max.  
7)  
DQ output access time from CK / CK  
CAS A to CAS B command period  
CK, CK high-level width  
tAC  
tCCD  
tCH  
tCKE  
tCL  
tDAL  
tDELAY  
–400  
2
+400  
—
ps  
tCK  
tCK  
tCK  
tCK  
tCK  
ns  
0.45  
3
0.55  
—
CKE minimum high and low pulse width  
CK, CK low-level width  
0.45  
WR + tRP  
0.55  
—
Auto-Precharge write recovery + precharge time  
Minimum time clocks remain ON after CKE  
asynchronously drops LOW  
tIS + tCK + tIH ––  
DQ and DM input hold time (differential data strobe)  
DQ and DM input pulse width (each input)  
DQS output access time from CK / CK  
tDH(base)  
tDIPW  
—
––  
ps  
tCK  
ps  
tCK  
ps  
0.35  
—
tDQSCK  
tDQSL,H  
tDQSQ  
tDQSS  
tDS(base)  
tDSH  
–350  
+350  
—
DQS input low (high) pulse width (write cycle)  
DQS-DQ skew (for DQS & associated DQ signals)  
Write command to 1st DQS latching transition  
DQ and DM input setup time (differential data strobe)  
DQS falling edge hold time from CK (write cycle)  
DQS falling edge to CK setup time (write cycle)  
Clock half period  
0.35  
—
—
– 0.25  
+ 0.25 tCK  
—
—
—
—
ps  
0.2  
tCK  
tCK  
tDSS  
0.2  
tHP  
MIN. (tCL, tCH)  
Data-out high-impedance time from CK / CK  
Address and control input hold time  
tHZ  
—
tAC.MAX ps  
tIH(base)  
tIPW  
—
—
—
ps  
Address and control input pulse width  
(each input)  
0.6  
tCK  
Address and control input setup time  
DQ low-impedance time from CK / CK  
DQS low-impedance from CK / CK  
Mode register set command cycle time  
OCD drive mode output delay  
tIS(base)  
tLZ(DQ)  
tLZ(DQS)  
tMRD  
—
—
ps  
2 x tAC.MIN  
tAC.MAX ps  
tAC.MAX ps  
tAC.MIN  
2
0
—
tCK  
tOIT  
12  
ns  
Data output hold time from DQS  
Data hold skew factor  
tQH  
t
HP – tQHS  
—
tQHS  
—
—
—
75  
400  
7.8  
3.9  
—
ps  
µs  
µs  
ns  
ns  
tCK  
tCK  
ns  
ns  
8)  
9)  
Average periodic refresh Interval  
tREFI  
Auto-Refresh to Active/Auto-Refresh command period tRFC  
Precharge-All (4 banks) command period  
Read preamble  
tRP  
t
RP + 1tCK  
—
tRPRE  
tRPST  
tRRD  
0.9  
0.40  
7.5  
10  
1.1  
0.60  
—
Read postamble  
10)  
11)  
Active bank A to Active bank B command period  
—
Data Sheet  
18  
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
Electrical Characteristics  
Table 14  
Timing Parameter by Speed Grade - DDR2-800  
Symbol  
Parameter  
DDR2-800  
Min.  
Unit Note  
1)2)3)4)5)6)  
Max.  
7)  
Internal Read to Precharge command delay  
Write preamble  
tRTP  
7.5  
—
ns  
tWPRE  
tWPST  
tWR  
0.35  
0.40  
15  
—
tCK  
tCK  
ns  
Write postamble  
0.60  
—
Write recovery time for write without Auto-Precharge  
Write recovery time for write with Auto-Precharge  
Internal Write to Read command delay  
WR  
t
WR/tCK  
tCK  
ns  
tWTR  
tXARD  
7.5  
2
—
—
Exit power down to any valid command  
(other than NOP or Deselect)  
tCK  
Exit active power-down mode to Read command (slow tXARDS  
exit, lower power)  
8 – AL  
2
—
—
tCK  
tCK  
Exit precharge power-down to any valid command (other tXP  
than NOP or Deselect)  
Exit Self-Refresh to non-Read command  
Exit Self-Refresh to Read command  
tXSNR  
tXSRD  
t
RFC +10  
—
—
ns  
200  
tCK  
1) For details and notes see the relevant INFINEON component data sheet  
2) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V. See notes 4)5)6)7)  
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be  
powered down and then restarted through the specified initialization sequence before normal operation can continue.  
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a  
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.  
5) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross.  
The DQS/DQS, RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode  
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is  
recognized as low.  
7) The output timing reference voltage level is VTT. See Chapter 8 for the reference load for timing measurements.  
8) 0 ≤ TCASE ≤ 85 °C  
9) 85 °C < TCASE ≤ 95 °C  
10) x4 & x8  
11) x16  
Data Sheet  
19  
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
Electrical Characteristics  
Table 15  
Timing Parameter by Speed Grade - DDR2-533  
Symbol  
Parameter  
DDR2–533  
Min.  
Unit Note1)2)  
3)4)5)6)7)  
Max.  
+500  
—
DQ output access time from CK / CK  
CAS A to CAS B command period  
CK, CK high-level width  
tAC  
–500  
2
ps  
tCCD  
tCH  
tCKE  
tCL  
tDAL  
tDELAY  
tCK  
tCK  
tCK  
tCK  
tCK  
ns  
0.45  
0.55  
—
CKE minimum high and low pulse width  
CK, CK low-level width  
3
0.45  
0.55  
—
Auto-Precharge write recovery + precharge time  
WR + tRP  
Minimum time clocks remain ON after CKE  
asynchronously drops LOW  
tIS + tCK + tIH ––  
DQ and DM input hold time (differential data  
strobe)  
tDH(base)  
225  
–25  
––  
—
ps  
ps  
DQ and DM input hold time (single ended data  
strobe)  
tDH1(base)  
DQ and DM input pulse width (each input)  
DQS output access time from CK / CK  
DQS input low (high) pulse width (write cycle)  
tDIPW  
0.35  
—
tCK  
ps  
tCK  
ps  
tCK  
ps  
tDQSCK  
tDQSL,H  
–450  
0.35  
+450  
—
DQS-DQ skew (for DQS & associated DQ signals) tDQSQ  
—
300  
Write command to 1st DQS latching transition  
tDQSS  
WL – 0.25  
100  
WL + 0.25  
—
DQ and DM input setup time (differential data  
strobe)  
tDS(base)  
DQ and DM input setup time (single ended data  
strobe)  
t
DS1(base)  
–25  
—
ps  
DQS falling edge hold time from CK (write cycle) tDSH  
0.2  
—
—
tCK  
tCK  
DQS falling edge to CK setup time (write cycle)  
Clock half period  
tDSS  
0.2  
tHP  
MIN. (tCL, tCH)  
Data-out high-impedance time from CK / CK  
Address and control input hold time  
tHZ  
—
tAC.MAX  
ps  
ps  
tCK  
tIH(base)  
tIPW  
375  
0.6  
—
Address and control input pulse width  
(each input)  
—
Address and control input setup time  
DQ low-impedance time from CK / CK  
DQS low-impedance from CK / CK  
Mode register set command cycle time  
OCD drive mode output delay  
tIS(base)  
tLZ(DQ)  
tLZ(DQS)  
tMRD  
250  
—
ps  
ps  
ps  
tCK  
ns  
2 ° tAC.MIN  
tAC.MAX  
tAC.MAX  
—
tAC.MIN  
2
0
tOIT  
12  
Data output hold time from DQS  
Data hold skew factor  
tQH  
t
HP – tQHS  
—
tQHS  
—
—
—
75  
400  
7.8  
ps  
8)  
Average periodic refresh Interval  
tREFI  
µs  
9)  
3.9  
µs  
Auto-Refresh to Active/Auto-Refresh command  
period  
tRFC  
tRP  
—
ns  
Precharge-All (4 banks) command period  
t
RP + 1tCK  
—
ns  
Data Sheet  
20  
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
Electrical Characteristics  
Table 15  
Timing Parameter by Speed Grade - DDR2-533 (cont’d)  
Parameter  
Symbol  
DDR2–533  
Min.  
0.9  
Unit Note1)2)  
3)4)5)6)7)  
Max.  
1.1  
0.60  
—
Read preamble  
Read postamble  
tRPRE  
tRPST  
tCK  
tCK  
0.40  
7.5  
10)  
Active bank A to Active bank B command period tRRD  
ns  
1)11)  
10  
—
ns  
Internal Read to Precharge command delay  
Write preamble  
tRTP  
7.5  
—
ns  
tCK  
tCK  
ns  
tWPRE  
tWPST  
tWR  
0.35xtCK  
0.40  
15  
—
Write postamble  
0.60  
—
Write recovery time for write without Auto-  
Precharge  
Write recovery time for write with Auto-Precharge WR  
t
WR/tCK  
tCK  
ns  
Internal Write to Read command delay  
tWTR  
7.5  
2
—
—
Exit power down to any valid command  
(other than NOP or Deselect)  
tXARD  
tCK  
Exit active power-down mode to Read command tXARDS  
(slow exit, lower power)  
6 – AL  
2
—
—
tCK  
tCK  
Exit precharge power-down to any valid command tXP  
(other than NOP or Deselect)  
Exit Self-Refresh to non-Read command  
Exit Self-Refresh to Read command  
tXSNR  
tXSRD  
t
RFC +10  
—
—
ns  
200  
tCK  
1) For details and notes see the relevant INFINEON component data sheet  
2) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V. See notes 4)5)6)7)  
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be  
powered down and then restarted through the specified initialization sequence before normal operation can continue.  
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a  
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.  
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS,  
RDQS/ RDQS, input reference level is the crosspoint when in differential strobe mode  
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is  
recognized as low.  
7) The output timing reference voltage level is VTT.  
8) 0 ≤ TCASE ≤ 85 °C  
9) 85 < TCASE ≤ 95 °C  
10) x4 & x8  
11) x16  
Data Sheet  
21  
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
Electrical Characteristics  
Table 16  
Timing Parameter by Speed Grade - DDR2-400  
Symbol  
Parameter  
DDR2-400  
Min.  
Unit Note  
1)2)3)4)5)6)7)  
Max.  
+600  
—
DQ output access time from CK / CK  
CAS A to CAS B command period  
CK, CK high-level width  
tAC  
tCCD  
tCH  
tCKE  
tCL  
tDAL  
tDELAY  
–600  
2
ps  
tCK  
tCK  
tCK  
tCK  
tCK  
ns  
0.45  
0.55  
—
CKE minimum high and low pulse width  
CK, CK low-level width  
3
0.45  
0.55  
—
Auto-Precharge write recovery + precharge time  
WR + tRP  
Minimum time clocks remain ON after CKE  
asynchronously drops LOW  
tIS + tCK + tIH ––  
DQ and DM input hold time (differential data strobe)  
DQ and DM input hold time (single-ended strobe)  
DQ and DM input pulse width (each input)  
DQS output access time from CK / CK  
tDH(base)  
275  
––  
ps  
ps  
tCK  
ps  
tCK  
ps  
t
DH1(base) 25  
––  
tDIPW  
0.35  
–500  
0.35  
—
—
tDQSCK  
tDQSL,H  
tDQSQ  
tDQSS  
tDS(base)  
+500  
—
DQS input low (high) pulse width (write cycle)  
DQS-DQ skew (for DQS & associated DQ signals)  
Write command to 1st DQS latching transition  
DQ and DM input setup time (differential data strobe)  
DQ and DM input setup time (single-ended strobe)  
DQS falling edge hold time from CK (write cycle)  
DQS falling edge to CK setup time (write cycle)  
Clock half period  
350  
– 0.25  
150  
+ 0.25 tCK  
—
—
—
—
ps  
ps  
tCK  
tCK  
t
DS1(base) 25  
tDSH  
tDSS  
tHP  
0.2  
0.2  
MIN. (tCL, tCH)  
Data-out high-impedance time from CK / CK  
Address and control input hold time  
tHZ  
—
tAC.MAX ps  
tIH(base)  
tIPW  
475  
0.6  
—
—
ps  
Address and control input pulse width  
(each input)  
tCK  
Address and control input setup time  
DQ low-impedance time from CK / CK  
DQS low-impedance from CK / CK  
Mode register set command cycle time  
OCD drive mode output delay  
tIS(base)  
tLZ(DQ)  
tLZ(DQS)  
tMRD  
350  
—
ps  
2 x tAC.MIN  
tAC.MAX ps  
tAC.MAX ps  
tAC.MIN  
2
0
—
tCK  
tOIT  
12  
—
ns  
Data output hold time from DQS  
Data hold skew factor  
tQH  
tHP – tQHS  
tQHS  
—
—
—
75  
450  
7.8  
3.9  
—
ps  
µs  
µs  
ns  
ns  
tCK  
tCK  
ns  
ns  
ns  
8)  
9)  
Average periodic refresh Interval  
tREFI  
Auto-Refresh to Active/Auto-Refresh command period tRFC  
Precharge-All (4 banks) command period  
Read preamble  
tRP  
t
RP + 1tCK  
—
tRPRE  
tRPST  
tRRD  
0.9  
0.40  
7.5  
10  
1.1  
0.60  
—
Read postamble  
10)  
11)  
Active bank A to Active bank B command period  
—
Internal Read to Precharge command delay  
Data Sheet  
tRTP  
7.5  
—
22  
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
Electrical Characteristics  
Table 16  
Timing Parameter by Speed Grade - DDR2-400  
Symbol  
Parameter  
DDR2-400  
Min.  
Unit Note  
1)2)3)4)5)6)7)  
Max.  
—
Write preamble  
tWPRE  
tWPST  
tWR  
0.35  
tCK  
tCK  
ns  
Write postamble  
0.40  
0.60  
—
Write recovery time for write without Auto-Precharge  
Write recovery time for write with Auto-Precharge  
Internal Write to Read command delay  
10  
WR  
t
WR/tCK  
tCK  
ns  
tWTR  
tXARD  
7.5  
2
—
—
Exit power down to any valid command  
(other than NOP or Deselect)  
tCK  
Exit active power-down mode to Read command (slow tXARDS  
exit, lower power)  
6 – AL  
2
—
—
tCK  
tCK  
Exit precharge power-down to any valid command  
(other than NOP or Deselect)  
tXP  
Exit Self-Refresh to non-Read command  
Exit Self-Refresh to Read command  
tXSNR  
tXSRD  
t
RFC +10  
—
—
ns  
200  
tCK  
1) For details and notes see the relevant INFINEON component data sheet  
2) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V. See notes 4)5)6)7)  
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be  
powered down and then restarted through the specified initialization sequence before normal operation can continue.  
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a  
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.  
5) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross.  
The DQS/DQS, RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode  
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is  
recognized as low.  
7) The output timing reference voltage level is VTT. See Chapter 8 for the reference load for timing measurements.  
8) 0 ≤ TCASE ≤ 85 °C  
9) 85 °C < TCASE ≤ 95 °C  
10) x4 & x8  
11) x16  
Data Sheet  
23  
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
Electrical Characteristics  
3.3.3  
ODT AC Electrical Characteristics  
Table 17  
ODT AC Electrical Characteristics and Operating Conditions for DDR2-800  
Symbol Parameter / Condition  
Values  
Min.  
2
Unit  
Note  
Max.  
tAOND  
tAON  
ODT turn-on delay  
2
tCK  
ns  
ns  
tCK  
ns  
1)  
ODT turn-on  
tAC.MIN  
t
AC.MAX + 0.7 ns  
AC.MAX + 1 ns  
tAONPD  
tAOFD  
tAOF  
ODT turn-on (Power-Down Modes)  
ODT turn-off delay  
t
AC.MIN + 2 ns 2 tCK +  
t
2.5  
2.5  
2)  
ODT turn-off  
tAC.MIN  
tAC.MAX + 0.6 ns  
tAOFPD  
tANPD  
tAXPD  
ODT turn-off (Power-Down Modes)  
tAC.MIN + 2 ns 2.5 tCK + tAC.MAX + 1 ns ns  
ODT to Power Down Mode Entry Latency 3  
ODT Power Down Exit Latency  
—
—
tCK  
tCK  
8
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time  
max is when the ODT resistance is fully on. Both are measure from tAOND  
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high  
impedance. Both are measured from tAOFD  
.
.
Table 18  
ODT AC Characteristics and Operating Conditions for DDR2-533 and DDR2-400  
Symbol Parameter / Condition  
Values  
Min.  
2
Unit  
Note  
Max.  
tAOND  
tAON  
ODT turn-on delay  
2
tCK  
ns  
ns  
tCK  
ns  
1)  
ODT turn-on  
tAC.MIN  
t
AC.MAX + 1 ns  
AC.MAX + 1 ns  
tAONPD  
tAOFD  
tAOF  
ODT turn-on (Power-Down Modes)  
ODT turn-off delay  
t
AC.MIN + 2 ns 2 tCK +  
t
2.5  
2.5  
2)  
ODT turn-off  
tAC.MIN  
tAC.MAX + 0.6 ns  
tAOFPD  
tANPD  
tAXPD  
ODT turn-off (Power-Down Modes)  
tAC.MIN + 2 ns 2.5 tCK + tAC.MAX + 1 ns ns  
ODT to Power Down Mode Entry Latency 3  
ODT Power Down Exit Latency  
—
—
tCK  
tCK  
8
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time  
max is when the ODT resistance is fully on. Both are measure from tAOND  
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high  
impedance. Both are measured from tAOFD  
.
.
Data Sheet  
24  
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
Electrical Characteristics  
3.4  
IDD Specifications and Conditions  
Table 19  
I
DD Measurement Conditions 1)2)3)4)5)6)  
Parameter  
Symbol  
Operating Current 0  
IDD0  
One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH  
between valid commands. Address and control inputs are SWITCHING, Databus inputs are  
SWITCHING.  
Operating Current 1  
IDD1  
One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN  
,
t
RCD = tRCD.MIN, AL = 0, CL = CLMIN; CKE is HIGH, CS is HIGH between valid commands. Address and  
control inputs are SWITCHING, Databus inputs are SWITCHING.  
Precharge Standby Current  
IDD2N  
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are  
SWITCHING, Data bus inputs are SWITCHING.  
Precharge Power-Down Current  
Other control and address inputs are STABLE, Data bus inputs are FLOATING.  
IDD2P  
IDD2Q  
Precharge Quiet Standby Current  
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE,  
Data bus inputs are FLOATING.  
Active Standby Current  
IDD3N  
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN  
;
t
RAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are  
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.  
Active Power-Down Current  
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus  
inputs are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);  
IDD3P(0)  
IDD3P(1)  
IDD4W  
Active Power-Down Current  
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus  
inputs are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);  
Operating Current  
urst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN  
;
t
RAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are  
SWITCHING; Data Bus inputs are SWITCHING;  
Burst Refresh Current  
IDD5B  
t
CK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid  
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.  
Distributed Refresh Current  
IDD5D  
t
CK = tCK.MIN., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid  
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.  
Data Sheet  
25  
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
Electrical Characteristics  
Table 19  
I
DD Measurement Conditions (cont’d)1)2)3)4)5)6)  
Parameter  
Symbol  
Self-Refresh Current  
IDD6  
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING,  
Data bus inputs are FLOATING. IDD6 current values are guaranteed up to TCASE of 85 °C max.  
All Bank Interleave Read Current  
IDD7  
All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control  
and address bus inputs are STABLE during DESELECTS. Iout = 0 mA.  
1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V  
2) IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.  
3) Definitions for IDD see Table 20  
4) IDD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module  
level the output buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to  
HIGH.  
5) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode IDD2P  
6) For details and notes see the relevant INFINEON component data sheet  
Table 20  
Parameter  
LOW  
Definitions for IDD  
Description  
VIN ≤ VIL(ac).MAX, HIGH is defined as VIN ≥ VIH(ac).MIN  
inputs are stable at a HIGH or LOW level  
inputs are VREF = VDDQ /2  
STABLE  
FLOATING  
SWITCHING inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address  
and control signals, and inputs changing between HIGH and LOW every other data transfer (once  
per cycle) for DQ signals not including mask or strobes  
Data Sheet  
26  
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
Electrical Characteristics  
Table 21  
IDD Specification for HYS64T[16000/32020/64021]HDL–2.5–A  
Product Type  
Unit  
Notes1)  
Organization  
128 MB  
x64  
1 Rank  
–2.5  
Max.  
300  
340  
200  
20  
256 MB  
x64  
2 Ranks  
–2.5  
Max.  
320  
360  
400  
40  
512 MB  
x64  
2 Ranks  
–2.5  
Max.  
640  
Symbol  
IDD0  
2)  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
2)  
IDD1  
720  
3)  
IDD2N  
800  
3)  
IDD2P  
80  
3)  
IDD2Q  
140  
200  
90  
280  
400  
180  
40  
560  
3)  
IDD3N  
800  
3)  
IDD3P(MRS= 0)  
IDD3P(MRS= 1)  
IDD4R  
350  
3)  
20  
80  
2)  
700  
760  
380  
20  
720  
780  
400  
50  
1040  
1120  
800  
2)  
IDD4W  
IDD5B  
2)  
3)4)  
3)4)  
2)  
IDD5D  
100  
IDD6  
15  
30  
65  
IDD7  
680  
700  
1280  
1) Calculated values from component data. ODT disabled. IDD1, IDD4R and IDD7 are defined with the outputs disabled  
2) The other rank is in IDD2P Precharge Power-Down Standby Current mode  
3) Both ranks are in the same IDD mode  
4) Values for 0 °C ≤ TCASE ≤ 85 °C  
Data Sheet  
27  
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
Electrical Characteristics  
Table 22  
IDD Specification for HYS64T16000GDL-3.7-A  
Product Type  
Organization  
HYS64T16000HDL-3.7-A  
Unit  
Note1)  
128 MB  
×64  
1 Rank  
–3.7  
Max.  
220  
240  
140  
20  
Symbol  
IDD0  
2)  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
2)  
IDD1  
3)  
IDD2N  
3)  
IDD2P  
3)  
IDD2Q  
100  
140  
60  
3)  
IDD3N  
3)  
IDD3P(MRS= 0)  
IDD3P(MRS= 1)  
IDD4R  
3)  
20  
2)  
460  
520  
360  
20  
2)  
IDD4W  
IDD5B  
2)  
3)4)  
3)4)  
2)  
IDD5D  
IDD6  
15  
IDD7  
600  
1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled.  
2) The other rank is in IDD2P Precharge Power-Down Standby Current mode  
3) Both ranks are in the same IDD mode  
4) Values for 0 °C ≤ TCASE ≤ 85 °C  
Data Sheet  
28  
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
Electrical Characteristics  
Table 23  
IDD Specification for HYS64T16000HDL-5-A  
Product Type  
Organization  
HYS64T16000HDL-5-A  
Unit  
Note1)  
128 MB  
×64  
1 Rank  
–5  
Symbol  
IDD0  
Max.  
200  
220  
110  
20  
2)  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
2)  
IDD1  
3)  
IDD2N  
3)  
IDD2P  
3)  
IDD2Q  
80  
3)  
IDD3N  
120  
50  
3)  
IDD3P(MRS= 0)  
IDD3P(MRS= 1)  
IDD4R  
3)  
20  
2)  
360  
420  
340  
20  
2)  
IDD4W  
IDD5B  
2)  
3)4)  
3)4)  
2)  
IDD5D  
IDD6  
15  
IDD7  
560  
1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled.  
2) The other rank is in IDD2P Precharge Power-Down Standby Current mode  
3) Both ranks are in the same IDD mode  
4) Values for 0 °C ≤ TCASE ≤ 85 °C  
Data Sheet  
29  
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
Electrical Characteristics  
3.4.1  
IDD Test Conditions  
For testing the IDD parameters, the timing parameters as in Table 24 are used.  
Table 24  
IDD Measurement Test Conditions for DDR2–400 and DDR2–533  
Parameter  
Symbol  
–3.7  
–5  
Unit  
DDR2–533C  
DDR2–400B  
CAS Latency  
CL(IDD)  
tCK(IDD)  
tRCD(IDD)  
tRC(IDD)  
4
3
tCK  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
µs  
Clock Cycle Time  
3.75  
15  
60  
7.5  
10  
5
Active to Read or Write delay  
15  
Active to Active / Auto-Refresh command period  
55  
Active bank A to Active bank B command delay ×81) tRRD(IDD)  
×162) tRRD(IDD)  
7.5  
10  
Active to Precharge Command  
Active to Precharge Command  
tRAS.MIN(IDD) 45  
tRAS.MAX(IDD) 70000  
40  
70000  
15  
Precharge Command Period  
tRP(IDD)  
tREFI  
15  
Average periodic Refresh interval  
1) ×4 & ×8 (1 kB page size)  
7.8  
7.8  
2) ×16 (2 kB page size), not on 256M components  
3.4.2  
On Die Termination (ODT) Current  
The ODT function adds additional current consumption current consumption for any terminated input pin,  
to the DDR2 SDRAM when enabled by the EMRS(1). depends on the input pin is in tri-state or driving 0 or 1,  
Depending on address bits A[6,2] in the EMRS(1) a as long a ODT is enabled during a given period of time.  
“weak” or “strong” termination can be selected. The  
Table 25  
ODT current per terminated pin  
Parameter  
Symbol Min.  
Typ.  
Max. Unit  
EMRS(1) State  
Enabled ODT current per DQ  
IODTO  
5
6
7.5 mA/DQ A6 = 0, A2 = 1  
ODT is HIGH; Data Bus inputs are FLOATING  
2.5  
7.5  
10  
5
3
3.75 mA/DQ A6 = 1, A2 = 0  
11.25 mA/DQ A6 = 1, A2 = 1  
9
Active ODT current per DQ  
ODT is HIGH; worst case of Data Bus inputs are  
STABLE or SWITCHING.  
IODTT  
12  
6
15  
mA/DQ A6 = 0, A2 = 1  
mA/DQ A6 = 1, A2 = 0  
7.5  
15  
18  
22.5 mA/DQ A6 = 1, A2 = 0  
Note:For power consumption calculations the ODT duty cycle has to be taken into account  
Data Sheet  
30  
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
SPD Codes  
4
SPD Codes  
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet.  
SPD stands for serial presence detect. All values with XX in the table are module specific bytes which are defined  
during production.  
List of SPD Code Tables  
•
•
Table 26 “SPD Codes for PC2–6400S–666” on Page 31  
Table 27 “SPD Codes for PC2–4200S–444 and PC2–3200S–333” on Page 35  
Table 26  
SPD Codes for PC2–6400S–666  
Product Type  
Organization  
128 MB  
×64  
256 MB  
512 MB  
×64  
×64  
1 Rank (×16)  
2 Ranks (×16)  
2 Ranks (×8)  
Label Code  
PC2–6400S–666 PC2–6400S–666 PC2–6400S–666  
JEDEC SPD Revision  
Byte# Description  
Rev. 1.2  
HEX  
80  
Rev. 1.2  
HEX  
80  
Rev. 1.2  
HEX  
80  
0
Programmed SPD Bytes in EEPROM  
1
Total number of Bytes in EEPROM  
Memory Type (DDR2)  
Number of Row Addresses  
Number of Column Addresses  
DIMM Rank and Stacking Information  
Data Width  
08  
08  
08  
2
08  
08  
08  
3
0D  
09  
0D  
09  
0D  
0A  
61  
4
5
60  
61  
6
40  
40  
40  
7
Not used  
00  
00  
00  
8
Interface Voltage Level  
05  
05  
05  
9
t
t
CK @ CLMAX (Byte 18) [ns]  
25  
25  
25  
10  
11  
12  
13  
14  
15  
16  
17  
18  
AC SDRAM @ CLMAX (Byte 18) [ns]  
40  
40  
40  
Error Correction Support (non-ECC, ECC) 00  
00  
00  
Refresh Rate and Type  
Primary SDRAM Width  
Error Checking SDRAM Width  
Not used  
82  
10  
00  
00  
0C  
04  
70  
82  
82  
10  
08  
00  
00  
00  
00  
Burst Length Supported  
Number of Banks on SDRAM Device  
Supported CAS Latencies  
0C  
04  
0C  
04  
70  
70  
Data Sheet  
31  
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
SPD Codes  
Table 26  
SPD Codes for PC2–6400S–666 (cont’d)  
Product Type  
Organization  
128 MB  
×64  
256 MB  
512 MB  
×64  
×64  
1 Rank (×16)  
2 Ranks (×16)  
2 Ranks (×8)  
Label Code  
PC2–6400S–666 PC2–6400S–666 PC2–6400S–666  
JEDEC SPD Revision  
Byte# Description  
Rev. 1.2  
HEX  
01  
Rev. 1.2  
HEX  
01  
Rev. 1.2  
HEX  
01  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
DIMM Mechanical Characteristics  
DIMM Type Information  
DIMM Attributes  
04  
04  
04  
00  
00  
00  
Component Attributes  
03  
03  
03  
t
t
t
t
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]  
AC SDRAM @ CLMAX -1 [ns]  
CK @ CLMAX -2 (Byte 18) [ns]  
AC SDRAM @ CLMAX -2 [ns]  
RP.MIN [ns]  
30  
30  
30  
45  
45  
45  
3D  
50  
3D  
50  
3D  
50  
3C  
28  
3C  
28  
3C  
1E  
3C  
2D  
40  
RRD.MIN [ns]  
RCD.MIN [ns]  
3C  
2D  
20  
3C  
2D  
20  
RAS.MIN [ns]  
Module Density per Rank  
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]  
AH.MIN and tCH.MIN [ns]  
DS.MIN [ns]  
15  
15  
15  
22  
22  
22  
05  
05  
05  
DH.MIN [ns]  
12  
12  
12  
WR.MIN [ns]  
3C  
1E  
1E  
00  
3C  
1E  
1E  
00  
3C  
1E  
1E  
00  
WTR.MIN [ns]  
RTP.MIN [ns]  
Analysis Characteristics  
t
t
t
t
t
t
RC and tRFC Extension  
RC.MIN [ns]  
00  
00  
00  
3C  
4B  
80  
3C  
4B  
80  
3C  
4B  
80  
RFC.MIN [ns]  
CK.MAX [ns]  
DQSQ.MAX [ns]  
QHS.MAX [ns]  
14  
14  
14  
1E  
00  
1E  
00  
1E  
00  
PLL Relock Time  
Data Sheet  
32  
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
SPD Codes  
Table 26  
SPD Codes for PC2–6400S–666 (cont’d)  
Product Type  
Organization  
128 MB  
×64  
256 MB  
512 MB  
×64  
×64  
1 Rank (×16)  
2 Ranks (×16)  
2 Ranks (×8)  
Label Code  
PC2–6400S–666 PC2–6400S–666 PC2–6400S–666  
JEDEC SPD Revision  
Byte# Description  
Rev. 1.2  
HEX  
55  
Rev. 1.2  
HEX  
55  
Rev. 1.2  
HEX  
53  
47  
48  
49  
50  
TCASE.MAX Delta / ∆T4R4W Delta  
Psi(T-A) DRAM  
82  
82  
82  
∆T0 (DT0)  
5B  
5B  
5B  
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q,  
3E  
3E  
3E  
RDIMM)  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
∆T2P (DT2P)  
29  
29  
36  
19  
6C  
17  
2A  
00  
00  
00  
00  
12  
88  
C1  
00  
00  
00  
00  
00  
00  
00  
xx  
29  
29  
36  
19  
6C  
17  
2A  
00  
00  
00  
00  
12  
89  
C1  
00  
00  
00  
00  
00  
00  
00  
xx  
29  
29  
36  
19  
4E  
17  
26  
00  
00  
00  
00  
12  
74  
C1  
00  
00  
00  
00  
00  
00  
00  
xx  
∆T3N (DT3N)  
∆T3P.fast (DT3P fast)  
∆T3P.slow (DT3P slow)  
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)  
∆T5B (DT5B)  
∆T7 (DT7)  
Psi(ca) PLL  
Psi(ca) REG  
∆TPLL (DTPLL)  
∆TREG (DTREG) / Toggle Rate  
SPD Revision  
Checksum of Bytes 0-62  
JEDEC ID Code of Infineon (1)  
JEDEC ID Code of Infineon (2)  
JEDEC ID Code of Infineon (3)  
JEDEC ID Code of Infineon (4)  
JEDEC ID Code of Infineon (5)  
JEDEC ID Code of Infineon (6)  
JEDEC ID Code of Infineon (7)  
JEDEC ID Code of Infineon (8)  
Module Manufacturer Location  
Product Type, Char 1  
36  
36  
36  
Data Sheet  
33  
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
SPD Codes  
Table 26  
SPD Codes for PC2–6400S–666 (cont’d)  
Product Type  
Organization  
128 MB  
×64  
256 MB  
512 MB  
×64  
×64  
1 Rank (×16)  
2 Ranks (×16)  
2 Ranks (×8)  
Label Code  
PC2–6400S–666 PC2–6400S–666 PC2–6400S–666  
JEDEC SPD Revision  
Byte# Description  
Rev. 1.2  
HEX  
34  
Rev. 1.2  
HEX  
34  
Rev. 1.2  
HEX  
34  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
Product Type, Char 2  
Product Type, Char 3  
54  
54  
54  
Product Type, Char 4  
31  
33  
36  
Product Type, Char 5  
36  
32  
34  
Product Type, Char 6  
30  
30  
30  
Product Type, Char 7  
30  
32  
32  
Product Type, Char 8  
30  
30  
31  
Product Type, Char 9  
48  
48  
48  
Product Type, Char 10  
Product Type, Char 11  
Product Type, Char 12  
Product Type, Char 13  
Product Type, Char 14  
Product Type, Char 15  
Product Type, Char 16  
Product Type, Char 17  
Product Type, Char 18  
Module Revision Code  
Test Program Revision Code  
Module Manufacturing Date Year  
Module Manufacturing Date Week  
Module Serial Number  
44  
44  
44  
4C  
32  
4C  
32  
4C  
32  
2E  
35  
2E  
35  
2E  
35  
41  
41  
41  
20  
20  
20  
20  
20  
20  
20  
20  
20  
0x  
0x  
0x  
xx  
xx  
xx  
xx  
xx  
xx  
xx  
xx  
xx  
95 -  
98  
xx  
xx  
xx  
99 -  
127  
Not used  
00  
00  
00  
Data Sheet  
34  
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
SPD Codes  
Table 27  
SPD Codes for PC2–4200S–444 and PC2–3200S–333  
Product Type  
Organization  
128 MB  
×64  
128 MB  
×64  
1 Rank (×16)  
1 Rank (×16)  
Label Code  
PC2–4200S–444 PC2–3200S–333  
JEDEC SPD Revision  
Rev. 1.1  
HEX  
80  
Rev. 1.1  
HEX  
80  
Byte#  
0
Description  
Programmed SPD Bytes in EEPROM  
Total number of Bytes in EEPROM  
Memory Type (DDR2)  
Number of Row Addresses  
Number of Column Addresses  
DIMM Rank and Stacking Information  
Data Width  
1
08  
08  
2
08  
08  
3
0D  
09  
0D  
09  
4
5
60  
60  
6
40  
40  
7
Not used  
00  
00  
8
Interface Voltage Level  
05  
05  
9
t
t
CK @ CLMAX (Byte 18) [ns]  
3D  
50  
50  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
AC SDRAM @ CLMAX (Byte 18) [ns]  
60  
Error Correction Support (non-ECC, ECC)  
Refresh Rate and Type  
00  
00  
82  
82  
Primary SDRAM Width  
10  
10  
Error Checking SDRAM Width  
Not used  
00  
00  
00  
00  
Burst Length Supported  
Number of Banks on SDRAM Device  
Supported CAS Latencies  
DIMM Mechanical Characteristics  
DIMM Type Information  
DIMM Attributes  
0C  
04  
0C  
04  
38  
38  
00  
00  
04  
04  
00  
00  
Component Attributes  
01  
01  
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]  
AC SDRAM @ CLMAX -1 [ns]  
CK @ CLMAX -2 (Byte 18) [ns]  
AC SDRAM @ CLMAX -2 [ns]  
3D  
50  
50  
60  
50  
50  
60  
60  
Data Sheet  
35  
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
SPD Codes  
Table 27  
SPD Codes for PC2–4200S–444 and PC2–3200S–333 (cont’d)  
Product Type  
Organization  
128 MB  
×64  
128 MB  
×64  
1 Rank (×16)  
1 Rank (×16)  
Label Code  
PC2–4200S–444 PC2–3200S–333  
JEDEC SPD Revision  
Rev. 1.1  
HEX  
3C  
28  
Rev. 1.1  
HEX  
3C  
28  
Byte#  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
Description  
t
t
t
t
RP.MIN [ns]  
RRD.MIN [ns]  
RCD.MIN [ns]  
RAS.MIN [ns]  
3C  
2D  
20  
3C  
28  
Module Density per Rank  
20  
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]  
AH.MIN and tCH.MIN [ns]  
DS.MIN [ns]  
25  
35  
37  
47  
10  
15  
DH.MIN [ns]  
22  
27  
WR.MIN [ns]  
3C  
1E  
1E  
00  
3C  
28  
WTR.MIN [ns]  
RTP.MIN [ns]  
1E  
00  
Analysis Characteristics  
t
t
t
t
t
t
RC and tRFC Extension  
RC.MIN [ns]  
00  
00  
3C  
4B  
80  
37  
RFC.MIN [ns]  
4B  
80  
CK.MAX [ns]  
DQSQ.MAX [ns]  
QHS.MAX [ns]  
1E  
28  
23  
2D  
00  
PLL Relock Time  
CASE.MAX Delta / ∆T4R4W Delta  
00  
T
56  
56  
Psi(T-A) DRAM  
7A  
32  
7A  
2A  
20  
∆T0 (DT0)  
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)  
∆T2P (DT2P)  
29  
1F  
1B  
25  
1F  
17  
∆T3N (DT3N)  
∆T3P.fast (DT3P fast)  
∆T3P.slow (DT3P slow)  
1E  
13  
13  
Data Sheet  
36  
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
SPD Codes  
Table 27  
SPD Codes for PC2–4200S–444 and PC2–3200S–333 (cont’d)  
Product Type  
Organization  
128 MB  
×64  
128 MB  
×64  
1 Rank (×16)  
1 Rank (×16)  
Label Code  
PC2–4200S–444 PC2–3200S–333  
JEDEC SPD Revision  
Rev. 1.1  
HEX  
2E  
14  
Rev. 1.1  
HEX  
28  
Byte#  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
Description  
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)  
∆T5B (DT5B)  
13  
∆T7 (DT7)  
23  
20  
Psi(ca) PLL  
00  
00  
Psi(ca) REG  
00  
00  
∆TPLL (DTPLL)  
00  
00  
∆TREG (DTREG) / Toggle Rate  
SPD Revision  
00  
00  
11  
11  
Checksum of Bytes 0-62  
JEDEC ID Code of Infineon (1)  
JEDEC ID Code of Infineon (2)  
JEDEC ID Code of Infineon (3)  
JEDEC ID Code of Infineon (4)  
JEDEC ID Code of Infineon (5)  
JEDEC ID Code of Infineon (6)  
JEDEC ID Code of Infineon (7)  
JEDEC ID Code of Infineon (8)  
Module Manufacturer Location  
Product Type, Char 1  
Product Type, Char 2  
Product Type, Char 3  
Product Type, Char 4  
Product Type, Char 5  
Product Type, Char 6  
Product Type, Char 7  
Product Type, Char 8  
Product Type, Char 9  
Product Type, Char 10  
47  
9B  
C1  
00  
C1  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
xx  
xx  
36  
36  
34  
34  
54  
54  
31  
31  
36  
36  
30  
30  
30  
30  
30  
30  
48  
48  
44  
44  
Data Sheet  
37  
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
SPD Codes  
Table 27  
SPD Codes for PC2–4200S–444 and PC2–3200S–333 (cont’d)  
Product Type  
Organization  
128 MB  
×64  
128 MB  
×64  
1 Rank (×16)  
1 Rank (×16)  
Label Code  
PC2–4200S–444 PC2–3200S–333  
JEDEC SPD Revision  
Rev. 1.1  
HEX  
4C  
33  
Rev. 1.1  
HEX  
4C  
35  
Byte#  
83  
Description  
Product Type, Char 11  
Product Type, Char 12  
Product Type, Char 13  
Product Type, Char 14  
Product Type, Char 15  
Product Type, Char 16  
Product Type, Char 17  
Product Type, Char 18  
Module Revision Code  
Test Program Revision Code  
Module Manufacturing Date Year  
Module Manufacturing Date Week  
Module Serial Number  
84  
85  
2E  
37  
41  
86  
20  
87  
41  
20  
88  
20  
20  
89  
20  
20  
90  
20  
20  
91  
1x  
1x  
92  
xx  
xx  
93  
xx  
xx  
94  
xx  
xx  
95 -  
98  
xx  
xx  
99 -  
127  
Not used  
00  
00  
Data Sheet  
38  
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
Package Outlines  
5
Package Outlines  
ꢂꢇꢄꢂ  
ꢆꢄꢉ -!8ꢄ  
›ꢀꢄꢅ  
ꢂꢆꢄꢂ  
ꢅ
ꢅꢀꢀ  
ꢊꢋꢄꢅꢈꢌ  
›ꢀꢄꢅ  
ꢊꢋꢄꢃꢈꢌ  
›ꢀꢄꢅ  
ꢅ
ꢅꢇꢄꢈꢈ  
ꢀꢄꢅꢈ  
›ꢀꢄꢅ  
ꢋꢄꢇ  
ꢊꢅꢄꢈꢌ  
›ꢀꢄꢅ  
›ꢀꢄꢅ  
ꢅꢅꢄꢃ  
›ꢀꢄꢅ  
ꢃꢇꢄꢃ  
ꢊꢅꢄꢉꢌ  
ꢊꢋꢄꢃꢈꢌ  
›ꢀꢄꢅ  
ꢊꢋꢄꢅꢈꢌ  
ꢋꢀꢀ  
ꢋꢄꢃ  
ꢅ
ꢅꢀꢅ  
ꢋ -).ꢄ  
$ETAIL OF CONTACTS  
›ꢀꢄꢀꢆ  
ꢀꢄꢃꢈ  
›ꢀꢄꢅ  
ꢀꢄꢂ  
"URNISHEDꢍ NO BURR ALLOWED  
',$ꢀꢁꢂꢃꢁ  
Figure 5  
Package Outline Raw Card A L-DIM-200-31  
Data Sheet  
39  
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
Package Outlines  
ꢂꢈꢅꢂ  
ꢇꢅꢄ -!8ꢅ  
›ꢀꢅꢆ  
ꢂꢇꢅꢂ  
ꢆ
ꢆꢀꢀ  
ꢊꢋꢅꢆꢉꢌ  
›ꢀꢅꢆ  
ꢊꢋꢅꢃꢉꢌ  
›ꢀꢅꢆ  
ꢆ
ꢆꢈꢅꢉꢉ  
ꢀꢅꢆꢉ  
›ꢀꢅꢆ  
ꢋꢅꢈ  
ꢊꢆꢅꢉꢌ  
›ꢀꢅꢆ  
›ꢀꢅꢆ  
ꢆꢆꢅꢃ  
›ꢀꢅꢆ  
ꢃꢈꢅꢃ  
ꢊꢆꢅꢄꢌ  
ꢊꢋꢅꢃꢉꢌ  
›ꢀꢅꢆ  
ꢊꢋꢅꢆꢉꢌ  
ꢋꢀꢀ  
ꢋꢅꢃ  
ꢆ
ꢆꢀꢆ  
ꢋ -).ꢅ  
$ETAIL OF CONTACTS  
›ꢀꢅꢀꢇ  
ꢀꢅꢃꢉ  
›ꢀꢅꢆ  
ꢀꢅꢂ  
"URNISHEDꢍ NO BURR ALLOWED  
',$ꢀꢁꢂꢃꢄ  
Figure 6  
Package Outline Raw Card C L-DIM-200-30  
Data Sheet  
40  
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
Package Outlines  
ꢂꢃꢅꢂ  
ꢇꢅꢉ -!8ꢅ  
›ꢀꢅꢆ  
ꢂꢇꢅꢂ  
ꢆ
ꢆꢀꢀ  
ꢊꢋꢅꢆꢄꢌ  
›ꢀꢅꢆ  
ꢊꢋꢅꢈꢄꢌ  
›ꢀꢅꢆ  
ꢆ
ꢆꢃꢅꢄꢄ  
ꢀꢅꢆꢄ  
›ꢀꢅꢆ  
ꢋꢅꢃ  
ꢊꢆꢅꢄꢌ  
›ꢀꢅꢆ  
›ꢀꢅꢆ  
ꢆꢆꢅꢈ  
›ꢀꢅꢆ  
ꢈꢃꢅꢈ  
ꢊꢆꢅꢉꢌ  
ꢊꢋꢅꢈꢄꢌ  
›ꢀꢅꢆ  
ꢊꢋꢅꢆꢄꢌ  
ꢋꢀꢀ  
ꢋꢅꢈ  
ꢆ
ꢆꢀꢆ  
ꢋ -).ꢅ  
$ETAIL OF CONTACTS  
›ꢀꢅꢀꢇ  
ꢀꢅꢈꢄ  
›ꢀꢅꢆ  
ꢀꢅꢂ  
"URNISHEDꢍ NO BURR ALLOWED  
',$ꢀꢁꢂꢃꢄ  
Figure 7  
Package Outline Raw Card F - L-DIM-200-34  
Data Sheet  
41  
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A  
Small Outline DDR2 SDRAM Modules  
Product Type Nomenclature (DDR2 DRAMs and DIMMs)  
6
Product Type Nomenclature (DDR2 DRAMs and DIMMs)  
Infineon’s nomenclature uses simple coding combined with some proprietary coding. Table 28 provides examples  
for module and component product type number as well as the field number. The detailed field description together  
with possible values and coding explanation is listed for modules in Table 29 and for components in Table 30.  
Table 28  
Nomenclature Fields and Examples  
Field Number  
Example for  
1
2
3
T
T
4
5
6
7
0
0
8
9
10  
–5  
–5  
11  
Micro-DIMM  
DDR2 DRAM  
HYS  
HYB  
64  
18  
64  
512  
0
2
K
A
M
C
–A  
16  
1) Multiplying “Memory Density per I/O” with “Module Data  
Width” and dividing by 8 for Non-ECC and 9 for ECC  
modules gives the overall module memory density in  
MBytes as listed in column “Coding”.  
Table 29  
DDR2 DIMM Nomenclature  
Values Coding  
Field Description  
1
INFINEON  
HYS  
Constant  
Modul Prefix  
2
Module Data  
Width [bit]  
64  
72  
T
Non-ECC  
ECC  
Table 30  
DDR2 DRAM Nomenclature  
Values Coding  
Field Description  
3
4
DRAM  
Technology  
DDR2  
1
2
3
4
INFINEON  
Component Prefix  
HYB  
Constant  
SSTL1.8  
DDR2  
Memory Density  
per I/O [Mbit];  
Module Density1)  
32  
256 MByte  
512 MByte  
1 GByte  
Interface Voltage 18  
[V]  
64  
DRAM  
Technology  
T
128  
256  
512  
0 .. 9  
2 GByte  
Component  
256  
512  
1G  
2G  
40  
256 Mbit  
512 Mbit  
1 Gbit  
2 Gbit  
×4  
4 GByte  
Density [Mbit]  
5
6
Raw Card  
Generation  
Look up table  
Number of Module 0, 2, 4 1, 2, 4  
Ranks  
5+6 Number of I/Os  
7
8
Product Variations 0 .. 9  
Look up table  
80  
×8  
Package,  
A .. Z  
Look up table  
16  
×16  
Lead-Free Status  
7
8
Product Variations 0 .. 9  
Look up table  
First  
9
Module Type  
D
SO-DIMM  
Die Revision  
A
B
C
M
Micro-DIMM  
Registered  
Second  
R
9
Package,  
FBGA,  
U
Unbuffered  
Lead-Free Status  
lead-containing  
–2.5  
–3  
–3S  
–3.7  
–5  
–A  
–B  
PC2–6400 6–6–6  
PC2–5300 4–4–4  
PC2–5300 5–5–5  
PC2–4200 4–4–4  
PC2–3200 3–3–3  
First  
F
FBGA, lead-free  
DDR2-800E 6-6-6  
DDR2-667C 4-4-4  
DDR2-667D 5-5-5  
DDR2-533C 4-4-4  
DDR2-400B 3-3-3  
10  
11  
Speed Grade  
Die Revision  
10  
Speed Grade  
–2.5  
–3  
–3S  
–3.7  
–5  
Second  
Data Sheet  
42  
Rev. 1.1, 2005-06  
02182004-HWZ1-64OM  
w w w . i n f i n e o n . c o m  
Published by Infineon Technologies AG  
厂商 型号 描述 页数 下载

INFINEON

 		HYS64-72V2200GU-8 3.3V 2M ×64 /72- 1位BANK SDRAM模块3.3V 4M ×64 /72- 2位BANK SDRAM模块[ 3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module ] 17 页

INFINEON

 		HYS64-74V8200GU 3.3 V 8M ×64 /72- 1位银行SDRAM模块3.3 V 16M ×64 /72- 2位银行SDRAM模块[ 3.3 V 8M x 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M x 64/72-Bit 2 Bank SDRAM Module ] 17 页

INFINEON

 		HYS6472V16200GU 3.3 V 16M ×64 /72-位SDRAM模块3.3 V 32M ×64 /72-位SDRAM模块3.3 V 64M ×64 /72-位SDRAM模块[ 3.3 V 16M x 64/72-Bit SDRAM Modules 3.3 V 32M x 64/72-Bit SDRAM Modules 3.3 V 64M x 64/72-Bit SDRAM Modules ] 17 页

INFINEON

 		HYS6472V4200GU 3.3V 4M ×64 /72- 1位BANK SDRAM模块3.3V 8M ×64 /72- 2位BANK SDRAM模块[ 3.3V 4M x 64/72-Bit 1 BANK SDRAM Module 3.3V 8M x 64/72-Bit 2 BANK SDRAM Module ] 15 页

INFINEON

 		HYS64D128020GBDL-6-A [ DDR DRAM Module, 128MX64, 0.7ns, CMOS, SO-DIMM-200 ] 11 页

ETC

 		HYS64D128020GBDL-7-A ？ 1GB （ 1024Mx64 ） PC2100 2银行？\n[ ?1GB (1024Mx64) PC2100 2-bank? ] 11 页

INFINEON

 		HYS64D128020GU-7-A 2.5 V 184针无缓冲DDR- SDRAM我模块[ 2.5 V 184-pin Unbuffered DDR-I SDRAM Modules ] 18 页

INFINEON

 		HYS64D128020GU-8-A 2.5 V 184针无缓冲DDR- SDRAM我模块[ 2.5 V 184-pin Unbuffered DDR-I SDRAM Modules ] 18 页

QIMONDA

 		HYS64D128020GU-8-A [ DDR DRAM Module, 128MX64, 0.8ns, CMOS, PDMA184 ] 18 页

INFINEON

 		HYS64D128021 200针的小型双列直插式内存模块[ 200-Pin Small Outline Dual-In-Line Memory Modules ] 23 页

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