HYS72Vx2x0GR
Registered SDRAM-Modules
Notes:
1. The specified values are valid when addresses are changed no more than once during tck(min.)
and when No Operation commands are registered on every rising clock edge during tRC(min).
Values are shown per SDRAM component.
2. The specified values are valid when data inputs (DQ’s) are stable during tRC(min.).
3. An initial pause of 100µs is required after power-up, then a Precharge All Banks command must
be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can
begin. Also the on-DIMM PLL must be given enough clock cycles to stabilize (tSTAB) before any
operation can be guaranteed.
4. AC timing tests have V = 0.8V and V = 2.0V with the timing referenced to the 1.4 V crossover
il
ih
point. The transition time is measured between V and V . All AC measurements assume
ih
il
t =1nswith the AC output load circuit shown. Specified tac and toh parameters are measured
T
with a 50 pF only, without any resisitve termination and with a input signal of 1V / ns edge rate
between 0.8V and 2.0 V.
2.0V
0.8V
+ 1.4 V
CLOCK
50 Ohm
t
T
tSETUP tHOLD
Z=50 Ohm
I/O
1.4V
INPUT
50 pF
tAC
tAC
I/O
tLZ
50 pF
tOH
Meaurement conditions for
tac and toh
1.4V
OUTPUT
tHZ
5. Any time that the refresh Period has been exceeded, a minimum of two Auto (CRB) Refresh
commands must be given to “wake-up“ the device.
6. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied
once the Self Refresh Exit command is registered.
7. Referenced to the time which the output achieves the open circuit condition, not to output voltage
levels.
8. Due to the usage of a register device on all input and address signals, all external command cycle
are delayed by one clock (Reg-DIMM Latency = 1) on the module board.
9. Delayed by one clock cycle due to the use of the register device.
INFINEON Technologies
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