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EZ-PD™ CCG4

USB Type-C Port Controller

General Description

EZ-PD™ CCG4 is a dual USB Type-C controller that complies with the latest USB Type-C and PD standards. EZ-PD CCG4 provides

a complete dual USB Type-C and USB-Power Delivery port control solution for notebooks, power adapters and docking stations. It

can also be used in dual role and downstream facing port applications. EZ-PD CCG4 uses Cypress’s proprietary M0S8 technology

with a 32-bit, 48-MHz ARM^®Cortex^®-M0 processor with 128 KB flash and integrates two complete Type-C Transceivers including the

Type-C termination resistors R_Pand R_D.

Low-Power Operation

Applications

■ 2.7-V to 5.5-V operation

■ Notebooks

■ Independent supply voltage pin for GPIO that allows 1.71-V to

■ Power adapters

5.5-V signaling on the I/Os

■ Docking stations

■ Reset: 1.0 µA, Deep Sleep: 2.5 µA, Sleep: 2.5 mA

System-Level ESD on CC Pins

Features

■ ±8-kVContactDischargeand±15-kVAirGapDischargebased

on IEC61000-4-2 level 4C

32-bit MCU Subsystem

■ 48-MHz ARM Cortex-M0 CPU

■ 128-KB Flash

Hot Swappable I/Os

■ Port 1 I²C pins and CC1, CC2 pins are hot-swappable

■ 8-KB SRAM

Integrated Digital Blocks

■ Up to four integrated timers and counters to meet response

Packages

■ 6.0 mm  6.0 mm, 0.6 mm, 40-pin QFN

■ Supports industrial temperature range (–40 °C to +85 °C)

times required by the USB-PD protocol

■ Four run-time serial communication blocks (SCBs) with

reconfigurable I²C, SPI, or UART functionality

Clocks and Oscillators

■ Integrated oscillator eliminating the need for external clock

Type-C and USB-PD Support

■ Integrated USB Power Delivery 3.0 support

■ Two integrated USB-PD BMC transceivers

■ Integrated UFP^[1](R_D) and current sources for DFP^[2](R_P) on

both Type-C ports

■ Integrated dead battery termination for DRP (Power

Source/Sink) applications

■ Supports two USB Type-C ports

■ Integrated VCONN FETs to power EMCA cables

■ Integrated fast role swap and extended data messaging

Notes

1. UFP refers to Power Sink.

2. DFP refers to Power Source.

Cypress Semiconductor Corporation

Document Number: 001-98440 Rev. *F

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 30, 2017

EZ-PD™ CCG4

Logic Block Diagram

CCG4: Single-ChipType-C Controller

MCU Subsystem

I/O Subsystem

CC_PORT1⁵

Integrated Digital Blocks

4 x TCPWM¹

4 x SCB²

CORTEX-M0

48 MHz

CC_PORT2⁵

(I²C, SPI, UART)

2x V_CONN

FETs

(PORT1)

Profiles and

Configurations

2x V_CONN

FETs

2 x Baseband MAC

2 x Baseband PHY

Integrated R_d³and R_p

4 x 8-bit SAR ADC

Flash

(128KB)

(PORT2)

GPIOs⁶

4

SRAM

(8KB)

Serial Wire Debug

1. Timer, counter, pulse width modulation block

2. Serial communication block configurable as UART, SPI, or I²C

3. Termination resistor denoting a UFP

4. Current Sources to indicate a DFP

5. Configuration Channel

6. General purpose input/output

Document Number: 001-98440 Rev. *F

Page 2 of 30

EZ-PD™ CCG4

Available Firmware and Software Tools

EZ-PD Configuration Utility

The EZ-PD Configuration Utility is a GUI-based Microsoft Windows application developed by Cypress to guide a CCGx user through

the process of configuring and programming the chip. The utility allows users to:

1. Select and configure the parameters they want to modify

2. Program the resulting configuration onto the target CCGx device.

The utility works with the Cypress supplied CCG1, CCG2, CCG3, and CCG4 kits, which host the CCGx controllers along with a USB

interface. This version of the EZ-PD Configuration Utility supports configuration and firmware update operations on CCGx controllers

implementing EMCA and Display Dongle applications. Support for other applications, such as Power Adapters and Notebook port

controllers, will be provided in later versions of the utility.

You can download the EZ-PD Configuration Utility and its associated documentation at the following link:

http://www.cypress.com/documentation/software-and-drivers/ez-pd-configuration-utility

Document Number: 001-98440 Rev. *F

Page 3 of 30

EZ-PD™ CCG4

Contents

Functional Overview ........................................................ 6

CPU and Memory Subsystem..................................... 6

USB-PD Subsystem (SS)............................................ 6

System Resources ...................................................... 7

Peripherals .................................................................. 7

GPIO ........................................................................... 8

Pinouts .............................................................................. 9

Power............................................................................... 14

Application Diagrams..................................................... 15

Electrical Specifications ................................................ 17

Absolute Maximum Ratings....................................... 17

Device-Level Specifications ...................................... 17

Digital Peripherals ..................................................... 20

Memory ..................................................................... 21

System Resources .................................................... 21

Ordering Information...................................................... 24

Ordering Code Definitions......................................... 24

Packaging........................................................................ 25

Acronyms........................................................................ 26

Document Conventions ................................................. 27

Units of Measure ....................................................... 27

References and Links To Applications Collaterals.... 28

Document History Page................................................. 29

Sales, Solutions, and Legal Information ...................... 30

Worldwide Sales and Design Support....................... 30

Products.................................................................... 30

PSoC® Solutions ...................................................... 30

Cypress Developer Community................................. 30

Technical Support .....................................................30

Document Number: 001-98440 Rev. *F

Page 4 of 30

EZ-PD™ CCG4

Figure 1. EZ-PD CCG4 Block Diagram

CPU Subsystem

CCG4

SWD/TC

Cortex

M0

48 MHz

FAST MUL

SPCIF

FLASH

128 KB

SRAM

8 KB

ROM

8 KB

32-bit

AHB-Lite

Read Accelerator

SRAM Controller

ROM Controller

NVIC, IRQMX

System Resources

Lite

System Interconnect (Single Layer AHB)

Peripheral Interconnect (MMIO)

Power

Sleep Control

WIC

Peripherals

POR

REF

PCLK

PWRSYS

Clock

Clock Control

WDT

2 x USB-PD 3.0

IMO

ILO

Reset

Reset Control

XRES

Test

DFT Logic

DFT Analog

Pads, ESD

Power Modes

Active/Sleep

Deep Sleep

High Speed I/O Matrix

27 x GPIOs, 2 OVTs

I/O Subsystem

Document Number: 001-98440 Rev. *F

Page 5 of 30

EZ-PD™ CCG4

Functional Overview

CPU and Memory Subsystem

CPU

USB-PD Subsystem (SS)

EZ-PD CCG4 has two USB-PD subsystems consisting of USB

Type-C baseband transceivers and physical-layer logic. These

transceivers perform the BMC and the 4b/5b encoding and

decoding functions as well as the 1.2-V analog front end. This

subsystem integrates the required termination resistors to

identify the role of the EZ-PD CCG4 solution. R_Dis used to

identify EZ-PD CCG4 as a UFP in a DRP application. When

configured as a DFP, integrated current sources perform the role

of R_Por pull-up resistors. These current sources can be

programmed to indicate the complete range of current capacity

on VBUS defined in the USB Type-C spec. EZ-PD CCG4

responds to all USB-PD communication.

The Cortex-M0 CPU in EZ-PD CCG4 is part of the 32-bit MCU

subsystem, which is optimized for low-power operation with

extensive clock gating. It mostly uses 16-bit instructions and

executes a subset of the Thumb-2 instruction set. This enables

fully compatible binary upward migration of the code to higher

performance processors such as the Cortex-M3 and M4, thus

enabling upward compatibility. The Cypress implementation

includes a hardware multiplier that provides a 32-bit result in one

cycle. It includes a nested vectored interrupt controller (NVIC)

block with 32 interrupt inputs and also includes a wakeup

interrupt controller (WIC). The WIC can wake the processor up

from the Deep Sleep mode, allowing power to be switched off to

the main processor when the chip is in the Deep Sleep mode.

The Cortex-M0 CPU provides a nonmaskable interrupt (NMI)

input, which is made available to the user when it is not in use

for system functions requested by the user.

The USB-PD sub-system contains two 8-bit SAR (successive

approximation register) ADCs for analog to digital conversions.

The ADCs include an 8-bit DAC and a comparator. The DAC

output forms the positive input of the comparator. The negative

input of the comparator is from a 4-input multiplexer. The four

inputs of the multiplexer are a pair of global analog multiplex

busses an internal bandgap voltage and an internal voltage

proportional to the absolute temperature. All GPIO inputs can be

connected to the global analog multiplex busses through a

switch at each GPIO that can enable that GPIO to be connected

to the mux bus for ADC use. The CC1 and CC2 pins of both

Type-C ports are not available to connect to the mux busses.

The CPU also includes a serial wire debug (SWD) interface,

which is a 2-wire form of JTAG. The debug configuration used for

EZ-PD CCG4 has four break-point (address) comparators and

two watchpoint (data) comparators.

Flash

The EZ-PD CCG4 device has a flash module with a flash

accelerator, tightly coupled to the CPU to improve average

access times from the flash block. The flash block is designed to

deliver two wait-states (WS) access time at 48 MHz and with

0-WS access time at 16 MHz. The flash accelerator delivers 85%

of single-cycle SRAM access performance on average. Part of

the flash module can be used to emulate EEPROM operation if

required.

To support the latest USB-PD 3.0 specification, CCG4 has

implemented the fast role swap feature. Fast Role Swap enables

externally powered docks and hubs to rapidly switch to bus

power when their external power supply is removed. For more

details, refer to Section 6.3.17 (FR_Swap Message) in the

USB-PD 3.0 specification.

CCG4 is designed to be fully interoperable with revision 3.0 of

the USB Power Delivery specification as well as revision 2.0 of

the USB Power Delivery specification.

SROM

A supervisory ROM that contains boot and configuration routines

is provided.

CCG4 supports Extended Messages containing data of up to 260

bytes. The Extended Messages will be larger than expected by

the USB-PD 2.0 hardware. To accommodate Revision 2.0 based

systems, a Chunking mechanism is implemented such that

Messages are limited to Revision 2.0 sizes unless it is

discovered that both systems support the longer Message

lengths.

Document Number: 001-98440 Rev. *F

Page 6 of 30

EZ-PD™ CCG4

Figure 2. USB-PD Subsystem

To/From System Resources

vref

iref

To/ from AHB

From AMUX

2 x 8-bit ADC

per Type-C port

VCONN FET Enable

TxRx Enable

V5V

VCONN

FETs

2 x Digital Baseband PHY

Tx_data

Enable Logic

from AHB

Tx

SRAM

4b5b

Encoder

BMC

Encoder

SOP

Insert

Rp

TX

CC1

RD1

CC2

CRC

Rx_data

to AHB

RX

Rx

4b5b

SOP

BMC

SRAM

Decoder

Detect

Decoder

Ref

DB

Rd

Comp

RD2

Active

Rd

CC control

CC detect

8kV IEC ESD

2 x Analog Baseband PHY

Deep Sleep Reference Enable

Functional, Wakeup Interrupts

Deep Sleep

Vref & Iref Gen

RD1 shorted to CC1 and RD2 shorted to CC2 for DRP applications using

bondwire. For DFP applications, RD1 and RD2 not shorted to CC1 and CC2.

Dead Battery (DB) Rd termination removed after MCU boots up

vref, iref

System Resources

Power System

Peripherals

Serial Communication Blocks (SCB)

The power system is described in detail in the section “Power”

on page 14. It provides the assurance that voltage levels are as

required for each respective mode and either delay mode entry

(on power-on reset (POR), for example) until voltage levels are

as required for proper function or generate resets (brown-out

detect (BOD)) or interrupts (low voltage detect (LVD)). EZ-PD

CCG4 can operate from three different power sources over the

range of 2.7 to 5.5 V and has three different power modes,

transitions between which are managed by the power system.

EZ-PD CCG4 provides Sleep and Deep Sleep low-power

modes.

EZ-PD CCG4 has four SCBs, which can be configured to

implement an I²C, SPI, or UART interface. The hardware I²C

blocks implement full multi-master and slave interfaces capable

of multimaster arbitration. In the SPI mode, the SCB blocks can

be configured to act as a master or a slave.

In the I²C mode, the SCB blocks are capable of operating at

speeds up to 1 Mbps (Fast Mode Plus) and have flexible

buffering options to reduce interrupt overhead and latency for the

CPU. These blocks also support I²C that creates a mailbox

address range in the memory of EZ-PD CCG4 and effectively

reduce I²C communication to reading from and writing to an

array in memory. In addition, the blocks support 8-deep FIFOs

for receive and transmit which, by increasing the time given for

the CPU to read data, greatly reduce the need for clock

stretching caused by the CPU not having read data on time.

Clock System

The clock system for EZ-PD CCG4 consists of the internal main

oscillator (IMO) and the internal low-power oscillator (ILO).

The I²C peripherals are compatible with the I²C Standard-mode,

Fast-mode, and Fast-mode Plus devices as defined in the NXP

I²C-bus specification and user manual (UM10204). The I²C bus

I/Os are implemented with GPIO in open-drain modes.

Document Number: 001-98440 Rev. *F

Page 7 of 30

EZ-PD™ CCG4

The I²C port on SCB 2, SCB 3 and SCB 4 blocks of EZ-PD CCG4

are not completely compliant with the I²C spec in the following:

GPIO

EZ-PD CCG4 has 30 GPIOs that includes the I²C and SWD pins,

which can also be used as GPIOs. The I²C pins from only

SCB 1 are overvoltage-tolerant. The number of available GPIOs

vary with the part numbers. The GPIO block implements the

following:

■ The GPIO cells for SCB 2 to SCB 4 I²C port are not

overvoltage-tolerant and, therefore, cannot be hot-swapped or

powered up independently of the rest of the I²C system.

■ Fast-mode Plus has an I_OLspecification of 20 mA at a V_OLof

0.4 V. The GPIO cells can sink a maximum of 8-mA I_OLwith a

■ Seven drive strength modes:

❐ Input only

V_OLmaximum of 0.6 V.

❐ Weak pull-up with strong pull-down

❐ Strong pull-up with weak pull-down

❐ Open drain with strong pull-down

❐ Open drain with strong pull-up

❐ Strong pull-up with strong pull-down

❐ Weak pull-up with weak pull-down

■ Fast-mode and Fast-mode Plus specify minimum Fall times,

which are not met with the GPIO cell; Slow strong mode can

help meet this spec depending on the bus load.

Timer/Counter/PWM Block (TCPWM)

EZ-PD CCG4 has up to four TCPWM blocks. Each implements

a 16-bit timer, counter, pulse-width modulator (PWM), and

quadrature decoder functionality. The block can be used to

measure the period and pulse width of an input signal (timer),

find the number of times a particular event occurs (counter),

generate PWM signals, or decode quadrature signals.

■ Input threshold select (CMOS or LVTTL)

■ Individual control of input and output buffer enabling/disabling

in addition to the drive strength modes

■ Hold mode for latching previous state (used for retaining I/O

state in Deep Sleep mode)

■ Selectable slew rates for dV/dt related noise control to improve

EMI

During power-on and reset, the I/O pins are forced to the disable

state so as not to crowbar any inputs and/or cause excess

turn-on current. A multiplexing network known as a high-speed

I/O matrix is used to multiplex between various signals that may

connect to an I/O pin.

Document Number: 001-98440 Rev. *F

Page 8 of 30

EZ-PD™ CCG4

Pinouts

Table 1. Pinout for CYPD4225-40LQXIT

Group

Pin Name

Pin Number

Description

CC1_P1

CC2_P1

CC1_P2

CC2_P2

9

7

USB PD connector detect/Configuration Channel 1

USB PD connector detect/Configuration Channel 2

USB PD connector detect/Configuration Channel 1

USB PD connector detect/Configuration Channel 2

USB Type-C Port 1

22

24

USB Type-C Port 2

Full rail control I/O for enabling/disabling Provider load FET of USB

Type-C port 1

VBUS_P_CTRL_P1

VBUS_C_CTRL_P1

VBUS_P_CTRL_P2

VBUS_C_CTRL_P2

VBUS_DISCHARGE_P1

11

12

39

38

20

Full rail control I/O for enabling/disabling Consumer load FET of USB

Type-C port 1/SCB1 (see Table 3 through Table 6 on page 12)

Full rail control I/O for enabling/disabling Provider load FET of USB

Type-C port 2

VBUS Control

Full rail control I/O for enabling/disabling Consumer load FET of USB

Type-C port 2

I/O used for discharging VBUS line during voltage change

VBUS_DISCHARGE_P2

VCONN_MON_P1/GPIO

40

19

I/O used for discharging VBUS line during voltage change

VCONN_MON_P1 (Monitor VCONN for UVP condition on port 1)/GPIO

VCONN Control

SCB3 (see Table 3 through Table 6) or VCONN_MON_P2(Monitor

VCONN for UVP condition on port 2)

SCL_3/VCONN_MON_P2

25

OVP_TRIP_P1

OVP_TRIP_P2

14

21

VBUS overvoltage output indicator for port 1 (active LOW)

VBUS overvoltage output indicator for port 2 (active LOW)

Overvoltage

Protection (OVP)

VBUS_MON_P1 (VBUS overvoltage protection monitoring

signal)/GPIO

VBUS_MON_P1/GPIO

13

HPD_P1/GPIO

HPD_P2/GPIO

18

30

HPD_P1 (Hot Plug Detect I/O for port 1)/GPIO

HPD_P2 (Hot Plug Detect I/O for port 2)/GPIO

MUX_CTRL_3_P2 (Mux control for port 2) or VBUS Overcurrent

Protection Input for port 2 (active LOW)

MUX_CTRL_3_P2/OCP_DET_P2

GPIO/MUX_CTRL_2_P2

34

35

36

MUX_CTRL_2_P2 (Mux control for port 2)/SCB4 (see Table 3 through

Table 6)

MUX_CTRL_1_P2 (Mux control for port 2)/SCB4 (see Table 3 through

Table 6)

GPIO/MUX_CTRL_1_P2

VBUS_MON_P2

VSEL_2_P2/GPIO

I2C_SCL_SCB1_EC

I2C_SDA_SCB1_EC

I2C_INT_EC

37

27

17

16

15

VBUS_MON_P2(VBUS overvoltage protection monitoring signal)

VSEL_2_P2(Voltage selection control for VBUS on port 2)/GPIO

SCB1/SCB4 (see Table 3 through Table 6)

SCB1/SCB3 (see Table 3 through Table 6)

I2C Interrupt line

GPIOs and Serial

Interfaces

SCB2 (see Table 3 through Table 6) or VSEL_1_P2 (Voltage selection

control for VBUS on port 2)

I2C_SCL_SCB2_AR/VSEL_1_P2

I2C_SDA_SCB2_AR/VSEL_1_P1

4

3

SCB1/SCB2 (see Table 3 through Table 6) or VSEL_1_P1 (Voltage

selection control for VBUS on port 1)

I2C interrupt line or VBUS Overcurrent Protection Input for port 1 (active

LOW)

I2C_INT_AR_P1/OCP_DET_P1

I2C_INT_AR_P2

5

6

I2C interrupt line/SCB1/SCB2 (see Table 3 through Table 6)

SCB3 (see Table 3 through Table 6) or MUX_CTRL_3_P1 (Mux control

for port 1) or VSEL_2_P1 (Voltage selection control for VBUS on port 1)

SDA_3/MUX_CTRL_3_P1/VSEL_2_P1

26

SCB4 (see Table 3 through Table 6)/MUX_CTRL_1_P1 (Mux control for

port 1)

SCL_4/MUX_CTRL_1_P1

29

Document Number: 001-98440 Rev. *F

Page 9 of 30

EZ-PD™ CCG4

Table 1. Pinout for CYPD4225-40LQXIT (continued)

Group

Pin Name

Pin Number

Description

SCB4 (see Table 3 through Table 6)/MUX_CTRL_2_P1 (Mux control for

port 1)

SDA_4/MUX_CTRL_2_P1

28

GPIOs and Serial

Interfaces

SWD_IO/AR_RST#

SWD_CLK/I2C_CFG_EC

XRES^[3]

1

2

SWD_IO (serial wire debug I/O)/SCB1. See Table 3 through Table 6.

SWD Clock/I2C_CFG_EC

Reset

10

8

Reset input (active LOW)

V5V_P1

2.7-V to 5.5-V supply for VCONN FET of Type-C port 1

2.7-V to 5.5-V supply for VCONN FET of Type-C port 2

1.71-V to 5.5-V supply for I/Os

V5V_P2

23

32

VDDIO

Power

1.8-V regulator output for filter capacitor. This pin cannot drive external

load.

VCCD

33

VDDD

VSS

31

VDDD supply input/output (2.7 V to 5.5 V)

Ground supply

EPAD

Figure 3. 40-Pin QFN Pin Map (Top View) for CYPD4225-40LQXIT

1

2

3

4

5

6

7

8

9

30

29

28

27

26

25

24

23

22

21

SWD_IO/AR_RST#

HPD_P2/GPIO

SWD_CLK/I2C_CFG_EC

SCL_4/MUX_CTRL_1_P1

SDA_4/MUX_CTRL_2_P1

VSEL_2_P2/GPIO

I2C_SDA_SCB2_AR/VSEL_1_P1

I2C_SCL_SCB2_AR/VSEL_1_P2

I2C_INT_AR_P1/OCP_DET_P1

I2C_INT_AR_P2

SDA_3/MUX_CTRL_3_P1/VSEL_2_P1

SCL_3/VCONN_MON_P2

CC2_P1

CC2_P2

V5V_P2

CC1_P2

V5V_P1

CC1_P1

XRES

OVP_TRIP_P2

10

Note

3. This is firmware configurable GPIO. By default, this pin is floating. Firmware can add pull-up/pull-down and enable/disable I/O buffers.

Document Number: 001-98440 Rev. *F

Page 10 of 30

EZ-PD™ CCG4

Table 2. Pinout for CYPD4125-40LQXIT

Group

Pin Name

Pin Number

Description

CC1_P1

CC2_P1

9

7

USB PD connector detect/Configuration Channel 1

USB PD connector detect/Configuration Channel 2

USB Type-C Port 1

Full rail control I/O for enabling/disabling. Provider load FET of USB

Type-C port 1.

VBUS_P_CTRL_P1

VBUS_C_CTRL_P1

11

12

Full rail control I/O for enabling/disabling. Consumer load FET of USB

Type-C port 1/SCB1 (see Table 3 through Table 6 on page 12).

VBUS Control

VBUS_DISCHARGE_P1

VCONN_MON_P1/GPIO

20

19

I/O used for discharging VBUS line during voltage change

VCONN Control

VCONN_MON_P1 (Monitor VCONN for OVP condition on port 1)/GPIO

Overvoltage

Protection (OVP)

OVP_TRIP_P1

GPIO

14

27

13

VBUS overvoltage output indicator for port 1 (active LOW)

SCB3 (see Table 3 through Table 6)/GPIO

VBUS_MON_P1 (VBUS overvoltage protection monitoring

signal)/GPIO

VBUS_MON_P1/GPIO

HPD_P1/GPIO

GPIO

18

21

30

34

35

36

37

38

39

40

17

16

15

4

HPD_P1 (Hot Plug Detect I/O for port 1)/GPIO

GPIO

GPIO/SCB4 (see Table 3 through Table 6)

GPIO

I2C_SCL_SCB1_EC

I2C_SDA_SCB1_EC

I2C_INT_EC

I2C_SCL_SCB2_AR

SCB1/SCB4 (see Table 3 through Table 6)

SCB1/SCB3 (see Table 3 through Table 6)

I2C interrupt line

GPIOs and Serial

Interfaces

SCB2 (see Table 3 through Table 6)

SCB1 or SCB2 (see Table 3 through Table 6) or voltage selection control

for VBUS on port 2

I2C_SDA_SCB2_AR/VSEL_1_P1

I2C_INT_AR_P1/OCP_DET_P1

3

5

I2C interrupt line or VBUS Overcurrent Protection Input for port 1 (Active

LOW)

GPIO

6

GPIO/SCB1/SCB2 (see Table 3 through Table 6)

GPIO/SCB3 (see Table 3 through Table 6)

SCL_3/GPIO

25

SCB3 (see Table 3 through Table 6) or MUX_CTRL_3_P1 (Mux control

for port 1), or Voltage selection control for VBUS on port 1

SDA_3/MUX_CTRL_3_P1/VSEL_2_P1

SCL_4/MUX_CTRL_1_P1

SDA_4/MUX_CTRL_2_P1

SWD_IO/AR_RST#

26

29

28

1

SCB3 (see Table 3 through Table 6) or MUX_CTRL_1_P1 (Mux control

for port 1)

SCB4 (see Table 3 through Table 6) or MUX_CTRL_2_P1 (Mux control

for port 1)

Serial wire debug I/O (SWD IO)/SCB1. See Table 3 through Table 6 or

Alpine Ridge Reset.

SWD_CLK/I2C_CFG_EC

XRES^[4]

2

SWD Clock/I2C_CFG_EC

Reset input (active LOW)

10

Reset

Note

4. This is firmware configurable GPIO. By default, this pin is floating. Firmware can add pull-up/pull-down and enable/disable IO buffers.

Document Number: 001-98440 Rev. *F

Page 11 of 30

EZ-PD™ CCG4

Table 2. Pinout for CYPD4125-40LQXIT (continued)

Group

Pin Name

Pin Number

Description

V5V_P1

VDDIO

8

2.7-V to 5.5-V supply for VCONN FET of Type-C port 1

1.71-V to 5.5-V supply for I/Os

32

1.8-V regulator output for filter capacitor. This pin cannot drive external

load.

VCCD

33

Power

VDDD

VSS

NC

31

EPAD

22

VDDD supply I/O (2.7 V to 5.5 V)

Ground supply

NC

23

These pins are not bonded

No Connect

NC

24

Table 3. Serial Communication Block (SCB1) Configuration

UART

SPI Master

SPI Slave

I2C Master

I2C Slave

12

UART_TX_SCB1

SPI_MOSI_SCB1

VBUS_C_CTRL_P1

VSEL_2_P1/

VCONN_MON_P1

VSEL_2_P1/

VCONN_MON_P1

14

UART_RX_SCB1

SPI_CLK_SCB1

17

16

UART_RTS_SCB1

UART_CTS_SCB1

SPI_MISO_SCB1

SPI_SEL_SCB1

SPI_MISO_SCB1

SPI_SEL_SCB1

I2C_SDA_SCB1

I2C_SCL_SCB1

I2C_SDA_SCB1

I2C_SCL_SCB1

Table 4. Serial Communication Block (SCB2) Configuration

4

UART

SPI Master

SPI_CLK_SCB2

SPI_MISO_SCB2

SPI_SEL_SCB2

SPI_MOSI_SCB2

SPI Slave

SPI_CLK_SCB2

SPI_MISO_SCB2

SPI_SEL_SCB2

SPI_MOSI_SCB2

I2C Master

I2C_SCL_SCB2

I2C_SDA_SCB2

GPIO

I2C Slave

I2C_SCL_SCB2

I2C_SDA_SCB2

GPIO

UART_TX_SCB2

UART_RX_SCB2

UART_RTS_SCB2

UART_CTS_SCB2

3

6

1

SWD_IO

Table 5. Serial Communication Block (SCB3) Configuration

26

25

16

21

UART

SPI Master

SPI_MISO_SCB3

SPI_MOSI_SCB3

SPI_SEL_SCB3

SPI_CLK_SCB3

SPI Slave

SPI_MISO_SCB2

SPI_MOSI_SCB3

SPI_SEL_SCB3

SPI_CLK_SCB3

I2C Master

I2C_SDA_SCB3

I2C_SCL_SCB3

I2C_SCL_SCB1

AR_RST#

I2C Slave

I2C_SDA_SCB3

I2C_SCL_SCB3

I2C_SCL_SCB1

AR_RST#

UART_TX_SCB3

UART_RX_SCB3

UART_RTS_SCB3

UART_CTS_SCB3

Table 6. Serial Communication Block (SCB4) Configuration

28

29

36

35

UART

SPI Master

SPI_MOSI_SCB4

SPI_MISO_SCB4

SPI_SEL_SCB4

SPI_CLK_SCB4

SPI Slave

SPI_MOSI_SCB4

SPI_MISO_SCB4

SPI_SEL_SCB4

SPI_CLK_SCB4

I2C Master

I2C_SDA_SCB4

I2C_SCL_SCB4

GPIO

I2C Slave

I2C_SDA_SCB4

I2C_SCL_SCB4

GPIO

UART_TX_SCB4

UART_RX_SCB4

UART_RTS_SCB4

UART_CTS_SCB4

GPIO

Document Number: 001-98440 Rev. *F

Page 12 of 30

EZ-PD™ CCG4

Figure 4. 40-Pin QFN Pin Map (Top View) for CYPD4125-40LQXIT

1

2

3

4

5

6

7

8

9

30

29

28

27

26

25

24

23

22

21

SWD_IO/AR_RST#

SWD_CLK/I2C_CFG_EC

GPIO

SCL_4/MUX_CTRL_1_P1

SDA_4/MUX_CTRL_2_P1

GPIO

I2C_SDA_SCB2_AR/VSEL_1_P1

I2C_SCL_SCB2_AR

SDA_3/MUX_CTRL_3_P1/VSEL_2_P1

SCL_3

I2C_INT_AR_P1/OCP_DET_P1

GPIO

CC2_P1

V5V_P1

CC1_P1

XRES

NC

GPIO

10

Document Number: 001-98440 Rev. *F

Page 13 of 30

EZ-PD™ CCG4

A separate I/O supply pin, VDDIO, allows the GPIOs to operate

at levels from 1.71 V to 5.5 V. The VDDIO pin can be equal to or

less than the voltages connected to the V5V_P1 or V5V_P2 and

VDDD pins. The VDDIO supply should be less than or equal to

VDDD supply.

Power

The following power system diagram shows the set of power

supply pins as implemented in EZ-PD CCG4.

CCG4 shall be able to operate from three possible external

supply sources: V5V_P1 for first Type-C port, V5V_P2 for

second Type- C port and VDDD.

The VCCD output of EZ-PD CCG4 must be bypassed to ground

via an external capacitor (in the range of 80 to 120 nF; X5R

ceramic or better).

CCG4 has the power supply input V5V_P1 and V5V_P2 pins for

providing power to EMCA cables through integrated VCONN

FETs. There are two VCONN FETs in CCG4 per Type-C port to

power either CC1 or CC2 pin. These FETs are capable of

providing a minimum of 1W on the CC1 and CC2 pins for the

EMCA cables. In USB-PD applications, the valid levels on

V5V_P1 and V5V_P2 supplies can range from 4.85 V to 5.5 V.

Bypass capacitors must be used from VDDD and V5V_P1 or

V5V_P2 pins to ground; typical practice for systems in this

frequency range is to use a 0.1-µF capacitor on VDDD, V5V_P1

and V5V_P2. Note that these are simply rules of thumb and that

for critical applications, the PCB layout, lead inductance, and the

bypass capacitor parasitic should be simulated to design and

obtain optimal bypassing.

The chip’s internal operating power supply is derived from

VDDD. In UFP mode, CCG4 operates in 2.7 V – 5.5V. In DFP

and DRP modes, it operates in the 3.0 V – 5.5 V range.

Figure 5 shows an example of the power supply bypass

capacitors.

Figure 5. EZ-PD CCG4 Power and Bypass Scheme Example

[6]

CC1_P2

CC2_P2^[7]

[5]

V5V_P2

CC1_P1

CC2_P1

V_DDD

V5V_P1

V_DDIO

Core Regulator

(SRSS-Lite)

V_CCD

2 x CC

Tx/Rx

GPIOs

Core

V_SS

Note

5. V5V_P1 denoted power supply input for Type-C port 1

V5V_P2 denoted power supply input for Type-C port 2

6. CC1_1:USB PD connector detect/Configuration Channel 1 for Type-C port 1

CC1_2:USB PD connector detect/Configuration Channel 1 for Type-C port 2

7. CC2_1:USB PD connector detect/Configuration Channel 2 for Type-C port 1

CC2_2:USB PD connector detect/Configuration Channel 2 for Type-C port 2

Document Number: 001-98440 Rev. *F

Page 14 of 30

EZ-PD™ CCG4

For the dual Type-C notebook application, these Type-C ports

can be power providers or power consumers simultaneously. In

addition, the CCG4 device controls the transfer of DisplayPort

signals over the Type-C interface using the display mux

controllers.

Application Diagrams

Figure 6 and Figure 7 show a dual Type-C port and a single

Type-C port Notebook DRP application diagram using a CCG4

device. The Type-C port can be used as a power provider or a

power consumer.

Optional FETs are provided for applications that need to provide

power for accessories and cables using VCONN pin of the

Type-C receptacle. VBUS FETs are also used for providing

power over VBUS and for consuming power over VBUS. A

VBUS_DISCHARGE FET controlled by CCG4 device is used to

quickly discharge VBUS after the Type-C connection is

detached.

In each of these applications, CCG4 communicates with the

Embedded Controller (EC), which manages the Battery Charger

Controller (BCC) to control the charging and discharging of

internal battery. It also controls the Data Mux to route the

HighSpeed signals either to the USB chipset (during normal

mode) or the DisplayPort Chipset (during Alternate Mode).The

SBU, SuperSpeed, and HighSpeed lines are routed directly from

the Display Mux of the notebook to the Type-C receptacle.

Figure 6. CCG4 in a Dual Port Notebook Application using CYPD4225-40LQXIT

2

HS

USB 3.0

HOST

4

SSTX/RX

TX

4

2

RX

MUX

4

ML_LANE_[0:3]N

SBU

ML_LANE_[0:3]P

AUX P/N

DISPLAY PORT

CONTROLLER 1

2

HPD_P1

I2C_SCL I2C_SDA

VBUS_SINK

49.9KO

4.7 uF

100 KO

2

100 KO

10

O

VBUS_C_CTRL_P1

100 KO

2

VBUS_SOURCE

VBUS

OPTIONAL VDDIO SUPPLY. CAN SHORT

TO VDDD IN SINGLE SUPPLY SYSTEMS.

49.9KO

100 KO

4.7 uF

5.0V

3.3V VDDIO

100 KO

10

O

VBUS_P_CTRL_P1

100 KO

1µF

SWD_IO/AR_RST#

1µF

0.1µF

1

2

18

30

SWD_CLK/I2C_CFG_EC

200

O

TYPE-C

RECEPTACLE 1

TO DISPLAY_PORT

CONTROLLER 1

10

O

HPD_P1

HPD_P2

VBUS_DISCHARGE_P1

100 KO

VBUS

100 KO

HPD_P1/GPIO

TO DISPLAY PORT

HPD_P2/GPIO

13 VBUS_MON_P1

10 KO

VBUS_MON_P1/GPIO

CONTROLLER

2

0.1µF

19

VCONN_MON_P1/GPIO

7

9

14

27

CC2

CC1

OVP_TRIP_P1

CC2_P1

CC1_P1

VSEL_2_P2

VSEL_2_P2/GPIO

DC/DC

OR

AC-DC

SECONDARY

(5-20V)

VDDIO

11 VBUS_P_CTRL_P1

330pF

CHARGER

VBUS_P_CTRL_P1

100 KO

0.1µF

10

21

15

VBUS_DISCHARGE_P1

20

XRES

GND

VBUS_DISCHARGE_P1

2.2 KO

12 VBUS_C_CTRL_P1

34

OVP_TRIP_P2

2.2 KO

VBUS_C_CTRL_P1

CCG4

2.2 KO

EMBEDDED

CONTROLLER

(CYPD4225-40LQXIT)

I2C_INT_EC

40-QFN ^{MUX_CTRL_3_P2/GPIO}

17

16

I2C_SCL_SCB1_EC

I2C_SDA_SCB1_EC

35

36

MUX_CTRL_2_P2/GPIO

VSEL_1_P2

VSEL_1_P1

4

3

MUX_CTRL_1_P2/GPIO

I2C_SCL_SCB2_AR/VSEL_1_P2

VBUS_C_CTRL_P2

38

VBUS_C_CTRL_P2/

I2C_SDA_SCB2_AR/VSEL_1_P1

I2C_INT_AR_P1

5

6

VBUS_P_CTRL_P2

39

VBUS_P_CTRL_P2

VBUS_DISCHARGE_P2

CC2_P2

I2C_INT_AR_P2

VBUS_DISCHARGE_P2

40

24

VDDIO

2.2 KO

25

SCL_3/VCONN_MON_P2/GPIO

CC2

VSEL_2_P1

I2C_SCL

26

29

SDA_3/MUX_CTRL_3_P1/VSEL_2_P1

SCL_4/MUX_CTRL_1_P1/GPIO

22

I2C MASTER

FOR ALT

CC1_P2

CC1

VBUS

TYPE-C

RECEPTACLE 2

I2C_SDA

28

330pF

MODE MUX

CONTROL

CONNECTED

TO TYPE-C

PORT1 or

SDA_4/MUX_CTRL_2_P1/GPIO

VSS

100 KO

37 VBUS_MON_P2

EPAD

VBUS_MON_P2

0.1µF

10 KO

PORT2

VBUS_SINK

VBUS

49.9KO

100 KO

2

4.7 uF

2

10

O

VBUS_P_CTRL_P2

100 KO

VBUS (5-20V)

VBUS_SOURCE

49.9KO

100 KO

4.7 uF

10

O

VBUS_P_CTRL_P2

100 KO

200

O

10

VBUS_DISCHARGE_P2

100 KO

2

4

HS

USB 3.0

HOST

SSTX/RX

TX

4

2

RX

MUX

4

2

ML_LANE_[0:3]N

SBU

ML_LANE_[0:3]P

AUX P/N

DISPLAY PORT

CONTROLLER 2

HPD_P2

I2C_SCL I2C_SDA

Document Number: 001-98440 Rev. *F

Page 15 of 30

EZ-PD™ CCG4

Figure 7. CCG4 in a Single Port Notebook Application using CYPD4125-40LQXIT

HS

2

USB 3.0

HOST

4

SSTX/RX

TX

4

RX

2

MUX

SBU

4

ML_LANE_[0:3]N

ML_LANE_[0:3]P

AUX P/N

DISPLAY PORT

CONTROLLER 1

2

HPD_P1

VBUS_SINK

I2C_SCL

I2C_SDA

CHARGER

49.9KO

10 O

2

4.7 uF

100 KO

VBUS_C_CTRL_P1

100 KO

2

VBUS (5-20V)

DC/DC

OR

AC-DC

VSEL_2_P1

VSEL_1_P1

VBUS_SOURCE

VBUS

SECONDARY

(5-20V)

OPTIONAL VDDIO SUPPLY. CAN SHORT

TO VDDD IN SINGLE SUPPLY SYSTEMS.

49.9KO

4.7 uF

100 KO

5.0V

3.3V VDDIO

100 KO

10 O

VBUS_P_CTRL_P1

100 KO

1µF

0.1µF

1

200O

SWD_IO/AR_RST#

VBUS_DISCHARGE_P1 10 O

100 KO

2

SWD_CLK/I2C_CFG_EC

HPD_P1/GPIO

TO DISPLAY_PORT

CONTROLLER 1

TYPE-C

RECEPTACLE 1

HPD_P1

18

VBUS

100 KO

13 VBUS_MON_P1

VBUS_MON_P1/GPIO

0.1µF

19

14

10 KO

VCONN_MON__P1/GPIO

OVP_TRIP_P1

7

9

CC2

CC1

CC2_P1

CC1_P1

VDDIO

11 VBUS_P_CTRL_P1

330pF

VBUS_P_CTRL_P1

100 KO

0.1µF

10

21

15

VBUS_DISCHARGE_P1

20

XRES

GPIO

VBUS_DISCHARGE_P1

GND

2.2 KO

12 VBUS_C_CTRL_P1

2.2 KO

VBUS_C_CTRL_P1

CCG4

2.2 KO

EMBEDDED

CONTROLLER

(CYPD4125-40LQXIT)

40-QFN

I2C_INT_EC

27

30

GPIO

17

16

I2C_SCL_SCB1_EC

I2C_SDA_SCB1_EC

34

35

4

3

GPIO

I2C_SCL_SCB2_AR

VSEL_1_P1

I2C_SDA_SCB2_AR/VSEL_1_P1

I2C_INT_AR_P1

5

6

VDDIO

36

GPIO

37

38

39

40

24

22

25

2.2 KO

VSEL_2_P1

SCL_3

GPIO

2.2 KO

26

29

SDA_3/MUX_CTRL_3_P1/VSEL_2_P1

SCL_4/MUX_CTRL_1_P1

I2C_SCL

I2C MASTER FOR ALT MODE

GPIO

NC

MUX CONTROL CONNECTED TO I2C_SDA

TYPE-C PORT1

28

SDA_4/MUX_CTRL_2_P1

VSS

EPAD

NC

Document Number: 001-98440 Rev. *F

Page 16 of 30

EZ-PD™ CCG4

Electrical Specifications

Absolute Maximum Ratings

Table 7. Absolute Maximum Ratings^[8]

Parameter

V_{DDD_MAX}

Description

Min

–0.5

–

Typ

–

Max

Units

V

Details/Conditions

Absolute max

Absolute Max

Absolute max

Digital supply relative to V_SS

Max supply voltage relative to V_SS

GPIO voltage

6

V5V_P1

–

6

V

V5V_P2

–

6

V

V_{DDIO_MAX}

V_{GPIO_ABS}

I_{GPIO_ABS}

–

6

V_DDIO+ 0.5

25

V

–0.5

–25

–

V

Maximum current per GPIO

–

mA

GPIO injection current, Max for V_IH

> V_DDD, and Min for V_IL< V_SS

Absolute max, current

injected per pin

I_{GPIO_injection}

ESD_HBM

–0.5

–

0.5

–

mA

V

Electrostatic discharge human

body model

2200

–

Electrostatic discharge charged

device model

ESD_CDM

LU

500

–200

8000

–

200

–

V

mA

V

–

Pin current for latch-up

Electrostatic discharge

IEC61000-4-2

Contact discharge on

CC1, CC2 pins

ESD_IEC_CON

Electrostatic discharge

IEC61000-4-2

Air discharge for pins

CC1, CC2

ESD_IEC_AIR

15000

–

V

Device-Level Specifications

All specifications are valid for –40 °C  TA  85 °C and TJ  100 °C, except where noted. Specifications are valid for 3.0 V to 5.5 V,

except where noted.

Table 8. DC Specifications

Spec ID

Parameter

Description

Power supply input voltage

Min

2.7

3.0

Typ Max Units

Details/Conditions

UFP applications

SID.PWR#1

V_DDD

–

5.5

V

SID.PWR#1_A V_DDD

DFP/DRP applications

V5V_P1,

SID.PWR#26

Power supply input voltage

4.85

–

5.5

V

–

V5V_P2

V_DDIO

V_CCD

PWR#13

GPIO power supply

1.71

–

5.5

–

V

–

SID.PWR#24

Output voltage (for core logic)

1.8

External regulator voltage bypass

on V_CCD

SID.PWR#15

SID.PWR#16

SID.PWR#27

C_EFC

C_EXC

C_EXV

80

0.8

–

100

1

120

–

nF

µF

X5R ceramic or better

Power supply decoupling capacitor

on V_DDD

Power supply decoupling capacitor

on V5V_P1 and V5V_P2

0.1

–

Active Mode, V_DDD= 2.7 to 5.5 V. Typical values measured at V_DD= 3.3 V.

V5V_P1 and V5V_P2 = 5 V,

T_A= 25 °C,

mA CC I/O IN Transmit or Receive,

no I/O sourcing current, CPU at

24 MHz, two PD ports active

SID.PWR#4

I_DD12

Supply current

–

10

–

Note

8. Usage above the absolute maximum conditions listed in Table 7 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended

periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature

Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification.

Document Number: 001-98440 Rev. *F

Page 17 of 30

EZ-PD™ CCG4

Table 8. DC Specifications (continued)

Spec ID Parameter

Sleep Mode, V_DDD= 2.7 to 5.5 V

I²C wakeup

Description

Min

Typ Max Units

Details/Conditions

V_DDD= 3.3 V, T_A= 25 °C, all

SID25A

I_DD20A

WDT ON

IMO at 48 MHz

–

2.5

4.0

mA blocks except CPU are ON, CC

I/O ON, no I/O sourcing current

Deep Sleep Mode, V_DDD= 2.7 to 3.6 V (Regulator on)

V_DDD= 2.7 to 3.6 V

SID34

I_DD29

–

80

–

µA

V_DDD= 3.3 V, T_A= 25 °C

I²C wakeup and WDT ON

Power source = V_DDD, Type-C

not attached, CC enabled for

wakeup, R_Pdisabled

V_DDD= 2.7 to 3.6 V

CC wakeup ON

SID_DS

I_{DD_DS}

2.5

Power source = V_DDD, Type-C

not attached, CC enabled for

wakeup, R_Pand R_Dconnected

at 70 ms intervals by CPU. R_P,

R_Dconnection should be

V_DDD= 2.7 to 3.6 V

CC wakeup ON

SID_DS1

I_{DD_DS1}

–

100

–

µA

enabled for both PD ports.

XRES Current

Supply current while XRES

asserted

SID307

I_{DD_XR}

1

10

µA

–

Table 9. AC Specifications

Spec ID

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

SID.CLK#4

F_CPU

CPU frequency

DC

–

48

MHz 3.0 V V_DDD5.5 V

Guaranteed by

µs

SID.PWR#20

SID.PWR#21

SID.XRES#5

SYS.FES#1

I/O

T_SLEEP

Wakeup from sleep mode

–

0

–

35

–

characterization

24-MHz IMO. Guaranteed by

characterization.

T_DEEPSLEEPWakeup from Deep Sleep mode

–

5

–

5

µs

Guaranteed by

characterization

T_XRES

External reset pulse width

Power-up to “Ready to accept

I2C / CC command”

Guaranteed by

characterization

T_{_PWR_RDY}

25

ms

Table 10. I/O DC Specifications

Spec ID

SID.GIO#37

SID.GIO#38

SID.GIO#39

SID.GIO#40

SID.GIO#41

SID.GIO#42

SID.GIO#33

SID.GIO#34

SID.GIO#35

SID.GIO#36

Parameter

Description

Min

Typ

–

Max

Units

Details/Conditions

[9]

V_IH

Input voltage HIGH threshold 0.7 × V_DDIO

–

V

CMOS input

V_IL

V_IH

V_IL

V_IH

V_IL

Input voltage LOW threshold

LVTTL input, V_DDIO< 2.7 V

LVTTL input, V_DDIO 2.7 V

Output voltage HIGH level

Output voltage LOW level

–

0.3 × V_DDIO

[9]

0.7× V_DDIO

–

0.3 × V_DDIO

2.0

–

0.8

–

V_OH

V_OL

V_DDIO–0.6

–

I_OH= 4 mA at 3-V V_DDIO

I_OH= 1 mA at 1.8-V V_DDIO

I_OL= 4 mA at 1.8-V V_DDIO

I_OL= 8 mA at 3 V V_DDIO

V_DDIO–0.5

–

0.6

–

Note

9. V_IHmust not exceed V_DDIO+ 0.2 V.

Document Number: 001-98440 Rev. *F

Page 18 of 30

EZ-PD™ CCG4

Table 10. I/O DC Specifications (continued)

Spec ID

SID.GIO#5

SID.GIO#6

Parameter

Description

Pull-up resistor

Min

3.5

Typ

5.6

Max

8.5

Units

kΩ

Details/Conditions

R_PULLUP

–

R_PULLDOWNPull-down resistor

8.5

kΩ

Input leakage current

(absolute value)

SID.GIO#16

SID.GIO#17

SID.GIO#43

I_IL

–

2

7

–

nA 25 °C, V_DDIO= 3.0 V

C_IN

Input capacitance

pF

–

V_DDIO 2.7 V. Guaranteed

by characterization.

V_HYSTTL

Input hysteresis LVTTL

25

40

mV

Guaranteed by

characterization

SID.GPIO#44 V_HYSCMOS

Input hysteresis CMOS

0.05 × V_DDIO

–

mV

µA

Current through protection

diode to V_DDIO/Vss

Guaranteed by

characterization

SID69

I_DIODE

–

100

200

Maximum total source or sink

chip current

Guaranteed by

characterization

SID.GIO#45

I_{TOT_GPIO}

mA

Table 11. I/O AC Specifications

(Guaranteed by Characterization)

Spec ID

SID70

Parameter

T_RISEF

Description

Rise time

Fall time

Min

2

Typ

–

Max

Units

Details/Conditions

12

ns

3.3-V V_DDIO, Cload = 25 pF

SID71

T_FALLF

2

–

XRES

Table 12. XRES DC Specifications

Spec ID

SID.XRES#1

SID.XRES#2

SID.XRES#3

Parameter

Description

Min

Typ

–

Max

Units

V

Details/Conditions

CMOS input

–

V_IH

V_IL

C_IN

Input voltage HIGH threshold 0.7 × V_DDIO

–

Input voltage LOW threshold

Input capacitance

–

0.3 × V_DDIO

7

V

–

pF

Guaranteed by

characterization

SID.XRES#4

V_HYSXRES

Input voltage hysteresis

–

0.05 × V_DDIOmV

Document Number: 001-98440 Rev. *F

Page 19 of 30

EZ-PD™ CCG4

Digital Peripherals

The following specifications apply to the Timer/Counter/PWM peripherals in the Timer mode.

Pulse Width Modulation (PWM) for GPIO Pins

Table 13. PWM AC Specifications

(Guaranteed by Characterization)

Spec ID

SID.TCPWM.3

SID.TCPWM.4

Parameter

Description

Min Typ Max Units

Details/Conditions

T_CPWMFREQOperating frequency

–

Fc

–

MHz Fc max = CLK_SYS. Maximum = 48 MHz

ns For all trigger events

T_PWMENEXTInput trigger pulse width

2/Fc

Minimum possible width of Overflow,

ns Underflow, and CC (Counter equals

Compare value) outputs

SID.TCPWM.5

T_PWMEXT

Output trigger pulse width

–

2/Fc

–

Minimum time between successive

counts

SID.TCPWM.5A T_CRES

SID.TCPWM.5B PWM_RES

SID.TCPWM.5C Q_RES

Resolution of counter

PWM resolution

–

1/Fc

–

ns

ns Minimum pulse width of PWM output

Minimum pulse width between

quadrature-phase inputs

Quadrature inputs resolution

ns

I²C

Table 14. Fixed I²C AC Specifications

(Guaranteed by Characterization)

Spec ID

SID153

Parameter

F_I2C1

Description

Min

Typ Max Units

Details/Conditions

Bit rate

–

1

Mbps

–

Table 15. Fixed UART AC Specifications

(Guaranteed by Characterization)

Spec ID

SID162

Parameter

Description

Min

Typ

Max Units

Mbps

Details/Conditions

F_UART

Bit rate

–

1

–

Table 16. Fixed SPI AC Specifications

(Guaranteed by Characterization)

Spec ID

Parameter

Description

Min

Typ

Max Units

MHz

Details/Conditions

SPI operating frequency

(Master; 6X oversampling)

SID166

F_SPI

–

8

–

Table 17. Fixed SPI Master Mode AC Specifications

(Guaranteed by Characterization)

Spec ID

Parameter

Description

Min

Typ

Max Units

Details / Conditions

MOSI valid after SClock

driving edge

SID167

T_DMO

–

15

–

ns

–

MISO valid before SClock

capturing edge

SID168

SID169

T_DSI

20

0

–

ns Full clock, late MISO sampling

ns Referred to Slave capturing edge

Previous MOSI data hold

time

T_HMO

–

Document Number: 001-98440 Rev. *F

Page 20 of 30

EZ-PD™ CCG4

Table 18. Fixed SPI Slave Mode AC Specifications

(Guaranteed by Characterization)

Spec ID

Parameter

Description

Min

Typ

Max

Units Details / Conditions

MOSI valid before Sclock

capturing edge

SID170

T_DMI

40

–

ns

–

MISO valid after Sclock driving

edge

48 + 3 *

T_SCB

T_SCB= T_CPU

1/24 MHz

=

SID171

T_DSO

–

MISO valid after Sclock driving

edge in Ext Clk mode

SID171A

T_{DSO_EXT}

–

0

48

–

SID172

T_HSO

Previous MISO data hold time

–

ns

–

SID172A

T_SSELSCK

SSEL valid to first SCK valid edge 100

Memory

Table 19. Flash AC Specifications

Spec ID

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

Row (block) write time (erase and

program)

[10]

SID.MEM#4 T_ROWWRITE

–

20

ms

–

[10]

SID.MEM#3 T_ROWERASE

Row erase time

–

13

7

ms

–

[10]

SID.MEM#8 T_ROWPROGRAM

Row program time after erase

Bulk erase time (128 KB)

[10]

SID178

T_BULKERASE

35

Guaranteed by

characterization

[10]

SID180

T_DEVPROG

Total device program time

Flash endurance

–

100 K

20

–

25

–

seconds

cycles

years

Guaranteed by

characterization

SID.MEM#6 F_END

Flash retention. T_A 55 °C, 100 K

P/E cycles

Guaranteed by

characterization

SID182

F_RET1

F_RET2

–

Flash retention. T_A 85 °C, 10 K

P/E cycles

Guaranteed by

characterization

SID182A

10

–

years

System Resources

Power-on-Reset (POR) with Brown Out

Table 20. Imprecise Power On Reset (PRES)

Spec ID

SID185

Parameter

V_RISEIPOR

Description

Rising trip voltage

Min

Typ

Max

Units

Details/Conditions

Guaranteed by

characterization

0.80

–

1.50

1.4

V

Guaranteed by

characterization

SID186

V_FALLIPOR

Falling trip voltage

0.75

–

V

Table 21. Precise Power On Reset (POR)

Spec ID Parameter

SID190 V_FALLPPOR

Description

Min

Typ

Max

Units

Details/Conditions

BOD trip voltage in active and

sleep modes

Guaranteed by

characterization

1.48

–

1.62

V

Guaranteed by

characterization

SID192

V_FALLDPSLP

BOD trip voltage in Deep Sleep

1.1

–

1.5

V

Note

10. It can take as much as 20 milliseconds to write to flash. During this time the device should not be reset, or flash operations will be interrupted and cannot be relied

on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.

Make certain that these are not inadvertently activated.

Document Number: 001-98440 Rev. *F

Page 21 of 30

EZ-PD™ CCG4

SWD Interface

Table 22. SWD Interface Specifications

Spec ID

Parameter

Description

Min

Typ

–

Max

Units

Details/Conditions

SID.SWD#1 F_SWDCLK1

SID.SWD#2 F_SWDCLK2

3.3 V  V_DDIO 5.5 V

1.8 V  V_DDIO 3.3 V

–

14

MHz SWDCLK ≤ 1/3 CPU clock frequency

–

0.25 * T

–

7

SID.SWD#3 T_SWDI_SETUP T = 1/f SWDCLK

SID.SWD#4 T_SWDI_HOLD T = 1/f SWDCLK

–

ns

Guaranteed by characterization

–

SID.SWD#5 T_SWDO_VALID T = 1/f SWDCLK

SID.SWD#6 T_SWDO_HOLD T = 1/f SWDCLK

–

0.5*T

–

1

–

Internal Main Oscillator

Table 23. IMO AC Specifications

Spec ID

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

Frequency variation at 24, 36,

and 48 MHz (trimmed)

SID.CLK#13 F_IMOTOL

–

±2

%

–

SID226

SID229

F_IMO

T_STARTIMO

T_JITRMSIMO

–

IMO startup time

RMS jitter at 48 MHz

IMO frequency

–

145

–

7

–

µs

ps

–

24

48

MHz

Internal Low-Speed Oscillator

Table 24. ILO AC Specifications

Spec ID

SID234

Parameter

T_STARTILO

Description

Min

Typ

Max

Units

Details/Conditions

Guaranteed by

characterization

ILO startup time

–

2

ms

Guaranteed by

characterization

SID236

T_ILODUTY

ILO duty cycle

ILO Frequency

40

20

50

40

60

80

%

SID.CLK#5 F_ILO

kHz

–

Document Number: 001-98440 Rev. *F

Page 22 of 30

EZ-PD™ CCG4

Power Down

Table 25. PD DC Specifications

Spec ID

Parameter

Description

Min Typ Max Units

Details/Conditions

DFP CC termination for default USB

Power

SID.PD.1 Rp_std

64

80

96

µA

–

SID.PD.2 Rp_1.5A

SID.PD.3 Rp_3.0A

SID.PD.4 Rd

DFP CC termination for 1.5A power

DFP CC termination for 3.0A power

UFP CC termination

166 180 194

304 330 356

µA

–

4.59 5.1 5.61 kꢀ

–

All supplies forced to 0 V and 1.0 V

4.08 5.1 6.12 kꢀ applied at CC1 or CC2. Applicable

UFP Dead Battery CC termination on

CC1 and CC2

SID.PD.5 Rd_DB

for DRP applications only.

Voltage drop from V5V_P1 and

V5V_P2 pins to CC1 pin while

sourcing 215 mA.

SID.PD.15 Vdrop_V5V_CC1 CC1 and CC2 pins of Port1 and Port2

–

100 mV

–

are not short circuit protected.

Max allowed sourcing current is

500 mA.

Voltage drop from V5V_P1 and

V5V_P2 pins to CC2 pin while

sourcing 215 mA

SID.PD.16 Vdrop_V5V_CC2 CC1 and CC2 pins of Port1 and Port2

are not short circuit protected.

100 mV

Max allowed sourcing current is

500 mA.

Analog to Digital Converter

Table 26. ADC DC Specifications

Spec ID

SID.ADC.1

SID.ADC.2

SID.ADC.3

SID.ADC.4

Parameter

Resolution

INL

Description

ADC resolution

Min Typ Max Units

Details/Conditions

–

8

–

bits

LSB

–

Integral nonlinearity

Differential nonlinearity

Gain error

–1.5

–2.5

–1.0

1.5

2.5

1.0

DNL

Gain Error

Table 27. ADC AC Specifications

Spec ID

Parameter

Description

Min Typ Max Units

V/ms

Details/Conditions

Rate of change of sampled voltage

signal

SID.ADC.5

SLEW_Max

–

3

–

Document Number: 001-98440 Rev. *F

Page 23 of 30

EZ-PD™ CCG4

Ordering Information

The EZ-PD CCG4 part numbers and features are listed in Table 28.

Table 28. EZ-PD CCG4 Ordering Information

Type-C

Ports

PD

Dead Battery Termination

Resistor

Part Number

Application

TCPWM

Role

Package

Spec# Termination

[11]

[12]

CYPD4125-40LQXIT Notebooks, docking station

CYPD4225-40LQXIT Notebooks, docking station

CYPD4126-40LQXIT Notebooks, docking station

CYPD4226-40LQXIT Notebooks, docking station

CYPD4136-40LQXIT Power adapter

1

2

1

2

1

2

4

2

PD2.0

PD3.0

Yes

No

RP , RD

DRP

DFP

40-pin QFN

[11]

[12]

RP , RD

[11]

RP , RD

[11]

RP , RD

[11]

RP

[11]

CYPD4236-40LQXIT Power adapter

No

RP

Ordering Code Definitions

0

X

XX XX

X

I

T

4

PD

CY

-

1/2

T = Tape and Reel

Temperature Grade:

I = Industrial

Pb-free

Package Type: XX = FN, LH or LQ

FN = CSP; LH = DFN; LQ = QFN

Number of pins in the package: XX = 14, 20, or 40

Device Role: Unique combination of role and termination:

X = 2 or 3 or 4 or 5

Feature: Unique Applications

Number of Type-C Ports: 1 = 1 Port, 2 = 2 Ports

Product Type: 4 = Fourth-generation product family, CCG4

Marketing Code: PD = Power Delivery product family

Company ID: CY = Cypress

Notes

11. Termination resistor denoting a downstream facing port.

12. Termination resistor denoting an accessory or upstream facing port.

Document Number: 001-98440 Rev. *F

Page 24 of 30

EZ-PD™ CCG4

Packaging

Table 29. Package Characteristics

Parameter

T_A

Description

Conditions

Min

–40

–

Typ

25

–

Max

85

100

–

Units

°C

Operating ambient temperature

Operating junction temperature

Package _JA(40-pin QFN)

Package _JC(40-pin QFN)

–

T_J

°C

T_JA

T_JC

31

29

°C/W

–

Table 30. Solder Reflow Peak Temperature

Package Maximum Peak Temperature

40-pin QFN 260 °C

Maximum Time within 5 °C of Peak Temperature

30 seconds

Table 31. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2

Package

MSL

40-pin QFN

MSL 3

Figure 8. 40-Pin QFN (6 × 6 × 0.6 mm), LR40A/LQ40A 4.6 × 4.6 E-PAD (Sawn) Package Outline, 001-80659

001-80659 *A

Document Number: 001-98440 Rev. *F

Page 25 of 30

EZ-PD™ CCG4

Table 32. Acronyms Used in this Document (continued)

Acronyms

Acronym

opamp

OCP

OVP

PCB

Description

operational amplifier

Table 32. Acronyms Used in this Document

Acronym

ADC

Description

analog-to-digital converter

overcurrent protection

overvoltage protection

printed circuit board

power delivery

API

ARM^®

application programming interface

advanced RISC machine, a CPU architecture

configuration channel

PD

CC

PGA

PHY

programmable gain amplifier

physical layer

CPU

central processing unit

cyclic redundancy check, an error-checking

protocol

CRC

POR

PRES

PSoC^®

PWM

RAM

RISC

RMS

RTC

power-on reset

CS

current sense

precise power-on reset

Programmable System-on-Chip™

pulse-width modulator

random-access memory

reduced-instruction-set computing

root-mean-square

DFP

downstream facing port

digital input/output, GPIO with only digital

capabilities, no analog. See GPIO.

DIO

DRP

dual role port

electrically erasable programmable read-only

memory

EEPROM

real-time clock

a USB cable that includes an IC that reports cable

characteristics (e.g., current rating) to the Type-C

ports

EMCA

RX

receive

SAR

successive approximation register

I²C serial clock

I²C serial data

EMI

ESD

FPB

FS

electromagnetic interference

electrostatic discharge

flash patch and breakpoint

full-speed

SCL

SDA

S/H

sample and hold

Serial Peripheral Interface, a communications

protocol

SPI

GPIO

IC

general-purpose input/output

integrated circuit

SRAM

SWD

TX

static random access memory

serial wire debug, a test protocol

transmit

IDE

integrated development environment

I²C, or IIC Inter-Integrated Circuit, a communications protocol

ILO

internal low-speed oscillator, see also IMO

internal main oscillator, see also ILO

input/output, see also GPIO

low-voltage detect

a new standard with a slimmer USB connector and

a reversible cable, capable of sourcing up to 100 W

of power

Type-C

IMO

I/O

Universal Asynchronous Transmitter Receiver, a

communications protocol

UART

USB

LVD

LVTTL

MCU

NC

low-voltage transistor-transistor logic

microcontroller unit

Universal Serial Bus

USB input/output, CCG4 pins used to connect to a

USB port

USBIO

XRES

no connect

external reset I/O pin

NMI

NVIC

nonmaskable interrupt

nested vectored interrupt controller

Document Number: 001-98440 Rev. *F

Page 26 of 30

EZ-PD™ CCG4

Table 33. Units of Measure (continued)

Symbol Unit of Measure

µV

Document Conventions

Units of Measure

microvolt

Table 33. Units of Measure

µW

mA

ms

mV

nA

ns

microwatt

milliampere

millisecond

millivolt

Symbol

°C

Unit of Measure

degrees Celsius

hertz

Hz

KB

1024 bytes

nanoampere

nanosecond

ohm

kHz

k

kilohertz

kilo ohm



Mbps

MHz

M

Msps

µA

megabits per second

megahertz

pF

ppm

ps

picofarad

parts per million

picosecond

second

mega-ohm

megasamples per second

microampere

microfarad

s

sps

V

samples per second

volt

µF

µs

microsecond

Document Number: 001-98440 Rev. *F

Page 27 of 30

EZ-PD™ CCG4

■ AN95615 - Designing USB 3.1 Type-C Cables Using EZ-PD™

CCG2

References and Links To Applications Collaterals

Knowledge Base Articles

■ AN95599 - Hardware Design Guidelines for EZ-PD™ CCG2

■ Key Differences Among EZ-PD™ CCG1, CCG2, CCG3 and

CCG4 - KBA210740

■ AN210403 - Hardware Design Guidelines for Dual Role Port

Applications Using EZ-PD™ USB Type-C Controllers

■ Programming EZ-PD™ CCG2, EZ-PD™ CCG3 and EZ-PD™

CCG4 Using PSoC® Programmer and MiniProg3 - KBA96477

■ AN210771 - Getting Started with EZ-PD™ CCG4

■ CCGX Frequently Asked Questions (FAQs) - KBA97244

■ Handling Precautions for CY4501 CCG1 DVK - KBA210560

■ Cypress EZ-PD™ CCGx Hardware - KBA204102

■ Difference between USB Type-C and USB-PD - KBA204033

■ CCGx Programming Methods - KBA97271

Reference Designs

■ EZ-PD™ CCG2 Electronically Marked Cable Assembly

(EMCA) Paddle Card Reference Design

■ EZ-PD™ CCG2 USB Type-C to DisplayPort Cable Solution

■ CCG1 USB Type-C to DisplayPort Cable Solution

■ Getting started with Cypress USB Type-C Products -

KBA04071

■ CCG1 USB Type-C to HDMI/DVI/VGA Adapter Solution

■ EZ-PD™ CCG2 USB Type-C to HDMI Adapter Solution

■ Type-C to DisplayPort Cable Electrical Requirements

■ CCG1 Electronically Marked Cable Assembly (EMCA) Paddle

Card Reference Design

■ Dead Battery Charging Implementation in USB Type-C

Solutions - KBA97273

■ CCG1 USB Type-C to Legacy USB Device Cable Paddle Card

Reference Schematics

■ TerminationResistorsRequiredfortheUSBType-CConnector

– KBA97180

■ EZ-USB GX3 USB Type-C to Gigabit Ethernet Dongle

■ EZ-PD™ CCG2 USB Type-C Monitor/Dock Solution

■ CCG2 20W Power Adapter Reference Design

■ CCG2 18W Power Adapter Reference Design

■ VBUS Bypass Capacitor Recommendation for Type-C Cable

and Type-C to Legacy Cable/Adapter Assemblies – KBA97270

■ Need for Regulator and Auxiliary Switch in Type-C to

DisplayPort (DP) Cable Solution - KBA97274

■ Need for a USB Billboard Device in Type-C Solutions –

KBA97146

■ EZ-USB GX3 USB Type-A to Gigabit Ethernet Reference

Design Kit

■ CCG1DevicesinType-CtoLegacyCable/AdapterAssemblies

– KBA97145

Kits

■ Cypress USB Type-C Controller Supported Solutions –

KBA97179

■ CY4501 CCG1 Development Kit

■ CY4502 EZ-PD™ CCG2 Development Kit

■ CY4531 EZ-PD CCG3 Evaluation Kit

■ CY4541 EZ-PD™ CCG4 Evaluation Kit

■ Termination Resistors for Type-C to Legacy Ports – KBA97272

■ Handling Instructions for CY4502 CCG2 Development Kit –

KBA97916

■ Thunderbolt™ Cable Application Using CCG3 Devices -

KBA210976

Datasheets

■ CCG1 Datasheet: USB Type-C Port Controller with Power

Delivery

■ Power Adapter Application Using CCG3 Devices - KBA210975

■ Methods to Upgrade Firmware on CCG3 Devices - KBA210974

■ Device Flash Memory Size and Advantages - KBA210973

■ Applications of EZ-PD™ CCG4 - KBA210739

Application Notes

■ CYPD1120 Datasheet: USB Power Delivery Alternate Mode

Controller on Type-C

■ CCG2: USB Type-C Port Controller Datasheet

■ CCG3: USB Type-C Controller Datasheet

■ AN96527 - Designing USB Type-C Products Using Cypress’s

CCG1 Controllers

Document Number: 001-98440 Rev. *F

Page 28 of 30

EZ-PD™ CCG4

Document History Page

Document Title: EZ-PD™ CCG4 USB Type-C Port Controller

Document Number: 001-98440

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

**

*A

*B

4921014

4999504

5049109

MURT

09/24/2015 New datasheet

Updated Table 1, Table 2, Table 7, Table 8, Table 18 and Table 23.

Updated Figure 3 through Figure 6 and Figure 7.

11/03/2015

12/14/2015 Updated Table 8 and Table 26.

Removed “Fixed UART DC Specifications”, “Fixed I2C DC Specifications”, “Fixed SPI DC

Specifications”, “IMO DC SPecifications” and “ILO DC Specifications” table.

Updated application schematic for both single port and dual port notebook applications

03/02/2016 Updated copyright information

*C

5141544

MVTA

Updated Sleep Current in General Description from 2 mA to 2.5 mA

Updated description for pin#34, pin#5, and pin#10 row in Table 1

Updated description for pin#5 and pin#10 row in Table 2

*D

*E

5290129 MURT/MVTA 05/31/2016 Updated to include support for PD 3.0 features.

Added Available Firmware and Software Tools.

Added descriptive notes for the application diagrams.

5307418

5669709

VGT

06/14/2016

03/30/2017

Added References and Links To Applications Collaterals.

Updated Cypress logo and copyright information.

Updated SID34 typ value.

Updated the template.

Removed CYPD4135 and CYPD4235 parts.

Moved datasheet status to Final.

*F

SVPH

Document Number: 001-98440 Rev. *F

Page 29 of 30

EZ-PD™ CCG4

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

®

Products

PSoC Solutions

ARM^®Cortex^®Microcontrollers

cypress.com/arm

cypress.com/automotive

cypress.com/clocks

cypress.com/interface

cypress.com/iot

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP

Automotive

Cypress Developer Community

Clocks & Buffers

Interface

Training | Components

Internet of Things

Memory

Technical Support

cypress.com/memory

cypress.com/mcu

cypress.com/support

Microcontrollers

PSoC

cypress.com/psoc

Power Management ICs

Touch Sensing

USB Controllers

Wireless Connectivity

cypress.com/pmic

cypress.com/touch

cypress.com/usb

cypress.com/wireless

including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress

hereby grants you under its copyright rights in the Software, a personal, non-exclusive, nontransferable license (without the right to sublicense) (a) for Software provided in source code form, to modify

and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either

directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units. Cypress also grants you a personal, non-exclusive, nontransferable, license (without the right

to sublicense) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely to the minimum

extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence. Any other use, reproduction, modification, translation, or compilation of the Software

is prohibited.

CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes to this document without further notice. Cypress does not

assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or

programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application

made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of

weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or

hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any

component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole

or in part, and Company shall and hereby does release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. Company shall indemnify

and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress

products.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in

the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 001-98440 Rev. *F

Revised March 30, 2017

Page 30 of 30

厂商	型号	描述	页数
NIDEC	CYP	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0200MB	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0200MC	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0200TB	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0200TC	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0201MB	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0201MC	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0201TB	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0201TC	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0202MB	[ PIANO SWITCHES (FULL PITCH) ]	5 页