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CYM1851V33PZ-35C

型号：

CYM1851V33PZ-35C

品牌：

CYPRESS[ CYPRESS ]

页数：

9 页

PDF大小：

286 K

下载PDF手册
851V33  
PRELIMINARY  
CYM1851V33  
1,024K x 32 3.3V Static RAM Module  
packages mounted on an epoxy laminate substrate. Four chip  
selects are used to independently enable the four bytes. Read-  
ing or writing can be executed on individual bytes or any com-  
Features  
• High-density 3.3V 32-megabit SRAM module  
bination of multiple bytes through proper use of selects.  
• 32-bit Standard Footprint supports densities from  
16K x 32 through 1M x 32  
• High-speed SRAMs  
The CYM1851V33 is designed for use with standard 72-pin  
SIMM sockets. The pinout is downward compatible with the  
64-pin JEDEC ZIP/SIMM module family (CYM1821,  
CYM1831, CYM1836, and CYM1841). Thus, a single mother-  
board design can be used to accommodate memory depth  
ranging from 16K words (CYM1821) to 1,024K words  
(CYM1851). The CYM1851V33 is offered in vertical and an-  
gled SIMM configurations and both are available with either  
tin-lead or 10 micro-inches of gold flash on the edge contacts.  
— Access time of 12 ns  
• Low active power  
— 3.3W (max.) at 12 ns  
• 72 pins  
• Available in ZIP, SIMM, or angled SIMM format  
Functional Description  
Presence detect pins (PD0−PD3) are used to identify module  
memory density in applications where modules with alternate  
word depths can be interchanged.  
The CYM1851V33 is a 3.3V high-performance 32-megabit  
static RAM module organized as 1,024K words by 32 bits. This  
module is constructed from eight 1,024K x 4 SRAMs in SOJ  
Logic Block Diagram  
Pin Configuration  
ZIP/SIMM  
Top View  
PD - GND  
0
PD - OPEN  
PD - GND  
2
NC  
PD  
1
3
5
1
NC  
3
PD  
0
A -A  
2
4
0
19  
2
PD  
20  
GND  
PD - OPEN  
3
OE  
6
8
7
9
PD  
1
8
I/O  
0
WE  
I/O  
I/O  
1
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
I/O  
I/O  
I/O  
9
10  
11  
I/O  
2
I/O  
3
1M x 4  
SRAM  
1M x 4  
SRAM  
I/O –I/O  
I/O −I/O  
4
7
0
3
V
4
4
4
4
4
CC  
7
8
A
0
A
A
1
2
A
CS  
1
A
A
9
I/O  
I/O  
I/O  
I/O  
12  
13  
14  
15  
I/O  
I/O  
I/O  
I/O  
4
5
6
7
1M x 4  
SRAM  
1M x 4  
SRAM  
I/O –I/O  
I/O −I/O  
12  
15  
8
11  
4
GND  
WE  
CS  
2
3
4
33  
35  
A
15  
A
14  
34  
36  
CS  
CS  
2
CS  
1
1M x 4  
SRAM  
1M x 4  
I/O –I/O  
I/O −I/O  
20  
23  
16  
19  
37  
39  
41  
43  
45  
47  
49  
51  
53  
55  
57  
59  
61  
63  
65  
67  
69  
71  
SRAM  
4
4
4
CS  
3
16  
38  
40  
42  
44  
46  
48  
50  
52  
54  
56  
58  
60  
62  
64  
66  
68  
70  
72  
A
17  
A
OE  
I/O  
I/O  
I/O  
I/O  
CS  
CS  
GND  
24  
25  
26  
27  
I/O  
16  
I/O  
17  
1M x 4  
SRAM  
1M x 4  
SRAM  
I/O –I/O  
28  
31  
I/O − I/O  
I/O  
24  
27  
18  
I/O  
19  
A
3
A
10  
A
4
5
A
11  
12  
13  
20  
21  
22  
23  
A
A
V
CC  
A
A
6
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
28  
29  
30  
31  
GND  
A
18  
A
19  
NC  
NC  
Cypress Semiconductor Corporation  
Document #: 38-05268 Rev. **  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Revised March 15, 2002  
PRELIMINARY  
CYM1851V33  
Selection Guide  
1851V33-12 1851V33-15 1851V33-20 1851V33-25 1851V33-35  
Maximum Access Time (ns)  
12  
15  
20  
25  
35  
Maximum Operating Current (mA)  
1450  
540  
1250  
520  
1100  
480  
1100  
480  
1100  
480  
Maximum Standby Current (mA)  
Shaded area contains advance information.  
Maximum Ratings  
Operating Range  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Ambient  
Temperature  
Range  
VCC  
Storage Temperature .................................–55°C to +125°C  
Commercial  
0°C to +70°C  
3.3V +10%/  
−5%  
Ambient Temperature with  
Power Applied...............................................–10°C to +85°C  
Supply Voltage to Ground Potential............... –0.5V to +4.6V  
DC Voltage Applied to Outputs  
in High Z State................................................ –0.5V to +VCC  
DC Input Voltage............................................ –0.5V to +4.6V  
Electrical Characteristics Over the Operating Range  
Parameter  
VOH  
VOL  
Description  
Output HIGH Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
Input Load Current  
Output Leakage Current  
Test Conditions  
VCC = Min., IOH = −4.0 mA  
Min.  
Max.  
Unit  
V
2.4  
VCC = Min., IOL = 4.0 mA  
0.4  
VCC + 0.3  
0.8  
V
VIH  
2.0  
–0.3  
–16  
–10  
V
VIL  
V
IIX  
GND < VI < VCC  
+16  
µA  
µA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
IOZ  
GND < VO < VCC, Output Disabled  
VCC = Max., IOUT = 0 mA, -12  
+10  
ICC  
VCC Operating Supply  
Current  
1450  
1250  
1100  
540  
CSN < VIL, f = MAX  
f
-15  
-20, -25, -35  
-12  
ISB1  
Automatic CS Power-Down  
Current[1]  
Max. VCC, CS > VIH,  
Min. Duty Cycle = 100%  
-15  
520  
-20, -25, -35  
480  
ISB2  
Automatic CS Power-Down  
Current[1]  
Max. VCC, CS > VCC − 0.2V, VIN > VCC − 0.2V,  
or VIN < 0.2V  
270  
Shaded area contains advance information.  
Capacitance[2]  
Parameter  
CINA  
Description  
Test Conditions  
Max.  
40  
Unit  
Input Capacitance (WE, OE, A0−19  
Input Capacitance (CS)  
)
TA = 25°C, f = 1 MHz,  
VCC = 5.0V  
pF  
pF  
pF  
CINB  
10  
COUT  
Output Capacitance  
8
Notes:  
1. A pull-up resistor to VCC on the CS input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given.  
2. Tested on a sample basis.  
Document #: 38-05268 Rev. **  
Page 2 of 9  
 
 
PRELIMINARY  
CYM1851V33  
AC Test Loads and Waveforms  
R1 317Ω  
R1 317Ω  
ALL INPUT PULSES  
90%  
10%  
5V  
5V  
3.0V  
GND  
90%  
10%  
OUTPUT  
OUTPUT  
R2  
351Ω  
R2  
351Ω  
30 pF  
5 pF  
≥ 5 ns  
≥ 5 ns  
INCLUDING  
JIG AND  
SCOPE  
INCLUDING  
JIG AND  
SCOPE  
(b)  
(a)  
Equivalent to:  
THÉVENIN EQUIVALENT  
167Ω  
1.73V  
OUTPUT  
Switching Characteristics Over the Operating Range[3]  
1851V33-12  
1851V33-15  
Parameter  
Description  
Min.  
12  
3
Max.  
Min.  
Max.  
Unit  
READ CYCLE  
tRC  
Read Cycle Time  
15  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
Address to Data Valid  
12  
15  
tOHA  
tACS  
Data Hold from Address Change  
CS LOW to Data Valid  
OE LOW to Data Valid  
OE LOW to Low Z  
3
12  
7
15  
8
tDOE  
tLZOE  
tHZOE  
tLZCS  
tHZCS  
tPD  
0
3
0
3
OE HIGH to High Z  
CS LOW to Low Z[4]  
7
8
CS HIGH to High Z[4, 5]  
7
8
CS HIGH to Power-Down  
12  
15  
WRITE CYCLE[6]  
tWC  
Write Cycle Time  
12  
9
15  
10  
10  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tSCS  
CS LOW to Write End  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
tAW  
9
tHA  
0
tSA  
1
1
tPWE  
tSD  
10  
7
12  
8
Data Set-Up to Write End  
Data Hold from Write End  
WE HIGH to Low Z  
tHD  
1
1
tLZWE  
tHZWE  
3
3
WE LOW to High Z[5]  
0
7
0
8
Shaded area contains advance information.  
Notes:  
3. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified  
IOL/IOH and 30-pF load capacitance.  
4. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device. These parameters are guaranteed and not 100% tested.  
5.  
tHZCS and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage.  
6. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can  
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.  
Document #: 38-05268 Rev. **  
Page 3 of 9  
 
 
 
 
PRELIMINARY  
CYM1851V33  
Switching Characteristics Over the Operating Range[3] (continued)  
1851V33-20  
1851V33-25  
1851V33-35  
Parameter  
Description  
Min.  
20  
3
Max.  
Min.  
25  
3
Max.  
Min.  
35  
3
Max.  
Unit  
READ CYCLE  
tRC  
Read Cycle Time  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
Address to Data Valid  
Data Hold from Address Change  
CS LOW to Data Valid  
OE LOW to Data Valid  
OE LOW to Low Z  
20  
25  
35  
tOHA  
tACS  
20  
12  
25  
15  
35  
18  
tDOE  
tLZOE  
tHZOE  
tLZCS  
tHZCS  
tPD  
0
3
0
3
0
3
OE HIGH to High Z  
CS LOW to Low Z[4]  
CS HIGH to High Z[4, 5]  
10  
12  
15  
10  
20  
12  
25  
15  
35  
CS HIGH to Power-Down  
WRITE CYCLE[6]  
tWC  
Write Cycle Time  
20  
17  
17  
3
25  
20  
20  
3
35  
30  
30  
3
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tSCS  
CS LOW to Write End  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
tAW  
tHA  
tSA  
2
2
2
tPWE  
tSD  
15  
12  
2
20  
15  
2
30  
20  
2
Data Set-Up to Write End  
Data Hold from Write End  
WE HIGH to Low Z  
tHD  
tLZWE  
tHZWE  
3
3
3
WE LOW to High Z[5]  
0
12  
0
12  
0
15  
Switching Waveforms  
Read Cycle No. 1 [7,8]  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
Notes:  
7. WE is HIGH for read cycle.  
8. Device is continuously selected, CS = VIL, and OE= VIL  
.
Document #: 38-05268 Rev. **  
Page 4 of 9  
 
 
 
PRELIMINARY  
CYM1851V33  
Switching Waveforms (continued)  
[7,9]  
Read Cycle No. 2  
t
RC  
CS  
t
ACS  
OE  
t
HZOE  
t
DOE  
t
HZCS  
t
LZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA VALID  
DATA OUT  
t
LZCS  
t
PD  
t
PU  
ICC  
ISB  
V
CC  
50%  
50%  
SUPPLY  
CURRENT  
Write Cycle No. 1 (WE Controlled) [6]  
t
WC  
ADDRESS  
CS  
t
SCS  
t
t
HA  
AW  
t
t
SA  
PWE  
WE  
t
t
HD  
SD  
DATA IN  
DATA VALID  
t
t
LZWE  
HZWE  
HIGH IMPEDANCE  
DATA OUT  
DATA UNDEFINED  
Note:  
9. Address valid prior to or coincident with CS transition LOW.  
Document #: 38-05268 Rev. **  
Page 5 of 9  
 
PRELIMINARY  
CYM1851V33  
Switching Waveforms (continued)  
Write Cycle No. 2 (CS Controlled)[6,10]  
t
WC  
ADDRESS  
t
SA  
t
SCS  
CS  
t
t
HA  
AW  
t
PWE  
WE  
t
t
HD  
SD  
DATA IN  
DATA VALID  
t
HZWE  
HIGH IMPEDANCE  
DATA OUT  
DATA UNDEFINED  
Note:  
10. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.  
Truth Table  
CS WE OE Inputs/Output  
Mode  
Deselect/Power-Down  
Read  
H
L
L
L
X
H
L
X
L
High Z  
Data Out  
Data In  
High Z  
X
H
Write  
H
Deselect  
Ordering Information  
Speed  
Package  
Operating  
(ns)  
Ordering Code  
Type  
PM04  
PM04  
PN04  
PN04  
PZ09  
PM04  
PM04  
PN04  
PN04  
PZ09  
Package Type  
72-Pin Plastic SIMM Module  
Range  
12  
CYM1851V33PM-12C  
CYM1851V33P8-12C  
CYM1851V33PN-12C  
CYM1851V33P6-12C  
CYM1851V33PZ-12C  
CYM1851V33PM-15C  
CYM1851V33P8-15C  
CYM1851V33PN-15C  
CYM1851V33P6-15C  
CYM1851V33PZ-15C  
Commercial  
72-Pin Plastic SIMM Module (gold contacts)  
72-Pin Plastic Angled SIMM Module  
72-Pin Plastic Angled SIMM Module (gold contacts)  
72-Pin Plastic ZIP Module  
15  
72-Pin Plastic SIMM Module  
Commercial  
72-Pin Plastic SIMM Module (gold contacts)  
72-Pin Plastic Angled SIMM Module  
72-Pin Plastic Angled SIMM Module (gold contacts)  
72-Pin Plastic ZIP Module  
Shaded area contains advance information.  
Document #: 38-05268 Rev. **  
Page 6 of 9  
 
PRELIMINARY  
CYM1851V33  
Ordering Information (continued)  
Speed  
(ns)  
Package  
Type  
Operating  
Range  
Ordering Code  
Package Type  
20  
25  
35  
CYM1851V33PM-20C  
CYM1851V33P8-20C  
CYM1851V33PN-20C  
CYM1851V33P6-20C  
CYM1851V33PZ-20C  
CYM1851V33PM-25C  
CYM1851V33P8-25C  
CYM1851V33PN-25C  
CYM1851V33P6-25C  
CYM1851V33PZ-25C  
CYM1851V33PM-35C  
CYM1851V33P8-35C  
CYM1851V33PN-35C  
CYM1851V33P6-35C  
CYM1851V33PZ-35C  
PM04  
PM04  
PN04  
PN04  
PZ09  
PM04  
PM04  
PN04  
PN04  
PZ09  
PM04  
PM04  
PN04  
PN04  
PZ09  
72-Pin Plastic SIMM Module  
Commercial  
72-Pin Plastic SIMM Module (gold contacts)  
72-Pin Plastic Angled SIMM Module  
72-Pin Plastic Angled SIMM Module (gold contacts)  
72-Pin Plastic ZIP Module  
72-Pin Plastic SIMM Module  
Commercial  
Commercial  
72-Pin Plastic SIMM Module (gold contacts)  
72-Pin Plastic Angled SIMM Module  
72-Pin Plastic Angled SIMM Module (gold contacts)  
72-Pin Plastic ZIP Module  
72-Pin Plastic SIMM Module  
72-Pin Plastic SIMM Module (gold contacts)  
72-Pin Plastic Angled SIMM Module  
72-Pin Plastic Angled SIMM Module (gold contacts)  
72-Pin Plastic ZIP Module  
Package Diagrams  
72-Pin Plastic SIMM Module PM04  
72-Pin Plastic Angled SIMM Module PN04  
Document #: 38-05268 Rev. **  
Page 7 of 9  
PRELIMINARY  
CYM1851V33  
Package Diagrams (continued)  
72-Pin Plastic ZIP Module PZ09  
Document #: 38-05268 Rev. **  
Page 8 of 9  
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
PRELIMINARY  
CYM1851V33  
Document Title: CYM1851V33 1,024K x 32 3.3V Static RAM Module  
Document Number: 38-05268  
Issue  
Date  
Orig. of  
Change  
REV.  
ECN NO.  
Description of Change  
**  
114168  
3/19/02  
DSG  
Change from Spec number: 38-M-00090 to 38-05268  
Document #: 38-05268 Rev. **  
Page 9 of 9  
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