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8N4SV75LC-0165CDI

型号：

8N4SV75LC-0165CDI

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

19 页

PDF大小：

192 K

下载PDF手册
LVDS Frequency-Programmable VCXO  
IDT8N4SV75  
DATA SHEET  
General Description  
Features  
The IDT8N4SV75 is a LVDS Frequency-Programmable VCXO with  
very flexible frequency and pull-range programming capabilities. The  
device uses IDT’s fourth generation FemtoClock® NG technology for  
an optimum of high clock frequency and low phase noise  
performance. The device accepts 2.5V or 3.3V supply and is  
packaged in a small, lead-free (RoHS 6) 6-lead ceramic 5mm x 7mm  
x 1.55mm package.  
• Fourth generation FemtoClock® NG technology  
• Programmable clock output frequency from 15.476MHz to  
866.67MHz and from 975MHz to 1,300MHz  
• Frequency programming resolution is 218Hz and better  
• Factory-programmable VCXO pull range and control voltage  
polarity  
• Absolute pull-range (APR) programmable from 4.5 to  
The device can be factory-programmed to any frequency in the  
range of 15.476MHz to 866.67MHz and from 975MHz to 1,300MHz  
to the very high degree of frequency precision of 218Hz or better.  
The extended temperature range supports wireless infrastructure,  
telecommunication and networking end equipment requirements.  
754.5ppm  
• One 2.5V / 3.3V LVDS clock output  
• Output enable control input, LVCMOS/LVTTL compatible  
• RMS phase jitter @ 156.25MHz (12kHz - 20MHz):  
0.53ps (typical)  
• 2.5V or 3.3V supply voltage  
• -40°C to 85°C ambient operating temperature  
• Lead-free (RoHS 6) 6-lead ceramic 5mm x 7mm x 1.55mm  
package  
Block Diagram  
Pin Assignment  
VC 1  
OE 2  
6 V  
DD  
PFD  
&
LPF  
FemtoClock® NG  
VCO  
1950-2600MHz  
Q  
nQ  
÷P  
5 nQ  
4 Q  
OSC  
÷N  
GND 3  
114.285 MHz  
IDT8N4SV75  
6-lead ceramic 5mm x 7mm x 1.55mm  
package body  
2
÷MINT, MFRAC  
A/D  
VC  
OE  
CD Package  
Top View  
7
7
25  
Configuration Register (ROM)  
(Frequency, APR, Polarity)  
Pullup  
IDT8N4SV75CCD REVISION B NOVEMBER 6, 2013  
1
©2013 Integrated Device Technology, Inc.  
IDT8N4SV75 Data Sheet  
LVDS FREQUENCY PROGRAMMABLE VCXO  
Pin Description and Characteristic Tables  
Table 1. Pin Descriptions  
Number  
Name  
VC  
Type  
Description  
1
2
Input  
Input  
VCXO Control Voltage input.  
OE  
Pullup  
Output enable pin. See Table 3A for function. LVCMOS/LVTTL interface levels.  
Power supply ground.  
3
GND  
Power  
Output  
Power  
4, 5  
Differential clock output pair. LVDS interface levels.  
Q, nQ  
VDD  
6
Power supply pin.  
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.  
Table 2. Pin Characteristics  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
5.5  
Maximum  
Units  
pF  
OE  
VC  
CIN  
Input Capacitance  
Input Pullup Resistor  
10  
pF  
RPULLUP  
50  
k  
IDT8N4SV75CCD REVISION B NOVEMBER 6, 2013  
2
©2013 Integrated Device Technology, Inc.  
 
IDT8N4SV75 Data Sheet  
LVDS FREQUENCY PROGRAMMABLE VCXO  
Function Tables  
Table 3A. OE Configuration  
Input  
OE  
0
Output Enable  
Outputs Q, nQ are in high-impedance state.  
Outputs are enabled.  
1 (default)  
Table 3B. Output Frequency Range  
15.476MHz to 866.67MHz  
975MHz to 1,300MHz  
NOTE: Supported output frequency range. The output frequency can be programmed to any frequency in this range and to a precision of  
218Hz or better.  
Principles of Operation  
The block diagram consists of the internal 3RD overtone crystal and  
oscillator which provide the reference clock fXTAL of 114.285MHz.  
The PLL includes the FemtoClock® NG VCO along with the  
Table 3C. Frequency Selection  
Pre-divider (P), the feedback divider (M) and the post divider (N). The  
P, M, and N dividers determine the output frequency based on the  
fXTAL reference. The feedback divider is fractional supporting a huge  
number of output frequencies. Internal registers are used to hold up  
to two different factory pre-set configuration settings. The  
configuration is selected via the FSEL pin. Changing the FSEL  
control results in an immediate change of the output frequency to the  
selected register values. The P, M, and N frequency configurations  
support an output frequency range 15.476MHz to 866.67MHz and  
975MHz to 1,300MHz.  
Input  
FSEL  
0 (default)  
1
Selects  
Frequency 0  
Frequency 1  
Frequency Configuration  
The devices use the fractional feedback divider with a delta-sigma  
modulator for noise shaping and robust frequency synthesis  
capability. The relatively high reference frequency minimizes phase  
noise generated by frequency multiplication and allows more efficient  
shaping of noise by the delta-sigma modulator. The output frequency  
is determined by the 2-bit pre-divider (P), the feedback divider (M)  
and the 7-bit post divider (N). The feedback divider (M) consists of  
both a 7-bit integer portion (MINT) and an 18-bit fractional portion  
(MFRAC) and provides the means for high-resolution frequency  
generation. The output frequency fOUT is calculated by:  
An order code is assigned to each frequency configuration and the  
VCXO pull-range programmed by the factory (default frequencies).  
For more information on the available default frequencies and order  
codes, please see the Ordering Information Section in this document.  
For available order codes, see the FemtoClock NG Ceramic-Package  
XO and VCXO Ordering Product Information document. For more  
information on programming capabilities of the device for custom  
frequency and pull range configurations, see the FemtoClock NG  
Ceramic 5x7 Module Programming Guide.  
1
P N  
MFRAC + 0.5  
------------  
-------------------------------------  
f
= f  
MINT +  
(1)  
OUT  
XTAL  
18  
2
IDT8N4SV75CCD REVISION B NOVEMBER 6, 2013  
3
©2013 Integrated Device Technology, Inc.  
IDT8N4SV75 Data Sheet  
LVDS FREQUENCY PROGRAMMABLE VCXO  
Absolute Maximum Ratings  
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.   
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond   
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for   
extended periods may affect product reliability.  
Item  
Rating  
Supply Voltage, VDD  
Inputs, VI  
3.63V  
-0.5V to VDD + 0.5V  
Outputs, IO (LVDS)  
Continuous Current  
Surge Current  
10mA  
15mA  
Package Thermal Impedance, JA  
49.4C/W (0 mps)  
-65C to 150C  
Storage Temperature, TSTG  
DC Electrical Characteristics  
Table 4A. Power Supply DC Characteristics, VDD = 3.3V 5%, TA = -40°C to 85°C  
Symbol Parameter  
VDD Power Supply Voltage  
IDD Power Supply Current  
Test Conditions  
Minimum  
Typical  
3.3  
Maximum  
3.465  
Units  
V
3.135  
140  
175  
mA  
Table 4B. Power Supply DC Characteristics, VDD = 2.5V 5%, TA = -40°C to 85°C  
Symbol Parameter  
VDD Power Supply Voltage  
IDD Power Supply Current  
Test Conditions  
Minimum  
Typical  
2.5  
Maximum  
2.625  
Units  
V
2.375  
136  
170  
mA  
Table 4C. LVCMOS/LVTTL DC Characteristic, VDD = 3.3V 5% or 2.5V 5%, TA = -40°C to 85°C  
Symbol Parameter  
Test Conditions  
VDD = 3.3V  
Minimum  
Typical  
Maximum  
VDD + 0.3  
VDD + 0.3  
0.8  
Units  
V
2
VIH  
VIL  
Input High Voltage  
VDD = 2.5V  
1.7  
-0.3  
-0.3  
V
V
DD = 3.3V  
DD = 2.5V  
V
Input Low Voltage  
V
0.7  
V
IIH  
IIL  
Input High Current  
Input Low Current  
OE  
OE  
VDD = VIN = 3.465V or 2.625V  
5
µA  
µA  
VDD = 3.465V or 2.625V, VIN = 0V  
-150  
IDT8N4SV75CCD REVISION B NOVEMBER 6, 2013  
4
©2013 Integrated Device Technology, Inc.  
IDT8N4SV75 Data Sheet  
LVDS FREQUENCY PROGRAMMABLE VCXO  
Table 4D. LVDS DC Characteristics, VDD = 3.3V 5%, TA = -40°C to 85°C  
Symbol  
VOD  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
454  
Units  
mV  
mV  
V
Differential Output Voltage  
VOD Magnitude Change  
Offset Voltage  
247  
330  
VOD  
VOS  
50  
1.14  
1.23  
1.31  
50  
VOS  
VOS Magnitude Change  
mV  
Table 4E. LVDS DC Characteristics, VDD = 2.5V 5%, TA = -40°C to 85°C  
Symbol  
VOD  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
454  
Units  
mV  
mV  
V
Differential Output Voltage  
VOD Magnitude Change  
Offset Voltage  
247  
320  
VOD  
VOS  
50  
1.13  
1.22  
1.30  
50  
VOS  
VOS Magnitude Change  
mV  
IDT8N4SV75CCD REVISION B NOVEMBER 6, 2013  
5
©2013 Integrated Device Technology, Inc.  
IDT8N4SV75 Data Sheet  
LVDS FREQUENCY PROGRAMMABLE VCXO  
AC Electrical Characteristics  
Table 5A. AC Characteristics, VDD = 3.3V 5% or 2.5V 5%, TA = -40°C to 85°C  
Symbol  
fOUT  
fI  
Parameter  
Test Conditions  
Minimum  
15.476  
975  
Typical  
Maximum  
Units  
MHz  
MHz  
ppm  
ppm  
ppm  
ppm  
ppm  
ppm  
ppm  
ppm  
ppm  
ps  
866.67  
1,300  
10  
Output Frequency Q, nQ  
Initial Accuracy  
Measured @ 25°C, VC = VDD/2  
Option code = A or B  
100  
50  
fS  
fA  
fT  
Temperature Stability  
Aging  
Option code = E or F  
Option code = K or L  
20  
Frequency drift over 10 year life  
Frequency drift over 15 year life  
Option code A, B (10 year life)  
Option code E, F (10 year life)  
Option code K, L (10 year life)  
3
5
113  
63  
Total Stability  
33  
tjit(cc)  
Cycle-to-Cycle Jitter; NOTE 1  
Period Jitter; NOTE 1  
6
4
14  
tjit(per)  
6
ps  
RMS Phase Jitter (Random);  
NOTE 2, 3  
156.25MHz, Integration Range:  
12kHz - 20MHz  
tjit(Ø)  
0.53  
0.73  
ps  
500MHz <fout 1300MHz  
100MHz <fout 500MHz  
15MHz fout 100MHz  
0.46  
0.48  
0.76  
0.67  
0.63  
1.4  
ps  
ps  
ps  
RMS Phase Jitter (Random);   
NOTE 2, 3  
fXTAL = 114.285MHz  
tjit(Ø)  
Single-side band phase noise,  
100Hz from Carrier  
N(100)  
N(1k)  
156.25MHz  
156.25MHz  
156.25MHz  
156.25MHz  
156.25MHz  
156.25MHz  
-67  
-89  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dbc  
Single-side band phase noise,   
1kHz from Carrier  
Single-side band phase noise,   
10kHz from Carrier  
N(10k)  
N(100k)  
N(1M)  
N(10M)  
PSNR  
-113  
-118  
-127  
-137  
-58.7  
Single-side band phase noise,  
100kHz from Carrier  
Single-side band phase noise,   
1MHz from Carrier  
Single-side band phase noise,   
10MHz from Carrier  
50mV Sinusoidal Noise  
1kHz - 50MHz  
Power Supply Noise Rejection  
tR / tF  
odc  
Output Rise/Fall Time  
Output Duty Cycle  
20% to 80%  
80  
45  
500  
55  
ps  
%
Device Startup Time after  
Power-up  
tSTARTUP  
15  
ms  
NOTES are on next page.  
IDT8N4SV75CCD REVISION B NOVEMBER 6, 2013  
6
©2013 Integrated Device Technology, Inc.  
IDT8N4SV75 Data Sheet  
LVDS FREQUENCY PROGRAMMABLE VCXO  
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is  
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium  
has been reached under these conditions.  
NOTE: Characterized with VC = VDD/2.  
NOTE: XTAL parameters (initial accuracy, temperature stability, aging and total stability) are guaranteed by manufacturing.  
NOTE 1: This parameter is defined in accordance with JEDEC standard 65.  
NOTE 2: Please refer to the phase noise plots.  
NOTE 3: Please see the FemtoClock NG Ceramic 5x7 Modules Programming guide for more information on PLL feedback modes and the  
optimum configuration for phase noise.  
NOTE 4: 12kHz to 20MHz.  
Table 5B. VCXO Control Voltage Input (V ) Characteristics, VDD = 3.3V 5% or 2.5 5, TA = -40°C to 85°C  
C
Symbol Parameter  
Test Conditions  
Minimum  
7.57  
Typical  
Maximum  
477.27  
630  
Units  
ppm/V  
ppm/V  
Oscillator Gain, NOTE 1, 2, 3  
VDD = 3.3V  
KV  
Oscillator Gain, NOTE 1, 2, 3  
V
DD = 2.5V  
10  
Control Voltage Linearity;  
NOTE 4  
LVC  
BSL Variation  
-1  
0.1  
+1  
%
BW  
Modulation Bandwidth  
VC Input Impedance  
Nominal Control Voltage  
100  
500  
kHz  
k  
V
ZVC  
VCNOM  
VDD/2  
Control Voltage Tuning Range;  
NOTE 4  
VC  
0
VDD  
V
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is  
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium  
has been reached under these conditions.  
NOTE 1: VC = 10% to 90% of VDD.  
NOTE 2: Nominal oscillator gain: Pull range divided by the control voltage tuning range of 3.3V. E.g. for ADC_GAIN [6:0] = 000001 the pull  
range is 12.5ppm, resulting in an oscillator gain of 25ppm ÷ 3.3V = 7.57ppm/V.  
NOTE 3: For best phase noise performance, use the lowest KV that meets the requirements of the application.  
NOTE 4: BSL = Best Straight Line Fit: Variation of the output frequency vs. control voltage VC, in percent. VC ranges from 10% to 90% VDD  
.
IDT8N4SV75CCD REVISION B NOVEMBER 6, 2013  
7
©2013 Integrated Device Technology, Inc.  
IDT8N4SV75 Data Sheet  
LVDS FREQUENCY PROGRAMMABLE VCXO  
RMS Phase Jitter  
Offset from Carrier Frequency (Hz)  
IDT8N4SV75CCD REVISION B NOVEMBER 6, 2013  
8
©2013 Integrated Device Technology, Inc.  
IDT8N4SV75 Data Sheet  
LVDS FREQUENCY PROGRAMMABLE VCXO  
Parameter Measurement Information  
SCOPE  
SCOPE  
Q
Q
V
DD  
V
2.5V 5%  
POWER SUPPLY  
DD  
3.3V 5%  
POWER SUPPLY  
+
Float GND –  
+
Float GND –  
nQ  
nQ  
2.5V LVDS Output Load Test Circuit  
3.3V LVDS Output Load Test Circuit  
VOH  
VREF  
VOL  
1σ contains 68.26% of all measurements  
2σ contains 95.4% of all measurements  
3σ contains 99.73% of all measurements  
4σ contains 99.99366% of all measurements  
6σ contains (100-1.973x10-7)% of all measurements  
Histogram  
Reference Point  
(Trigger Edge)  
Mean Period  
(First edge after trigger)  
RMS Phase Jitter  
Period Jitter  
nQ  
Q
nQ  
Q
tPW  
tPERIOD  
➤
➤
tcycle n  
tcycle n+1  
➤
➤
tPW  
tjit(cc) = tcycle n – tcycle n+1  
|
|
odc =  
x 100%  
1000 Cycles  
tPERIOD  
Cycle-to-Cycle Jitter  
Output Duty Cycle/Pulse Width/Period  
IDT8N4SV75CCD REVISION B NOVEMBER 6, 2013  
9
©2013 Integrated Device Technology, Inc.  
IDT8N4SV75 Data Sheet  
LVDS FREQUENCY PROGRAMMABLE VCXO  
Parameter Measurement Information, continued  
nQ  
80%  
tF  
80%  
tR  
VOD  
20%  
20%  
Q
Output Rise/Fall Time  
Offset Voltage Setup  
Differential Output Voltage Setup  
IDT8N4SV75CCD REVISION B NOVEMBER 6, 2013  
10  
©2013 Integrated Device Technology, Inc.  
IDT8N4SV75 Data Sheet  
LVDS FREQUENCY PROGRAMMABLE VCXO  
Applications Information  
LVDS Driver Termination  
For a general LVDS interface, the recommended value for the  
termination impedance (ZT) is between 90and 132. The actual  
value should be selected to match the differential impedance (Z0) of  
your transmission line. A typical point-to-point LVDS design uses a  
100parallel resistor at the receiver and a 100differential  
transmission-line environment. In order to avoid any  
standard termination schematic as shown in Figure 1A can be used  
with either type of output structure. Figure 1B, which can also be  
used with both output types, is an optional termination with center tap  
capacitance to help filter common mode noise. The capacitor value  
should be approximately 50pF. If using a non-standard termination, it  
is recommended to contact IDT and confirm if the output structure is  
current source or voltage source type. In addition, since these  
outputs are LVDS compatible, the input receiver’s amplitude and  
common-mode input range should be verified for compatibility with  
the output.  
transmission-line reflection issues, the components should be  
surface mounted and must be placed as close to the receiver as  
possible. IDT offers a full line of LVDS compliant devices with two  
types of output structures: current source and voltage source. The  
ZO ZT  
LVDS  
Driver  
LVDS  
Receiver  
ZT  
Figure 1A. Standard Termination  
ZT  
ZO ZT  
LVDS  
Driver  
2
ZT  
2
LVDS  
Receiver  
C
Figure 1B. Optional Termination  
Figure 1. Typical LVDS Driver Termination  
IDT8N4SV75CCD REVISION B NOVEMBER 6, 2013  
11  
©2013 Integrated Device Technology, Inc.  
IDT8N4SV75 Data Sheet  
LVDS FREQUENCY PROGRAMMABLE VCXO  
Schematic Layout  
Figure 2 shows an example of IDT8N4SV75 application schematic.  
In this example, the device is operated at VDD = 3.3V. As with any  
high speed analog circuitry, the power supply pins are vulnerable to  
random noise. To achieve optimum jitter performance, power supply  
isolation is required.  
filter performance is designed for a wide range of noise frequencies.  
This low-pass filter starts to attenuate noise at approximately 10kHz.  
If a specific frequency noise component is known, such as switching  
power supplies frequencies, it is recommended that component  
values be adjusted and if required, additional filtering be added.  
Additionally, good general design practices for power plane voltage  
stability suggests adding bulk capacitance in the local area of all  
devices.  
In order to achieve the best possible filtering, it is recommended that  
the placement of the filter components be on the device side of the  
PCB as close to the power pins as possible. If space is limited, the  
0.1µF capacitor in each power pin filter should be placed on the  
device side of the PCB and the other components can be placed on  
the opposite side.  
The schematic example focuses on functional connections and is not  
configuration specific. Refer to the pin description and functional  
tables in the datasheet to ensure that the logic control inputs are  
properly set.  
Power supply filter recommendations are a general guideline to be  
used for reducing external noise from coupling into the devices. The  
3.3V  
BLM18BB221SN1  
VDD  
1
2
C1  
C2  
Ferrite Bead  
C3  
U1  
VDD  
0.1uF  
10uF  
0.1uF  
R1  
SP  
J1  
1
VC  
1
2
3
6
5
4
VC  
OE  
VEE  
VCC  
nQ  
Q
OE  
R4  
SP  
Q
+
-
Zo_Dif f = 100 Ohm  
R1  
100  
nQ  
LVDS Termination  
VDD=3.3V  
Q
Logic Control Input Examples  
Set Logic  
Input to  
'1'  
Set Logic  
Input to  
'0'  
VDD  
VDD  
R2  
50  
Zo_Dif f = 100 Ohm  
+
-
RU1  
1K  
RU2  
Not Install  
C4  
0.1uF  
R3  
50  
To Logic  
Input  
pins  
To Logic  
Input  
pins  
nQ  
RD1  
Not Install  
RD2  
1K  
Alternate  
LVDS  
Termination  
Figure 2. IDT8N4SV75 Schematic Example  
IDT8N4SV75CCD REVISION B NOVEMBER 6, 2013  
12  
©2013 Integrated Device Technology, Inc.  
IDT8N4SV75 Data Sheet  
LVDS FREQUENCY PROGRAMMABLE VCXO  
Power Considerations  
This section provides information on power dissipation and junction temperature for the IDT8N4SV75.   
Equations and example calculations are also provided.  
1. Power Dissipation.  
The total power dissipation for the IDT8N4SV75 is the sum of the core power plus the analog power plus the power dissipated due to the load.  
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.  
•
Power MAX = VCC_MAX * ICC_MAX = 3.465V * 175mA = 606mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond  
wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = JA * Pd_total + TA  
Tj = Junction Temperature  
JA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and  
a multi-layer board, the appropriate value is 49.4°C/W per Table 6 below.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C + 0.606mW * 49.4°C/W = 114.9°C. This is below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of  
board (multi-layer).  
Table 6. Thermal Resistance JA for a 6-Lead Ceramic 5mm x 7mm Package, Forced Convection  
JA by Velocity  
Meters per Second  
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards  
49.4°C/W  
44.2°C/W  
42.1°C/W  
IDT8N4SV75CCD REVISION B NOVEMBER 6, 2013  
13  
©2013 Integrated Device Technology, Inc.  
IDT8N4SV75 Data Sheet  
LVDS FREQUENCY PROGRAMMABLE VCXO  
Reliability Information  
Table 7. JA vs. Air Flow Table for a 6-Lead Ceramic 5mm x 7mm Package  
JA vs. Air Flow  
Meters per Second  
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards  
49.4°C/W  
44.2°C/W  
42.1°C/W  
Transistor Count  
The transistor count for IDT8N4SV75 is: 47,414  
IDT8N4SV75CCD REVISION B NOVEMBER 6, 2013  
14  
©2013 Integrated Device Technology, Inc.  
IDT8N4SV75 Data Sheet  
LVDS FREQUENCY PROGRAMMABLE VCXO  
Package Outline and Package Dimensions  
IDT8N4SV75CCD REVISION B NOVEMBER 6, 2013  
15  
©2013 Integrated Device Technology, Inc.  
IDT8N4SV75 Data Sheet  
LVDS FREQUENCY PROGRAMMABLE VCXO  
Ordering Information for FemtoClock NG Ceramic-Package XO and VCXO Products  
The programmable VCXO and XO devices support a variety of  
devices options such as the output type, number of default frequen-  
cies, internal crystal frequency, power supply voltage, ambient  
temperature range and the frequency accuracy. The device options,  
default frequencies and default VCXO pull range must be specified at  
the time of order and are programmed by IDT before the shipment.  
The table below specifies the available order codes, including the  
device options and default frequency configurations. Example part  
number: the order code 8N3QV01FG-0001CDI specifies a  
contains a 114.285MHz internal crystal as frequency source,  
industrial temperature range, a lead-free (6/6 RoHS) 6-lead ceramic  
5mm x 7mm x 1.55mm package and is factory-programmed to the  
default frequencies of 100MHz, 122.88MHz, 125MHz and  
156.25MHz and to the VCXO pull range of min. 100 ppm.  
Other default frequencies and order codes are available from IDT on  
request. For more information on available default frequencies, see  
the FemtoClock NG Ceramic-Package XO and VCXO Ordering  
Product Information document.  
programmable, quad default-frequency VCXO with a voltage supply  
of 2.5V, a LVPECL output, a 50 ppm crystal frequency accuracy,  
Part/Order Number  
8N X X XXX X X - dddd XX X X  
Shipping Package  
8: Tape & Reel  
(no letter): Tray  
FemtoClock NG  
I/O Identifier  
Ambient Temperature Range  
“I”: Industrial: (TA = -40°C to 85°C)  
(no letter) : (TA = 0°C to 70°C)  
0: LVCMOS  
3: LVPECL  
4: LVDS  
Package Code  
CD: Lead-Free, 6/10-lead ceramic 5mm x 7mm x 1.55mm  
Number of Default Frequencies  
S: 1: Single  
D: 2: Dual  
Q: 4: Quad  
Default-Frequency and VCXO Pull Range  
See document FemtoClock NG Ceramic-Package XO and VCXO  
Ordering Product Information.  
dddd  
fXTAL (MHz) PLL feedback  
Use for  
VCXO, XO  
XO  
Part Number  
0000 to 0999  
1000 to 1999  
2000 to 2999  
114.285  
Fractional  
Integer  
OE fct. at  
Function #pins  
pin  
100.000  
Fractional  
XO  
001  
003  
V01  
V03  
V75  
V76  
V85  
085  
270  
271  
272  
273  
XO  
XO  
10  
10  
10  
10  
6
OE@2  
OE@1  
OE@2  
OE@1  
OE@2  
nOE@2  
—
Last digit = L: configuration pre-programmed and not changeable  
VCXO  
VCXO  
VCXO  
VCXO  
VCXO  
XO  
Die Revision  
C
6
6
Option Code (Supply Voltage and Frequency-Stability)  
6
OE@1  
OE@1  
OE@2  
nOE@2  
nOE@1  
A: VCC = 3.3V 5%, 100ppm  
B: VCC = 2.5V 5%, 100ppm  
XO  
6
XO  
6
E: VCC = 3.3V 5%,  
F: VCC = 2.5V 5%,  
K: VCC = 3.3V 5%,  
L: VCC = 2.5V 5%,  
50ppm  
50ppm  
20ppm  
20ppm  
XO  
6
XO  
6
NOTE: For order information, also see the FemtoClock NG Ceramic-Package XO and VCXO Ordering Product Information document.  
IDT8N4SV75CCD REVISION B NOVEMBER 6, 2013  
16  
©2013 Integrated Device Technology, Inc.  
IDT8N4SV75 Data Sheet  
LVDS FREQUENCY PROGRAMMABLE VCXO  
Device Marking  
Table 8. Device Marking  
Industrial Temperature Range (TA = -40°C to 85°C)  
Commercial Temperature Range (TA = 0°C to 70°C)  
IDT8N4SV75yC-  
ddddCDI  
IDT8N4SV75yC-  
ddddCD  
Marking  
y = Option Code, dddd=Default-Frequency and VCXO Pull Range  
IDT8N4SV75CCD REVISION B NOVEMBER 6, 2013  
17  
©2013 Integrated Device Technology, Inc.  
IDT8N4SV75 Data Sheet  
LVDS FREQUENCY PROGRAMMABLE VCXO  
Revision History Sheet  
Rev  
Table  
Page  
Description of Change  
Date  
4
Absolute Maximum Ratings - Thermal Impedance changed from 41.4 to 41.9.  
Power Considerations - corrected Thermal Resistance table and updated calculations.  
Reliability Information - corrected thermal table.  
A
13  
14  
4/25/12  
8/22/12  
T7  
T4D  
T4E  
5
5
15  
3.3V LVDS DC Characteristics Table - updated specs.  
2.5V LVDS DC Characteristics Table - updated specs.  
Corrected Package Information.  
B
B
Per PCN #N1206-02.  
T5A  
6
AC Characteristics Table - RMS Phase Jitter parameter change test conditions of:  
500MHz fout 1300MHz to 500MHz <fout 1300MHz; and  
100MHz fout 500MHz to 100MHz <fout 500MHz  
11/6/13  
15  
Corrected Package Outline & Dimensions drawing.  
IDT8N4SV75CCD REVISION B NOVEMBER 6, 2013  
18  
©2013 Integrated Device Technology, Inc.  
IDT8N4SV75 Data Sheet  
LVDS FREQUENCY PROGRAMMABLE VCXO  
We’ve Got Your Timing Solution  
6024 Silver Creek Valley Road Sales  
Technical Support  
800-345-7015 (inside USA)  
netcom@idt.com  
San Jose, California 95138  
+408-284-8200 (outside USA) +480-763-2056  
Fax: 408-284-2775  
www.IDT.com/go/contactIDT  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,  
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not  
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the  
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any  
license under intellectual property rights of IDT or any third parties.  
IDT’s products are not intended for use in application involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to signifi-  
cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third  
party owners.  
Copyright 2013. All rights reserved.  
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