找货询价

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

QQ咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

技术支持

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

售后咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

HYS72V16600GR-7.5-C2

型号:

HYS72V16600GR-7.5-C2

品牌:

INFINEON[ Infineon ]

页数:

20 页

PDF大小:

295 K

HYS 72Vxx5/6x0GR-7.5  
Low Profile PC133 Registered SDRAM-Modules  
3.3 V Low Profile 168-pin PC133 Registered  
SDRAM Modules for 1U Server Applications  
PC133 128 MByte Module  
PC133 256 MByte module  
PC133 512 MByte Module  
PC133 1024 MByte Module  
168-pin Registered 8 Byte Dual-In-Line  
SDRAM Module for Workstation and Server  
main memory applications with 1,2inch  
(30,40 mm) height  
Programmable CAS Latency, Burst Length,  
and Wrap Sequence (Sequential &  
Interleave)  
All inputs and outputs are LVTTL compatible  
One bank 16M × 72, 32M x 72 and 64M × 72  
and two bank 128Mx72 organization  
Utilizes SDRAMs in TSOPII-54 packages  
with on-board registers and PLL.  
Optimized for ECC applications with very low  
input capacitances  
Card Sizes :  
RawCard Fand G133.35 mm x 30,40 with  
gold contact pads  
JEDEC standard Synchronous DRAMs  
(SDRAM) with 128Mb, 256Mb and  
512Mb memory density. Stacked  
components for two bank modules  
These modules all fully compatible with the  
current industry standard PC133  
specifications and fully backward compatible  
to PC100 applications  
Single + 3.3 V (± 0.3 V) power supply  
Auto Refresh (CBR) and Self Refresh  
Serial Presence Detect with E2PROM  
Performance:  
-7.5  
133  
5.4  
100  
6
Unit  
MHz  
ns  
fCK3  
tAC3  
fCK2  
tAC2  
Clock Frequency (max.) @ CL = 3  
Clock Access Time (min.)@ CL = 3  
Clock Frequency (max.) @ CL = 2  
Clock Access Time (min.)@ CL = 2  
MHz  
ns  
The HYS 72Vxx5/6x0GR-7.5 are industry standard 168-pin 8-byte Dual in-line Memory Modules (DIMMs)  
organized as 16M × 72, 32M x 72, 64M × 72 and 128M x 72 high speed memory arrays designed with x4 or x8  
organised Synchronous DRAMs (SDRAMs) for ECC applications. All control and address signals are registered  
on-DIMM and the design incorporates a PLL circuit for the Clock inputs. Use of an on-board register reduces  
capacitive loading on the input signals but are delayed by one cycle in arriving at the SDRAM devices. Decoupling  
capacitors are mounted on the PC board. The DIMMs use a serial presence detects scheme implemented via a  
serial E2PROM using the 2-pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the  
second 128 bytes are available to the end user. All Infineon 168-pin DIMMs provide a high performance, flexible  
8-byte interface in a 133.35 mm long footprint. This module family is designed with 30,40 mm (1.2 inch) maximum  
height for 1U Server Applications b ased on JEDEC standard RawCards “F” and “G”.  
INFINEON Technologies  
1
1.02  
HYS 72Vxx5/6x0GR-7.5  
Low Profile PC133 Registered SDRAM-Modules  
Ordering Information  
Type  
Compliance Code  
Description  
SDRAM  
Technology  
1.2” height:  
HYS 72V16600GR-7.5 PC133R-333-542-F one bank 128 MB Reg. DIMM 128 MBit (x8)  
HYS 72V32501GR-7.5 PC133R-333-542-G one bank 256 MB Reg. DIMM 128 MBit (x4)  
HYS 72V32600GR-7.5 PC133R-333-542-F one bank 256 MB Reg. DIMM 256 Mbit (x8)  
HYS 72V64500GR-7.5 PC133R-333-542-G one bank 512 MB Reg. DIMM 256 Mbit (x4)  
HYS 72V64601GR-7.5 PC133R-333-542-F one bank 512 MB Reg. DIMM 512 MBit (x8)  
HYS 72V128520GR-7.5 PC133R-333-542-G two banks 1024 MB Reg.  
DIMM  
256 Mbit (x4)  
stacked  
Note: All part numbers end with a place code (not shown), designating the die revision. Consult factory for  
current revision. Example: HYS 64V16600GR-7.5-C2, indicating Rev.C2 dies are used for SDRAM  
components.  
INFINEON Technologies  
2
1.02  
HYS 72Vxx5/6x0GR-7.5  
Low Profile PC133 Registered SDRAM-Modules  
Pin Definitions and Functions  
A0 - A11, A12 Address Inputs  
DQMB0 - DQMB7 Data Mask  
(A12 is used for 256Mbit and 512Mbit  
based modules only)  
BA0, BA1  
Bank Selects  
CS0 - CS3  
REGE *)  
Chip Select  
Register Enable  
Hor N.C = registered mode  
L= buffered mode  
DQ0 - DQ63 Data Input/Output  
CB0 - CB7  
RAS  
Check Bits  
VDD  
VSS  
SCL  
SDA  
N.C.  
Power (+ 3.3 V)  
Ground  
Row Address Strobe  
Column Address Strobe  
Read/Write Input  
Clock Enable  
CAS  
Clock for Presence Detect  
Serial Data Out  
No Connection  
WE  
CKE0  
CLK0 - CLK3 Clock Input  
*) note : To confirm to this specification, motherboards must pull this pin to high state or no connect.  
Address Format  
Density Organization Memory SDRAMs # of  
# of row/bank/ Refresh Period Interval  
Banks  
SDRAMs columns bits  
128 MB 16M × 72  
256 MB 32M x 72  
256 MB 32M x 72  
512 MB 64M × 72  
512 MB 64M × 72  
1
1
1
1
1
2
16M x 8  
32M x 4  
32M x 8  
64M × 4  
64M × 8  
64M × 4  
9
12/2/10  
12/2/11  
13/2/10  
13/2/11  
13/2/12  
13/2/11  
4k  
4k  
8k  
8k  
8k  
8k  
64 ms 15.6 µs  
64 ms 15.6 µs  
64 ms 7.8 µs  
64 ms 7.8 µs  
64 ms 7.8 µs  
64 ms 7.8 µs  
18  
9
18  
9
1 GB  
128M x 72  
36  
INFINEON Technologies  
3
1.02  
HYS 72Vxx5/6x0GR-7.5  
Low Profile PC133 Registered SDRAM-Modules  
Pin Configuration  
PIN# Symbol  
PIN# Symbol  
PIN# Symbol  
PIN# Symbol  
1
VSS  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
VSS  
85  
VSS  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
157  
158  
159  
160  
161  
162  
163  
164  
165  
166  
167  
168  
VSS  
2
DQ0  
DQ1  
DQ2  
DQ3  
VDD  
DU  
86  
DQ32  
DQ33  
DQ34  
DQ35  
VDD  
CKE0  
CS3  
3
CS2  
87  
4
DQMB2  
DQMB3  
DU  
88  
DQMB6  
DQMB7  
N.C.  
5
89  
6
90  
7
DQ4  
DQ5  
DQ6  
DQ7  
DQ8  
VSS  
VDD  
91  
DQ36  
DQ37  
DQ38  
DQ39  
DQ40  
VSS  
VDD  
8
N.C.  
N.C.  
CB2  
92  
N.C.  
9
93  
N.C.  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
94  
CB6  
CB3  
95  
CB7  
VSS  
96  
VSS  
DQ9  
DQ10  
DQ11  
DQ12  
DQ13  
VDD  
DQ16  
DQ17  
DQ18  
DQ19  
VDD  
97  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
VDD  
DQ48  
DQ49  
DQ50  
DQ51  
VDD  
98  
99  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
DQ20  
N.C.  
DU  
DQ52  
N.C.  
DQ14  
DQ15  
CB0  
CB1  
VSS  
DQ46  
DQ47  
CB4  
CB5  
VSS  
DU  
N.C.  
VSS  
REGE  
VSS  
DQ21  
DQ22  
DQ23  
VSS  
DQ53  
DQ54  
DQ55  
VSS  
N.C.  
N.C.  
VDD  
N.C.  
N.C.  
VDD  
WE  
DQ24  
DQ25  
DQ26  
DQ27  
VDD  
CAS  
DQMB4  
DQMB5  
CS1  
RAS  
VSS  
DQ56  
DQ57  
DQ58  
DQ59  
VDD  
DQMB0  
DQMB1  
CS0  
DU  
VSS  
DQ28  
DQ29  
DQ30  
DQ31  
VSS  
DQ60  
DQ61  
DQ62  
DQ63  
VSS  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
CLK2  
N.C.  
WP  
A9  
CLK3  
N.C.  
A10 (AP)  
BA1  
VDD  
BA0  
A11  
SA0  
SDA  
SCL  
VDD  
SA1  
VDD  
CLK1  
A12  
SA2  
CLK0  
VDD  
VDD  
INFINEON Technologies  
4
1.02  
HYS 72Vxx5/6x0GR-7.5  
Low Profile PC133 Registered SDRAM-Modules  
RCS0  
CS  
DQM  
DQ0-DQ7  
D0  
CS  
DQM  
RDQMB0  
DQ0-DQ7  
RDQMB4  
DQ32-DQ39  
DQ0-DQ7  
D4  
CS  
DQM  
DQ0-DQ7  
D1  
CS  
DQM  
DQ0-DQ7  
D5  
RDQMB1  
RDQMB5  
DQ8-DQ15  
DQ40-DQ47  
CS WE  
DQM  
DQ0-DQ7  
D8  
RCB0-RCB7  
RCS2  
CS  
DQM  
DQ0-DQ7  
D2  
CS  
DQM  
DQ0-DQ7  
D6  
RDQMB2  
RDQMB4  
DQ16-DQ23  
DQ48-DQ55  
CS  
DQM  
DQ0-DQ7  
D3  
CS  
DQM  
DQ0-DQ7  
D7  
RDQMB3  
RDQMB7  
DQ24-DQ31  
DQ56-DQ63  
E2PROM  
(256 word x 8 Bit)  
VCC  
VSS  
D0-D8, Reg., DLL  
D0-D8, Reg., DLL  
SA0  
SA1  
SA2  
SCL  
SA0  
SA1 SDA  
C
SA2  
SCL  
WP  
47 k  
CLK0  
12 pF  
PLL  
SDRAMs D0-D8  
Notes:  
1)  
DQ wirding may differ from that  
decribed in this drawing;  
however DQ/DQB relationship  
CS0/CS2  
DQMB0-7  
BA0, BA1  
A0-A11,12*)  
RAS  
CAS  
CKE0  
WE  
RCS0/RCS2  
RDQMB0-7  
RBA0, RBA1  
RA0-11,12  
RRAS  
RCAS  
RCKE0  
RWE  
SDRAMs D0-D8  
SDRAMs D0-D8  
SDRAMs D0-D8  
SDRAMs D0-D8  
SDRAMs D0-D8  
SDRAMs D0-D8  
must be maintained as shown  
2)  
All resistors are 10 unless  
otherwise noted  
A12 is only for 32 M x 72 & 64Mx72  
organisation  
)
*
CLK1, CLK2, CLK3  
REGE  
12 pF  
10 k  
VCC  
reg_1U_1  
Block Diagram: One Bank 16M x72, 32M x 72 and 64M × 72 Modules  
HYS72V16600, HYS72V32600 & HYS72V64601GR using x8 organized SDRAMs (RawCard F)  
INFINEON Technologies  
5
1.02  
HYS 72Vxx5/6x0GR-7.5  
Low Profile PC133 Registered SDRAM-Modules  
RCS0  
RDQMB0  
RDQMB4  
DQM  
CS  
DQM  
CS  
DQ0-DQ3  
DQ4-DQ7  
DQ32-DQ35  
DQ0-DQ3  
DQ0-DQ3  
D0  
D8  
DQM  
CS  
DQM  
CS  
DQ36-DQ39  
DQ0-DQ3  
DQ0-DQ3  
D1  
D9  
RDQMB1  
RDQMB5  
DQM  
DQM  
CS  
DQ8-DQ11  
DQ40-DQ43  
DQ0-DQ3  
DQ0-DQ3  
D2  
D3  
D10  
DQM  
CS  
DQ0-DQ3  
DQM  
CS  
DQ12-DQ15  
CB0-CB3  
DQ44-DQ47  
CB4-CB7  
DQ0-DQ3  
D11  
DQM  
CS  
DQM  
CS  
DQ0-DQ3  
D17  
DQ0-DQ3  
D16  
RCS2  
RDQMB2  
RDQMB6  
DQM  
DQ0-DQ3  
CS  
DQM  
DQ0-DQ3  
D12  
CS  
DQ16-DQ19  
DQ20-DQ23  
DQ48-DQ51  
D4  
DQM  
CS  
DQ0-DQ3  
DQM  
DQ0-DQ3  
D13  
CS  
DQ52-DQ55  
D5  
RDQMB3  
RDQMB7  
DQM  
CS  
DQ0-DQ3  
DQM  
DQ0-DQ3  
D14  
CS  
DQ24-DQ27  
DQ56-DQ59  
D6  
DQM  
CS  
DQ0-DQ3  
DQM  
CS  
DQ0-DQ3  
D15  
DQ28-DQ31  
DQ60-DQ63  
D7  
E2PROM  
(256 word x 8 Bit)  
CLK0  
12 pF  
PLL  
SDRAMs D0-D17  
CLK1, CLK2, CLK3  
SA0  
SA1  
SA2  
SCL  
SA0  
SA1 SDA  
SA2  
SCL  
12 pF  
CS0/CS2  
DQMB0-7  
BA0, BA1  
A0-A11, A12  
RAS  
CAS  
CKE0  
WE  
RCS0/RCS2  
WP  
RDQMB0-7  
RBA0, RBA1  
RA0-RA11, RA12  
RRAS  
RCAS  
RCKE0  
SDRAMs D0-D17  
SDRAMs D0-D17  
SDRAMs D0-D17  
SDRAMs D0-D17  
SDRAMs D0-D17  
SDRAMs D0-D17  
47 k  
VCC  
VSS  
D0-D17, Reg., DLL  
D0-D17, Reg., DLL  
C
RWE  
REGE  
1) DQ wirding may differ from that decribed  
in this drawing; however DQ/DQB relationship  
must be maintained as shown  
10 kΩ  
VCC  
2) All resistors are 10 unless otherwise noted  
SPB04135  
Block Diagram: One Bank 32M x 72 and 64M x 72 Modules  
HYS72V32501GR and HYS72V64500GR with x4 components (RawCard G)  
INFINEON Technologies  
6
1.02  
HYS 72Vxx5/6x0GR-7.5  
Low Profile PC133 Registered SDRAM-Modules  
RCS0  
RCS1  
RDQMB0  
RDQMB4  
DQM  
CS DQM  
CS  
DQM CS  
DQ0-DQ3  
DQM  
CS  
DQ0-DQ3  
DQ0-DQ3  
DQ4-DQ7  
DQ32-DQ35  
DQ0-DQ3  
DQ0-DQ3  
D0  
D0  
CS  
D8  
D8  
DQM  
DQ0-DQ3  
CS DQM  
DQ0-DQ3  
DQM CS  
DQ0-DQ3  
DQM  
DQ0-DQ3  
CS  
DQ36-DQ39  
D1  
D1  
D9  
D9  
RDQMB1  
RDQMB5  
DQM  
DQ0-DQ3  
CS DQM  
DQ0-DQ3  
CS  
DQM CS  
DQ0-DQ3  
DQM  
DQ0-DQ3  
CS  
DQ8-DQ11  
DQ40-DQ43  
D2  
D2  
D10  
D10  
DQM  
CS DQM  
DQ0-DQ3 DQ0-DQ3  
CS  
DQM CS  
DQ0-DQ3  
DQM  
CS  
DQ0-DQ3  
DQ12-DQ15  
CB0-CB3  
DQ44-DQ47  
CB4-CB7  
D3  
D3  
D11  
D11  
DQM  
CS DQM  
DQ0-DQ3 DQ0-DQ3  
CS  
DQM CS  
DQ0-DQ3  
DQM  
DQ0-DQ3  
D17  
CS  
D16  
D16  
D17  
RCS2  
RCS3  
RDQMB2  
RDQMB6  
DQM  
DQ0-DQ3  
CS DQM  
CS  
DQM CS  
DQ0-DQ3  
DQM  
DQ0-DQ3  
D12  
CS  
DQ16-DQ19  
DQ48-DQ51  
DQ0-DQ3  
D4  
D4  
D12  
DQM  
DQ0-DQ3  
CS DQM  
DQ0-DQ3  
CS  
DQM CS  
DQ0-DQ3  
DQM  
CS  
DQ0-DQ3  
D13  
DQ20-DQ23  
DQ52-DQ55  
D5  
D5  
D13  
RDQMB3  
RDQMB7  
DQM  
DQ0-DQ3  
CS DQM  
DQ0-DQ3  
CS  
DQM CS  
DQ0-DQ3  
DQM  
DQ0-DQ3  
D14  
CS  
DQ24-DQ27  
DQ56-DQ59  
D6  
D6  
D14  
DQM  
DQ0-DQ3  
CS DQM  
DQ0-DQ3  
CS  
DQM CS  
DQ0-DQ3  
DQM  
DQ0-DQ3  
CS  
DQ28-DQ31  
DQ61-DQ63  
D7  
D7  
D15  
D15  
E2PROM  
(256 word x 8 Bit)  
CLK0  
12 pF  
PLL  
Stacked SDRAMs D0-D17  
CLK1, CLK2, CLK3  
SA0  
SA1  
SA2  
SCL  
SA0  
SA1 SDA  
SA2  
SCL  
12 pF  
CS0-CS3  
DQMB0-7  
BA0, BA1  
A0-A11, A12* )  
RAS  
CAS  
CKE0  
WE  
RCS0-RCS3  
WP  
RDQMB0-7  
RBA0, RBA1  
RA0-RA11  
RRAS  
RCAS  
RCKE0  
Stacked SDRAMs D0-D17  
Stacked SDRAMs D0-D17  
Stacked SDRAMs D0-D17  
Stacked SDRAMs D0-D17  
Stacked SDRAMs D0-D17  
Stacked SDRAMs D0-D17  
47 k  
VCC  
VSS  
D0-D17, Reg. DLL  
D0-D17, Reg. DLL  
C
RWE  
REGE  
1.) DQ wirding may differ from that decribed  
*) A12 is only used for  
128 M x 72 organisation  
10 k  
in this drawing; however DQ/DQB relationship  
must be maintained as shown  
VCC  
2.) All resistors are 10  
unless otherwise noted  
SPB04136  
Block Diagram: Two Bank 128M x 72 Modules HYS72V128520GR with x4 components  
(RawCard G)  
INFINEON Technologies  
7
1.02  
HYS 72Vxx5/6x0GR-7.5  
Low Profile PC133 Registered SDRAM-Modules  
Absolute Maximum Ratings  
Parameter  
Symbol  
Limit Values  
max.  
Unit  
min.  
VIN, VOUT 1.0  
Input / Output voltage relative to VSS  
Power supply voltage on VDD  
V
4.6  
VDD  
TSTG  
PD  
1.0  
4.6  
+150  
1
V
Storage temperature range  
-55  
oC  
W
mA  
Power dissipation (per SDRAM component)  
Data out current (short circuit)  
IOS  
50  
Permanent device damage may occur if Absolute Maximum Ratingsare exceeded.  
Functional operation should be restricted to recommended operation conditions.  
Exposure to higher than recommended voltage for extended periods of time affect device reliability  
DC Characteristics  
TA = 0 to 70 °C 1); VSS = 0 V; VDD = 3.3 V ± 0.3 V  
Parameter  
Symbol  
Limit Values  
max.  
Unit  
min.  
2.0  
Input High Voltage  
VIH  
VIL  
V
DD + 0.3  
V
Input Low Voltage  
0.5  
2.4  
0.8  
V
Output High Voltage (IOUT = 4.0 mA)  
Output Low Voltage (IOUT = 4.0 mA)  
VOH  
VOL  
II(L)  
V
0.4  
10  
V
Input Leakage Current, any input  
10  
µA  
(0 V < VIN < 3.6 V, all other inputs = 0 V)  
Output Leakage Current  
IO(L)  
10  
10  
µA  
(DQ is disabled, 0 V < VOUT < VDD  
)
Capacitance  
TA = 0 to 70 °C 1); VDD = 3.3 V ± 0.3 V, f = 1 MHz  
Parameter  
Symbol  
Limit Values  
Unit  
One Bank TwoBank  
Modules Modules  
Input Capacitance  
CIN  
10  
20  
pF  
(all inputs except CLK and CKE)  
Input Capacitance (CLK)  
Input Capacitance (CKE)  
CCLK  
CCKE  
CIO  
30  
17  
10  
30  
30  
17  
pF  
pF  
pF  
Input/Output Capacitance  
(DQ0 - DQ63, CB0 - CB7)  
Input Capacitance (SCL, SA0 - 2)  
Input/Output Capacitance (SDA)  
CSC  
CSD  
8
8
8
8
pF  
pF  
INFINEON Technologies  
8
1.02  
HYS 72Vxx5/6x0GR-7.5  
Low Profile PC133 Registered SDRAM-Modules  
Operating Currents per SDRAM Component  
TA = 0 to 70 °C 1), VDD = 3.3 V ± 0.3 V  
(Recommended Operating Conditions unless otherwise noted)  
Parameter  
Test Condition Symbol 128Mb 256Mb 512 Mb Unit Note  
max.  
2)  
Operating current  
tRC = tRC(MIN.), tCK = tCK(MIN.)  
160  
230  
270  
mA  
ICC1  
Outputs open, Burst Length = 4,  
CL = 3. All banks operated in  
random access, all banks  
operated in ping-pong manner  
to maximize gapless data  
access  
2)  
2)  
Precharge stand-by current  
in Power Down Mode  
t
CK = min.  
ICC2P  
1.5  
40  
2
4
mA  
mA  
CS = VIH(MIN.), CKE VIL(MAX.)  
Precharge Stand-by Current  
in Non-Power Down Mode  
tCK = min.  
ICC2N  
40  
36  
CS = VIH (MIN.), CKE VIH(MIN.)  
2)  
2)  
No operating current  
CKE VIH(MIN.) ICC3N  
CKE VIL(MAX.) ICC3P  
50  
10  
50  
10  
35  
11  
mA  
mA  
tCK = min., CS = VIH(MIN.),  
active state (max. 4 banks)  
2), 3)  
Burst operating current  
ICC4  
ICC5  
ICC6  
tCK = min.,  
100  
230  
150  
240  
255  
440  
mA  
mA  
Read command cycling  
2)  
Auto refresh current  
tCK = min.,  
Auto Refresh command cycling  
2)  
Self refresh current  
1.5  
3
4
mA  
Self Refresh Mode,CKE = 0.2 V  
INFINEON Technologies  
9
1.02  
HYS 72Vxx5/6x0GR-7.5  
Low Profile PC133 Registered SDRAM-Modules  
4), 5)  
AC Characteristics (SDRAM Device Specification)  
TA = 0 to 70 °C 1); VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns  
Parameter  
Symbol  
Limit Values  
-7.5  
Unit Note  
min.  
max.  
Clock and Access Time  
Clock Cycle Time  
tCK  
fCK  
tAC  
CAS Latency = 3  
CAS Latency = 2  
7.5  
10  
ns  
ns  
Clock Frequency  
MHz  
CAS Latency = 3  
CAS Latency = 2  
133  
100  
MHz  
Access Time from Clock  
CAS Latency = 3  
CAS Latency = 2  
5.4  
6
ns  
ns  
Clock High Pulse Width  
Clock Low Pulse Width  
Transition Time  
tCH  
tCL  
tT  
2.5  
2.5  
0.5  
ns  
ns  
ns  
10  
Setup and Hold Parameters  
Input Setup Time  
tIS  
1.5  
0.8  
1
ns  
Input Hold Time  
tIH  
ns  
Power Down Mode Entry Time  
Power Down Mode Exit Setup Time  
Mode Register Setup Time  
tSB  
tPDE  
tRCS  
CLK  
CLK  
CLK  
1
2
Common Parameters  
Row to Column Delay Time  
Row Precharge Time  
tRCD  
tRP  
tRAS  
tRC  
tRRD  
tCCD  
20  
20  
45  
ns  
ns  
Row Active Time  
100k  
ns  
Row Cycle Time  
67.5  
2
ns  
Activate (a) to Activate (b) Command Period  
CAS(a) to CAS(b) Command Period  
CLK  
CLK  
1
INFINEON Technologies  
10  
1.02  
HYS 72Vxx5/6x0GR-7.5  
Low Profile PC133 Registered SDRAM-Modules  
AC Characteristics (SDRAM Device Specification) (contd) 4), 5)  
TA = 0 to 70 °C 1); VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns  
Parameter  
Symbol  
Limit Values  
-7.5  
Unit Note  
min.  
max.  
Refresh Cycle  
Refresh Period  
tREF  
µs  
µs  
128MBit SDRAM Based Modules  
256 & 512MBit SDRAM Based Modules  
Self Refresh Exit Time  
15.6  
7.8  
6)  
tSREX  
1
CLK  
Read Cycle  
Data Out Hold Time  
tOH  
tLZ  
3
0
3
7
2
ns  
7)  
Data Out to Low Impedance Time  
Data Out to High Impedance Time  
DQM Data Out Disable Latency  
ns  
7)  
tHZ  
ns  
tDQZ  
CLK  
Write Cycle  
Data Input to Precharge  
(write recovery)  
tWR  
2
0
CLK  
CLK  
DQM Write Mask Latency  
tDQW  
INFINEON Technologies  
11  
1.02  
HYS 72Vxx5/6x0GR-7.5  
Low Profile PC133 Registered SDRAM-Modules  
Notes  
1. The registered DIMM modules are designed to operate under system operating conditions  
between 0-55 deg C ambient, maximum sustained bandwidth and 0 LFM airflow. Operating at  
higher ambient temperatures needs sufficient air flow to limit the case temperature of the  
SDRAM components do not exceed 85oC.  
2. These parameters depend on the cycle rate. All values are measured at 133 MHz operation  
frequency. Input signals are changed once during tck excepts for Icc6 and for standby currents  
when tck = infinity.  
3. These parameters are measured with continous data stream during read access and all DQ  
toggling. CL=3 and BL=4 is assumed and the data-out current is excluded.  
4. An initial pause of 100 µs is required after power-up. Then a Precharge All Banks command must  
be given followed by eight Auto Refresh (CBR) cycles before the Mode Register Set Operation  
can begin. Also the on-DIMM PLL must be given enough clock cycles to stabilize (tSTAB) before  
any operation can be guaranteed.  
5. AC timing tests have VIL = 0.8 V and VIH = 2.0 V with the timing referenced to the 1.4 V crossover  
point. The transition time is measured between VIH and VIL. All AC measurements assume  
tT = 1 ns with the AC output load circuit shown. Specified tAC and tOH parameters are measured  
with a 50 pF only, without any resistive termination and with a input signal of 1 V/ns edge rate  
between 0.8 V and 2.0 V.  
6. Self Refresh Exit is a synchronous operation and begins on the second positive clock edge after  
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied  
after the Self Refresh Exit command is registered.  
7. Referenced to the time at which the output achieves the open circuit condition, not to output  
voltage levels.  
tCH  
2.4 V  
0.4 V  
CLOCK  
tT  
tCL  
tHOLD  
tSETUP  
INPUT  
1.4 V  
tAC  
tAC  
I/O  
tLZ  
tOH  
50 pF  
OUTPUT  
1.4 V  
Measurement conditions for  
AC and tOH  
tHZ  
t
SPT03404  
Serial Presence Detect  
A serial presence detect storage device - E2PROM 34C02 - is assembled onto the module.  
Information about the module configuration, speed, etc. is written into the E2PROM device during  
module production using a serial presence detect protocol (I2C synchronous 2-wire bus).  
INFINEON Technologies  
12  
1.02  
HYS 72Vxx5/6x0GR-7.5  
Low Profile PC133 Registered SDRAM-Modules  
SPD-Table for -7.5 Registered DIMM Modules  
Byte# Description  
SPD  
Hex  
Entry  
Value  
0
Number of SPD Bytes  
Total Bytes in Serial PD  
Memory Type  
128  
80  
08  
1
2
256  
SDRAM  
04  
0D  
0B  
01  
3
4
5
Number of Row Addresses )  
Number of Column Addresses  
Number of DIMM Banks  
12/13  
10/11/12  
1,2  
0C  
0A  
01  
0C  
0B  
01  
0D  
0A  
01  
0D  
0A  
02  
0D  
0C  
01  
0D  
0B  
02  
6
Module Data Width  
72  
48  
00  
01  
75  
54  
02  
82  
04  
04  
01  
0F  
04  
06  
01  
01  
1F  
7
Module Data Width (contd)  
Module Interface Levels  
Cycle Time at CL = 3  
0
8
LVTTL  
7.5 ns  
5.4 ns  
ECC  
15.6/7.8 µs  
x4, x8  
x4, x8  
1 CLK  
1, 2, 4, 8  
4
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
Access Time from Clock at CL = 3  
DIMM Config (Error Det/Corr.)  
Refresh Rate/Type  
80  
08  
08  
80  
04  
04  
82  
08  
08  
82  
08  
08  
82  
08  
08  
82  
04  
04  
SDRAM Width, Primary  
Error Checking SDRAM Data Width  
Minimum tCCD  
Burst Length Supported  
Number of SDRAM Banks  
SDRAM Supported CAS Latencies  
SDRAM CS Latencies  
2 & 3  
0
SDRAM WE Latencies  
0
SDRAM DIMM Module Attributes  
Registered  
with PLL  
22  
SDRAM Device Attributes  
VDD tol +/–  
0E  
10%  
23  
24  
Min. Clock Cycle Time at CL = 2  
10 ns  
6.0  
A0  
60  
Max. Access Time from Clock for  
CL = 2  
25  
26  
Min. Clock Cycle Time at CL = 1  
not  
supported  
00  
00  
Max. Access Time from Clock at  
CL = 1  
not supp.  
27  
28  
29  
30  
31  
SDRAM Minimum tRP  
20 ns  
15 ns  
20 ns  
45 ns  
14  
0F  
14  
2D  
SDRAM Minimum tRRD  
SDRAM Minimum tRCD  
SDRAM Minimum tRAS  
Module Bank Density (per bank)  
128 M/  
256M/  
20  
40  
40  
80  
40  
80  
80  
512 MB  
32  
33  
34  
SDRAM Input Setup Time  
SDRAM Input Hold Time  
1.5 ns  
0.8 ns  
1.5 ns  
15  
08  
15  
SDRAM Data Input Setup Time  
INFINEON Technologies  
13  
1.02  
HYS 72Vxx5/6x0GR-7.5  
Low Profile PC133 Registered SDRAM-Modules  
SPD-Table for -7.5 Registered DIMM Modules (contd)  
Byte# Description  
SPD  
Hex  
Entry  
Value  
35  
SDRAM Data Input Hold Time  
0.8 ns  
08  
00  
36-61  
Superset Information(may be used in  
future)  
62  
SPD Revision  
JEDEC 2  
12  
BC  
63  
Checksum for Bytes 0 - 62  
Manufacturers JEDEC ID Code  
Manufacturer  
60  
79  
83  
84  
BD  
BD  
64  
C1  
65-71  
72  
INFINEO(N)  
Module Assembly Location  
Module Part Number  
Module Revision Code  
Module Manufacturing Date  
Module Serial Number  
73-90  
91-92  
93-94  
95-98  
99-125  
126  
Frequency Specification  
Details of Clocks  
64  
8F  
127  
128-  
255  
Open for Customer Use  
Note: 1) HYS72V32501GR-7.5 (128Mbit x4 based), 2) HYS72V32600GR-7.5 (256Mbit x8 based)  
*) HYS72V64500GR-7.5 (256Mbit based) **) HYS72V64601GR-7.5 (512Mbit based)  
INFINEON Technologies  
14  
1.02  
HYS 72Vxx5/6x0GR-7.5  
Low Profile PC133 Registered SDRAM-Modules  
Package Outlines Raw Card F  
Module Package  
JEDEC MO-161  
Registered DIMM Modules (Raw Card F) L-DIM168-51  
128MB, 256MB & 512MB modules based on x8 SDRAM components  
±
0.15  
133.35  
127.35  
Register  
42.18  
Register  
PLL  
3
1
10  
11  
6.35  
40  
41  
6.35  
84  
3
1.27  
66.68  
2
85 94  
95  
124 125  
168  
non-stacked:  
stacked:  
6.8 max.  
4 max.  
Detail of Contacts  
1+0.5  
1.27±  
1.27±  
0.1  
0.1  
1.27  
note: all outline dimensions and tolerances are in accordance with the JEDEC standard  
INFINEON Technologies  
15  
1.02  
HYS 72Vxx5/6x0GR-7.5  
Low Profile PC133 Registered SDRAM-Modules  
Package Outlines Raw Card G  
Module Package  
JEDEC MO-161  
Registered DIMM Modules (Raw Card G) L-DIM168-52  
±
0.15  
133.35  
127.35  
Register  
Register  
3
1
10  
11  
6.35  
40  
41  
6.35  
84  
3
1.27  
42.18  
66.68  
2
85 94  
95  
124 125  
168  
Register  
PLL  
non-stacked:  
4 max.  
stacked:  
6.8 max.  
Detail of Contacts  
1+0.5  
1.27±  
1.27±  
0.1  
0.1  
1.27  
L-DIM-168-52  
note: all outline dimensions and tolerances are in accordance with the JEDEC standard  
INFINEON Technologies  
16  
1.02  
HYS 72Vxx5/6x0GR-7.5  
Low Profile PC133 Registered SDRAM-Modules  
Functional Description  
All these PC133 168-pin Registered DIMMs conform to a compatible set of timing and operation  
characteristics intended to comply with the 133 MHz standards. The Registered DIMMs achieve  
high speed data transfer rate up to 133 MHz, when in registered mode. The registered modeis  
achieved when the REGE input signal is in highstate or the pin is not connected. Operation in  
buffered mode(REGE = low) needs careful system design to compensate all input signals for the  
extra delay time of the register components when in buffered mode. Buffered modeis limited to  
66 Mhz operation and is beyond the scope of this datasheet.  
Registered Mode:  
All control and address signals are synchronized with the positive edge of externally supplied clocks  
and are registered on-DIMM and hence delayed by one clock cycle in arriving at the SDRAM  
devices. The use of the on-board register reduces the capacitive loading of the DIMM on input  
control and address signals. The SDRAM device data lines (DQ) are connected directly to the DIMM  
tabs through 10 Ohm series resistors. All the following timing diagrams and explanations show  
DIMM operation at the tabs, not SDRAM operation.  
The picture below depicts an overview of the effect of the Registered Mode on the data outputs  
(DQs) for a Read operation. Without the registers, the data is delayed according to the device CAS  
latency, in the case two clocks. With the register, the data is delayed according to the device CAS  
latency plus an additional clock cycle. This is known as the DIMM CAS latency, and in this example  
is four three. The data path can be thought of as a pipeline in which the register effectively lengthens  
the pipe by one clock cycle.  
Registered DIMM Burst Read Operation (BL = 4)  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
CLK  
Command  
Read A  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
Device  
CAS latency = 2  
DOUT A0 DOUT A1 DOUT A2 DOUT A3  
t
CK2, DQs  
DIMM  
CAS latency = 3  
DOUT A0 DOUT A1 DOUT A2 DOUT A3  
Added for on-DIMM pipeline register  
t
CK3, DQs  
One Clock  
Reg-DIMM Latency = 1  
SPT03968  
In case of a Burst Write Command the data-in is delayed one clock due the op-DIMM pipeline  
register also. Therefore, data for the first Burst Write cycle must be applied on the DQ pins on the  
next clock cycle after the Write command is issued. the remaining data inputs must be supplied on  
INFINEON Technologies  
17  
1.02  
HYS 72Vxx5/6x0GR-7.5  
Low Profile PC133 Registered SDRAM-Modules  
each subsequent rising clock edge until the burst length is completed. When the burst has finished,  
any additional data supplied to the DQ pins will be ignored.  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
CLK  
Command  
DQs  
NOP  
Write A  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
dont care  
DIN A0  
DIN A1  
DIN A2  
DIN A3  
The first data element and the Write  
are registered on the next clock edge  
Reg-DIMM Latency = 1 CLK  
Extra data is ignored after  
termination of a Burst.  
SPT03969  
Registered DIMM Burst Write Operation (BL = 4)  
INFINEON Technologies  
18  
1.02  
HYS 72Vxx5/6x0GR-7.5  
Low Profile PC133 Registered SDRAM-Modules  
INFINEON Technologies  
19  
1.02  
HYS 72Vxx5/6x0GR-7.5  
Low Profile PC133 Registered SDRAM-Modules  
Change List  
12.00  
Rev. 0.1  
Rev. 0.1  
Rev. 0.1  
First revision  
18.1.2001  
23.1.2001  
Clarification of buffered modeoperation (not tested)  
Height reduced from 1.2(nominal) to 1.155(max) according to the  
lastest IBM drawings for RawCard F  
12.02.2001  
19.02.2001  
27.02.2001  
04.04.2001  
11.04.2001  
Rev.0.2  
Rev. 0.3  
Rev. 0.4  
Rev. 0.5  
Rev. 0.5b  
PM decided to stay with 1.2inch height  
New PCB L-DIM-168-56 with 1.125height  
Both Gerber Files (1,125and 1.2) are now in the target datasheet  
x4 based modules on L-DIM-168-52 added  
Info from Mr. Pammer AIT Rgb: L-DIM-168-51 is based on Raw Card A and  
L-DIM-168-52 is based on Raw Card B  
Block Diagram for stacked x8 module changed for use of x8 stacks with one  
CKE and two CS  
29.05.2001  
21.06.2001  
28.06.2001  
Rev. 0.6  
Rev. 0.7  
Rev. 0.8  
HYS72V32501GR-7.5 (128Mbit x4 based 256MByte) added  
Outline Drawings changed to L-DIM-168-51,52 & 56  
Product Marketing Decision : Remove all 1,125inch modules  
Datasheet changed from targetto preliminary”  
RawCards and therefore the Compliance Code changed according to  
JEDEC naming conventions, RawCard F for x8 and RawCard G for x4 (non-  
stackd and stacked)  
06.09.2001  
17.12.2001  
Rev. 0.9  
Final 1.0  
SCR: Thickness of modules changed from 4 to 4 max and 6.4 to 6.8 max  
SCR-028-2001-11-12 PC133 / TPCR_08 / JC42.5 Item 1138.5 :  
JEDEC changed Byte 62h (SPD Revision) from 02h to 12h  
Checksum changed therefore also  
INFINEON Technologies  
20  
1.02  
厂商 型号 描述 页数 下载

INFINEON

HYS64-72V2200GU-8 3.3V 2M ×64 /72- 1位BANK SDRAM模块3.3V 4M ×64 /72- 2位BANK SDRAM模块[ 3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module ] 17 页

INFINEON

HYS64-74V8200GU 3.3 V 8M ×64 /72- 1位银行SDRAM模块3.3 V 16M ×64 /72- 2位银行SDRAM模块[ 3.3 V 8M x 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M x 64/72-Bit 2 Bank SDRAM Module ] 17 页

INFINEON

HYS6472V16200GU 3.3 V 16M ×64 /72-位SDRAM模块3.3 V 32M ×64 /72-位SDRAM模块3.3 V 64M ×64 /72-位SDRAM模块[ 3.3 V 16M x 64/72-Bit SDRAM Modules 3.3 V 32M x 64/72-Bit SDRAM Modules 3.3 V 64M x 64/72-Bit SDRAM Modules ] 17 页

INFINEON

HYS6472V4200GU 3.3V 4M ×64 /72- 1位BANK SDRAM模块3.3V 8M ×64 /72- 2位BANK SDRAM模块[ 3.3V 4M x 64/72-Bit 1 BANK SDRAM Module 3.3V 8M x 64/72-Bit 2 BANK SDRAM Module ] 15 页

INFINEON

HYS64D128020GBDL-6-A [ DDR DRAM Module, 128MX64, 0.7ns, CMOS, SO-DIMM-200 ] 11 页

ETC

HYS64D128020GBDL-7-A ? 1GB ( 1024Mx64 ) PC2100 2银行?\n[ ?1GB (1024Mx64) PC2100 2-bank? ] 11 页

INFINEON

HYS64D128020GU-7-A 2.5 V 184针无缓冲DDR- SDRAM我模块[ 2.5 V 184-pin Unbuffered DDR-I SDRAM Modules ] 18 页

INFINEON

HYS64D128020GU-8-A 2.5 V 184针无缓冲DDR- SDRAM我模块[ 2.5 V 184-pin Unbuffered DDR-I SDRAM Modules ] 18 页

QIMONDA

HYS64D128020GU-8-A [ DDR DRAM Module, 128MX64, 0.8ns, CMOS, PDMA184 ] 18 页

INFINEON

HYS64D128021 200针的小型双列直插式内存模块[ 200-Pin Small Outline Dual-In-Line Memory Modules ] 23 页

PDF索引:

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

IC型号索引:

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

Copyright 2024 gkzhan.com Al Rights Reserved 京ICP备06008810号-21 京

0.235704s