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8N3SV75LG-1118CDI8

型号：

8N3SV75LG-1118CDI8

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

19 页

PDF大小：

915 K

下载PDF手册
LVPECL Frequency-Programmable VCXO  
IDT8N3SV75  
DATA SHEET  
General Description  
Features  
The IDT8N3SV75 is a LVPECL Frequency-Programmable VCXO  
with very flexible frequency and pull-range programming capabilities.  
The device uses IDT’s fourth generation FemtoClock® NG  
technology for an optimum of high clock frequency and low phase  
noise performance. The device accepts 2.5V or 3.3V supply and is  
packaged in a small, lead-free (RoHS 6) 6-lead ceramic 5mm x 7mm  
x 1.55mm package.  
• Fourth generation FemtoClock® NG technology  
• Programmable clock output frequency from 15.476MHz to  
866.67MHz and from 975MHz to 1,300MHz  
• Frequency programming resolution is 218Hz and better  
• Factory-programmable VCXO pull range and control voltage  
polarity  
• Absolute pull range (APR) programmable from typical 4.5 to  
The device can be factory-programmed to any frequency in the  
range of 15.476MHz to 866.67MHz and from 975MHz to 1,300MHz  
to the very high degree of frequency precision of 218Hz or better.  
The extended temperature range supports wireless infrastructure,  
telecommunication and networking end equipment requirements.  
754.5ppm  
• One 2.5V/3.3V LVPECL clock output  
• Output enable control input, LVCMOS/LVTTL compatible  
• RMS phase jitter @ 156.25MHz (12kHz - 20MHz): 0.5ps (typical),  
• 2.5V or 3.3V supply voltage  
• -40°C to 85°C ambient operating temperature  
• Lead-free (RoHS 6) 6-lead ceramic 5mm x 7mm x 1.55mm  
package  
Block Diagram  
Pin Assignment  
VC  
OE  
VEE  
1
2
3
6
5
4
VCC  
nQ  
Q
PFD  
&
LPF  
FemtoClock® NG  
VCO  
1950-2600MHz  
Q
nQ  
÷P  
OSC  
÷N  
IDT8N3SV75  
6-lead ceramic 5mm x 7mm x 1.55mm  
package body  
114.285 MHz  
2
÷MINT, MFRAC  
CD Package  
Top View  
A/D  
VC  
OE  
7
7
25  
Configuration Register (ROM)  
(Frequency, Pull-range, Polarity)  
Pullup  
IDT8N3SV75CCD REVISION A APRIL 26, 2012  
1
©2012 Integrated Device Technology, Inc.  
IDT8N3SV75 Data Sheet  
LVPECL-FREQUENCY PROGRAMMABLE VCXO  
Pin Description and Characteristic Tables  
Table 1. Pin Descriptions  
Number  
Name  
VC  
Type  
Description  
1
2
Input  
Input  
VCXO Control Voltage input.  
OE  
Pullup  
Output enable pin. See Table 3A for function. LVCMOS/LVTTL interface levels.  
Negative power supply.  
3
VEE  
Power  
Output  
Power  
4, 5  
Differential clock output. LVPECL interface levels.  
Q, nQ  
VCC  
6
Positive power supply.  
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.  
Table 2. Pin Characteristics  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
5.5  
Maximum  
Units  
pF  
OE  
VC  
CIN  
Input Capacitance  
Input Pullup Resistor  
10  
pF  
RPULLUP  
50  
kΩ  
Function Tables  
Table 3A. OE Configuration  
Input  
OE  
Output Enable  
0
Outputs Q, nQ are in high-impedance state.  
Outputs are enabled.  
1 (default)  
Table 3B. Output Frequency Range  
15.476MHz to 866.67MHz  
975MHz to 1,300MHz  
NOTE: Supported output frequency range. The output frequency can be programmed to any frequency in this range and to a precision of  
218Hz or better.  
IDT8N3SV75CCD REVISION A APRIL 26, 2012  
2
©2012 Integrated Device Technology, Inc.  
IDT8N3SV75 Data Sheet  
LVPECL-FREQUENCY PROGRAMMABLE VCXO  
Principles of Operation  
The block diagram consists of the internal 3rd overtone crystal and  
oscillator which provide the reference clock fXTAL of 114.285MHz.  
The PLL includes the FemtoClock® NG VCO along with the  
Pre-divider (P), the feedback divider (M) and the post divider (N). The  
P, M, and N dividers determine the output frequency based on the  
fXTAL reference. The feedback divider is fractional supporting a huge  
number of output frequencies. Internal registers are used to hold up  
the factory pre-set configuration setting. The P, M, and N frequency  
configurations support an output frequency range 15.476MHz to  
866.67MHz and 975MHz to 1,300MHz.  
Frequency Configuration  
An order code is assigned to each frequency configuration and the  
VCXO pull-range programmed by the factory (default frequencies).  
For more information on the available default frequencies and order  
codes, please see the Ordering Information Section in this document.  
For available order codes, see the FemtoClock NG Ceramic-Package  
XO and VCXO Ordering Product Information document.  
For more information on programming capabilities of the device for  
custom frequency and pull-range configurations, see the FemtoClock  
NG Ceramic 5x7 Module Programming Guide.  
The devices use the fractional feedback divider with a delta-sigma  
modulator for noise shaping and robust frequency synthesis  
capability. The relatively high reference frequency minimizes phase  
noise generated by frequency multiplication and allows more efficient  
shaping of noise by the delta-sigma modulator. The output frequency  
is determined by the 2-bit pre-divider (P), the feedback divider (M)  
and the 7-bit post divider (N). The feedback divider (M) consists of  
both a 7-bit integer portion (MINT) and an 18-bit fractional portion  
(MFRAC) and provides the means for high-resolution frequency  
generation. The output frequency fOUT is calculated by:  
1
MFRAC + 0.5  
------------  
f
= f  
⋅
⋅ MINT + -------------------------------------  
OUT  
XTAL  
P ⋅ N  
18  
2
IDT8N3SV75CCD REVISION A APRIL 26, 2012  
3
©2012 Integrated Device Technology, Inc.  
IDT8N3SV75 Data Sheet  
LVPECL-FREQUENCY PROGRAMMABLE VCXO  
Absolute Maximum Ratings  
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.  
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond  
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for  
extended periods may affect product reliability.  
Item  
Rating  
Supply Voltage, VCC  
Inputs, VI  
3.63V  
-0.5V to VCC + 0.5V  
Outputs, IO (LVPECL)  
Continuous Current  
Surge Current  
50mA  
100mA  
Package Thermal Impedance, θJA  
49.4°C/W (0 mps)  
-65°C to 150°C  
Storage Temperature, TSTG  
DC Electrical Characteristics  
Table 4A. Power Supply DC Characteristics, VCC = 3.3V 5%, VEE = 0V, TA = -40°C to 85°C  
Symbol  
VCC  
Parameter  
Test Conditions  
Minimum  
Typical  
3.3  
Maximum  
3.465  
Units  
V
Power Supply Voltage  
Power Supply Current  
3.135  
IEE  
130  
160  
mA  
Table 4B. Power Supply DC Characteristics, VCC = 2.5V 5%, VEE = 0V, TA = -40°C to 85°C  
Symbol  
VCC  
Parameter  
Test Conditions  
Minimum  
Typical  
2.5  
Maximum  
2.625  
Units  
V
Power Supply Voltage  
Power Supply Current  
2.375  
IEE  
120  
155  
mA  
Table 4C. LVPECL DC Characteristics, VCC = 3.3V 5%, VEE = 0V, TA = -40°C to 85°C  
Symbol  
VOH  
Parameter  
Test Conditions  
Minimum  
VCC – 1.4  
VCC – 2.0  
0.6  
Typical  
Maximum  
VCC – 0.8  
VCC – 1.7  
1.0  
Units  
Output High Voltage; NOTE 1  
Output Low Voltage; NOTE 1  
Peak-to-Peak Output Voltage Swing  
V
V
V
VOL  
VSWING  
NOTE 1: Outputs terminated with 50Ω to VCC – 2V.  
Table 4D. LVPECL DC Characteristics, VCC = 2.5V 5%, VEE = 0V, TA = -40°C to 85°C  
Symbol  
VOH  
Parameter  
Test Conditions  
Minimum  
VCC – 1.4  
VCC – 2.0  
0.4  
Typical  
Maximum  
VCC – 0.8  
VCC – 1.5  
1.0  
Units  
Output High Voltage; NOTE 1  
Output Low Voltage; NOTE 1  
Peak-to-Peak Output Voltage Swing  
V
V
V
VOL  
VSWING  
NOTE 1: Outputs terminated with 50Ω to VCC – 2V.  
IDT8N3SV75CCD REVISION A APRIL 26, 2012  
4
©2012 Integrated Device Technology, Inc.  
IDT8N3SV75 Data Sheet  
LVPECL-FREQUENCY PROGRAMMABLE VCXO  
Table 4E. LVCMOS/LVTTL DC Characteristic, VCC = 3.3V 5% or 2.5V 5%, VEE = 0V, TA = -40°C to 85°C  
Symbol  
Parameter  
Test Conditions  
VCC = 3.3V  
Minimum  
Typical  
Maximum  
VCC + 0.3  
VCC + 0.3  
0.8  
Units  
V
2
VIH  
Input High Voltage  
VCC = 2.5V  
1.7  
-0.3  
-0.3  
V
V
CC = VIN = 3.465V  
CC = VIN = 2.5V  
V
VIL  
Input Low Voltage  
V
0.7  
V
IIH  
IIL  
Input High Current  
Input Low Current  
OE  
OE  
VCC = VIN = 3.465V or 2.625V  
5
µA  
µA  
VCC = 3.465V or 2.625V, VIN = 0V  
-150  
IDT8N3SV75CCD REVISION A APRIL 26, 2012  
5
©2012 Integrated Device Technology, Inc.  
IDT8N3SV75 Data Sheet  
LVPECL-FREQUENCY PROGRAMMABLE VCXO  
AC Electrical Characteristics  
Table 5A. AC Characteristics, VCC = 3.3V 5% or 2.5V 5%, VEE = 0V, TA = -40°C to 85°C  
Symbol  
fOUT  
fI  
Parameter  
Test Conditions  
Minimum  
15.476  
975  
Typical  
Maximum  
Units  
MHz  
MHz  
ppm  
ppm  
ppm  
ppm  
ppm  
ppm  
ppm  
ppm  
ppm  
ps  
866.67  
1,300  
10  
Output Frequency Q, nQ  
Initial Accuracy  
Measured @ 25°C, VC = VCC/2  
Option code = A or B  
100  
50  
fS  
fA  
fT  
Temperature Stability  
Aging  
Option code = E or F  
Option code = K or L  
20  
Frequency drift over 10 year life  
Frequency drift over 15 year life  
Option code A, B (10 year life)  
Option code E, F (10 year life)  
Option code K, L (10 year life)  
3
5
113  
63  
Total Stability  
33  
tjit(cc)  
Cycle-to-Cycle Jitter; NOTE 1  
Period Jitter; NOTE 1  
6
12  
tjit(per)  
1.8  
2.8  
ps  
RMS Phase Jitter (Random);  
NOTE 2, 3  
156.25MHz, Integration Range:  
12kHz - 20MHz  
tjit(Ø)  
tjit(Ø)  
0.5  
0.9  
0.66  
1.3  
ps  
ps  
RMS Phase Jitter (Random);  
NOTE 2,3  
156.25MHz, Integration Range:  
1kHz - 40MHz  
500MHz ≤ fOUT ≤ 1300MHz  
100MHz ≤ fOUT ≤ 500MHz  
15MHz ≤ fOUT ≤ 100MHz  
0.44  
0.52  
0.74  
0.77  
0.90  
1.2  
ps  
ps  
ps  
RMS Phase Jitter (Random);  
NOTE 2,3,4  
fXTAL = 114.285mhz  
tjit(Ø)  
Single-side band phase noise,  
100Hz from Carrier  
ΦN(100)  
ΦN(1k)  
156.25MHz  
156.25MHz  
156.25MHz  
156.25MHz  
156.25MHz  
156.25MHz  
-69  
-98  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc  
Single-side band phase noise,  
1kHz from Carrier  
Single-side band phase noise,  
10kHz from Carrier  
ΦN(10k)  
ΦN(100k)  
ΦN(1M)  
ΦN(10M)  
PSNR  
-123  
-128  
-140  
-145  
-71.2  
Single-side band phase noise, 100kHz  
from Carrier  
Single-side band phase noise,  
1MHz from Carrier  
Single-side band phase noise,  
10MHz from Carrier  
50mV Sinusoidal Noise  
1kHz - 50MHz  
Power Supply Noise Rejection  
tR / tF  
odc  
Output Rise/Fall Time  
Output Duty Cycle  
20% to 80%  
80  
45  
500  
55  
ps  
%
tSTARTUP Device startup time after power up  
Notes continued on next page.  
10  
ms  
IDT8N3SV75CCD REVISION A APRIL 26, 2012  
6
©2012 Integrated Device Technology, Inc.  
IDT8N3SV75 Data Sheet  
LVPECL-FREQUENCY PROGRAMMABLE VCXO  
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is  
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium  
has been reached under these conditions.  
NOTE: XTAL parameters (initial accuracy, temperature stability, aging and total stability) are guaranteed by manufacturing.  
NOTE: Characterized with VC = VCC/2.  
NOTE 1: This parameter is defined in accordance with JEDEC standard 65.  
NOTE 2: Refer to the phase noise plot.  
NOTE 3: Please see the FemtoClock NG Ceramic 5x7 Modules Programming guide for more information on PLL feedback modes and the  
optimum configuration for phase noise.  
Table 5B. VCXO Control Voltage Input (V ) Characteristics, VCC = 3.3V 5% or 2.5V 5%, VEE = 0V, TA = -40°C to 85°C  
C
Symbol Parameter  
Test Conditions  
VCC = 3.3V  
Minimum  
Typical  
Maximum  
477.27  
630  
Units  
ppm/V  
ppm/V  
%
Oscillator Gain, NOTE 1, 2, 3  
7.57  
10  
KV  
Oscillator Gain, NOTE 1, 2, 3  
Control Voltage Linearity; NOTE 4  
Modulation Bandwidth  
VCC = 2.5V  
LVC  
BSL Variation  
-1  
0.1  
100  
+1  
BW  
kHz  
kΩ  
ZVC  
VC Input Impedance  
500  
VCNOM  
Nominal Control Voltage  
VCC/2  
V
Control Voltage Tuning Range;  
NOTE 4  
VC  
0
VCC  
V
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is  
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium  
has been reached under these conditions.  
NOTE 1: VC = 10% to 90% of VCC  
.
NOTE 2: Nominal oscillator gain: Pull range divided by the control voltage tuning range of 3.3V. E.g. for ADC_GAIN [6:0] = 000001 the pull  
range is 12.5ppm, resulting in an oscillator gain of 25ppm ÷ 3.3V = 7.57ppm/V.  
NOTE 3: For best phase noise performance, use the lowest KV that meets the requirements of the application.  
NOTE 4: BSL = Best Straight Line Fit: Variation of the output frequency vs. control voltage VC, in percent. VC ranges from 10% to 90% VCC  
.
IDT8N3SV75CCD REVISION A APRIL 26, 2012  
7
©2012 Integrated Device Technology, Inc.  
IDT8N3SV75 Data Sheet  
LVPECL-FREQUENCY PROGRAMMABLE VCXO  
Typical Phase Noise at 156.25MHz (12kHz - 20MHz)  
Offset Frequency (Hz)  
IDT8N3SV75CCD REVISION A APRIL 26, 2012  
8
©2012 Integrated Device Technology, Inc.  
IDT8N3SV75 Data Sheet  
LVPECL-FREQUENCY PROGRAMMABLE VCXO  
Parameter Measurement Information  
2V  
2V  
SCOPE  
SCOPE  
V
V
CC  
Qx  
Qx  
CC  
nQx  
nQx  
VEE  
VEE  
-1.3V 0.165V  
-0.5V 0.125V  
3.3V LVPECL Output Load AC Test Circuit  
2.5 LVPECL Output Load AC Test Circuit  
Phase Noise Plot  
nQ  
80%  
tF  
80%  
tR  
VSWING  
20%  
20%  
Q
Offset Frequency  
f1  
f2  
RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers  
Output Rise/Fall Time  
RMS Phase Jitter  
nQ  
nQ  
Q
Q
tPW  
➤
➤
tPERIOD  
tcycle n  
tcycle n+1  
➤
➤
tjit(cc) = tcycle n – tcycle n+1  
|
|
tPW  
1000 Cycles  
odc =  
x 100%  
tPERIOD  
Cycle -to-Cycle Jitter  
Output Duty Cycle /Pulse Width/Period  
IDT8N3SV75CCD REVISION A APRIL 26, 2012  
9
©2012 Integrated Device Technology, Inc.  
IDT8N3SV75 Data Sheet  
LVPECL-FREQUENCY PROGRAMMABLE VCXO  
Parameter Measurement Information, continued  
VOH  
VREF  
VOL  
1σ contains 68.26% of all measurements  
2σ contains 95.4% of all measurements  
3σ contains 99.73% of all measurements  
4σ contains 99.99366% of all measurements  
6σ contains (100-1.973x10-7)% of all measurements  
Histogram  
Reference Point  
(Trigger Edge)  
Mean Period  
(First edge after trigger)  
Period Jitter  
Applications Information  
Termination for 3.3V LVPECL Outputs  
The clock layout topology shown below is a typical termination for  
LVPECL outputs. The two different layouts mentioned are  
recommended only as guidelines.  
transmission lines. Matched impedance techniques should be used  
to maximize operating frequency and minimize signal distortion.  
Figures 1A and 1B show two different layouts which are  
recommended only as guidelines. Other suitable clock layouts may  
exist and it would be recommended that the board designers  
simulate to guarantee compatibility across all printed circuit and clock  
component process variations.  
The differential outputs are low impedance follower outputs that  
generate ECL/LVPECL compatible outputs. Therefore, terminating  
resistors (DC current path to ground) or current sources must be  
used for functionality. These outputs are designed to drive 50Ω  
3.3V  
R3  
125Ω  
R4  
125Ω  
3.3V  
3.3V  
3.3V  
Z
o = 50Ω  
3.3V  
+
_
Z
Z
o = 50Ω  
+
_
Input  
LVPECL  
Zo = 50Ω  
LVPECL  
Input  
o = 50Ω  
R1  
R2  
50Ω  
50Ω  
R1  
84Ω  
R2  
84Ω  
VCC - 2V  
1
RTT =  
* Zo  
RTT  
((VOH + VOL) / (VCC – 2)) – 2  
Figure 1A. 3.3V LVPECL Output Termination  
Figure 1B. 3.3V LVPECL Output Termination  
IDT8N3SV75CCD REVISION A APRIL 26, 2012  
10  
©2012 Integrated Device Technology, Inc.  
IDT8N3SV75 Data Sheet  
LVPECL-FREQUENCY PROGRAMMABLE VCXO  
Termination for 2.5V LVPECL Outputs  
Figure 2A and Figure 2B show examples of termination for 2.5V  
LVPECL driver. These terminations are equivalent to terminating 50Ω  
to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground  
level. The R3 in Figure 2B can be eliminated and the termination is  
shown in Figure 2C.  
2.5V  
VCC = 2.5V  
2.5V  
2.5V  
VCC = 2.5V  
50Ω  
R1  
R3  
250Ω  
250Ω  
+
50Ω  
50Ω  
+
–
50Ω  
–
2.5V LVPECL Driver  
R1  
R2  
50Ω  
50Ω  
2.5V LVPECL Driver  
R2  
R4  
62.5Ω  
62.5Ω  
R3  
18Ω  
Figure 2A. 2.5V LVPECL Driver Termination Example  
Figure 2B. 2.5V LVPECL Driver Termination Example  
2.5V  
VCC = 2.5V  
50Ω  
+
50Ω  
–
2.5V LVPECL Driver  
R1  
R2  
50Ω  
50Ω  
Figure 2C. 2.5V LVPECL Driver Termination Example  
IDT8N3SV75CCD REVISION A APRIL 26, 2012  
11  
©2012 Integrated Device Technology, Inc.  
IDT8N3SV75 Data Sheet  
LVPECL-FREQUENCY PROGRAMMABLE VCXO  
Schematic Layout  
Figure 3 shows an example of IDT8N3SV75 application schematic.  
In this example, the device is operated at VCC = 3.3V. As with any  
high speed analog circuitry, the power supply pins are vulnerable to  
random noise. To achieve optimum jitter performance, power supply  
isolation is required.  
the devices. The filter performance is designed for a wide range of  
noise frequencies. This low-pass filter starts to attenuate noise at  
approximately 10 kHz. If a specific frequency noise component is  
known, such as switching power supplies frequencies, it is  
recommended that component values be adjusted and if required,  
additional filtering be added. Additionally, good general design  
practices for power plane voltage stability suggests adding bulk  
capacitance in the local area of all devices.  
In order to achieve the best possible filtering, it is recommended that  
the placement of the filter components be on the device side of the  
PCB as close to the power pins as possible. If space is limited, the  
0.1µF capacitor in each power pin filter should be placed on the  
device side of the PCB and the other components can be placed on  
the opposite side. Power supply filter recommendations are a general  
guideline to be used for reducing external noise from coupling into  
The schematic example focuses on functional connections and is not  
configuration specific. Refer to the pin description and functional  
tables in the datasheet to ensure that the logic control inputs are  
properly set.  
3.3V  
FB  
VCC  
C 1  
1
2
m uRata, BLM18BB221SN1  
C2  
U 1  
C 3  
VCC  
0.1uF  
10uF  
0.1uF  
3.3 V  
R1  
J1  
SP  
1
VC  
1
2
3
6
5
4
R2  
133  
R3  
VC  
VC C  
nQ  
Q
OE  
133  
OE  
Zo = 50 Ohm  
Zo = 50 Ohm  
VEE  
Q
+
-
R4  
SP  
nQ  
R5  
82.5  
R 6  
82. 5  
VCC=3.3V  
Logic Cont rol Input Examples  
Zo = 50 Ohm  
Set Logic  
Input to  
'1'  
Set Logic  
Input to  
'0'  
+
VCC  
VCC  
Zo = 50 Ohm  
-
RU 1  
1K  
RU2  
Not Install  
R7  
50  
R 8  
50  
To Logic  
Input  
To Log i c  
Input  
pins  
pins  
RD 1  
RD2  
1K  
R 9  
50  
Optional  
Not Install  
Y-Termination  
Figure 3. IDT8N3SV75 Application Schematic  
IDT8N3SV75CCD REVISION A APRIL 26, 2012  
12  
©2012 Integrated Device Technology, Inc.  
IDT8N3SV75 Data Sheet  
LVPECL-FREQUENCY PROGRAMMABLE VCXO  
Power Considerations  
This section provides information on power dissipation and junction temperature for the IDT8N3SV75.  
Equations and example calculations are also provided.  
1. Power Dissipation.  
The total power dissipation for the IDT8N3SV75 is the sum of the core power plus the power dissipated in the load(s).  
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.  
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.  
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 160mA = 554.40mW  
Power (outputs)MAX = 30mW/Loaded Output pair  
Total Power_MAX (3.3V, with all outputs switching) = 554.40mW + 30mW = 584.40mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond  
wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = θJA * Pd_total + TA  
Tj = Junction Temperature  
θJA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and  
a multi-layer board, the appropriate value is 49.4°C/W per Table 6 below.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C + 0.584W * 49.4°C/W = 113.8°C. This is below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of  
board (multi-layer).  
Table 6. Thermal Resistance θJA for 6 Lead Ceramic VFQFN, Forced Convection  
θJA by Velocity  
Meters per Second  
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards  
49.4°C/W  
44.2°C/W  
42.1°C/W  
IDT8N3SV75CCD REVISION A APRIL 26, 2012  
13  
©2012 Integrated Device Technology, Inc.  
IDT8N3SV75 Data Sheet  
LVPECL-FREQUENCY PROGRAMMABLE VCXO  
3. Calculations and Equations.  
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.  
LVPECL output driver circuit and termination are shown in Figure 4.  
VCC  
Q1  
VOUT  
RL  
50Ω  
VCC - 2V  
Figure 4. LVPECL Driver Circuit and Termination  
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of  
VCC – 2V.  
•
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V  
(VCC_MAX – VOH_MAX) = 0.9V  
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V  
(VCC_MAX – VOL_MAX) = 1.7V  
Pd_H is power dissipation when the output drives high.  
Pd_L is the power dissipation when the output drives low.  
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =  
[(2V – 0.9V)/50Ω] * 0.9V = 19.8mW  
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =  
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW  
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW  
IDT8N3SV75CCD REVISION A APRIL 26, 2012  
14  
©2012 Integrated Device Technology, Inc.  
IDT8N3SV75 Data Sheet  
LVPECL-FREQUENCY PROGRAMMABLE VCXO  
Reliability Information  
Table 7. θ vs. Air Flow Table for a 6-lead Ceramic 5mm x 7mm Package  
JA  
θJA vs. Air Flow  
Meters per Second  
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards  
49.4°C/W  
44.2°C/W  
42.1°C/W  
Transistor Count  
The transistor count for IDT8N3SV75 is: 47,414  
IDT8N3SV75CCD REVISION A APRIL 26, 2012  
15  
©2012 Integrated Device Technology, Inc.  
IDT8N3SV75 Data Sheet  
LVPECL-FREQUENCY PROGRAMMABLE VCXO  
Package Outline and Package Dimensions  
D
2
B
C
D
1
F
N
N
(TYP.)  
A
E (TYP.)  
PIN 1  
INDEX  
H
(TYP.)  
O
1
1
6 Terminal  
Option Pkg.  
J (TYP.)  
G (TYP.)  
Metalized  
DIMENSION IN MM  
SYMBOL  
MIN.  
NOM.  
5.00  
7.00  
1.50  
MAX.  
A
B
C
4.85  
6.85  
1.35  
5.15  
7.15  
1.65  
D1  
2.41  
2.54  
2.67  
D2  
E
F
G
H
J
4.95  
2.47  
0.47  
1.27  
-
5.08  
2.6  
0.60  
5.21  
2.73  
0.73  
1.53  
-
1.40  
0.15 Ref.  
0.65 Ref.  
-
-
IDT8N3SV75CCD REVISION A APRIL 26, 2012  
16  
©2012 Integrated Device Technology, Inc.  
IDT8N3SV75 Data Sheet  
LVPECL-FREQUENCY PROGRAMMABLE VCXO  
Ordering Information for FemtoClockNG Ceramic-Package XO and VCXO Products  
The programmable VCXO and XO devices support a variety of  
devices options such as the output type, number of default  
frequencies, power supply voltage, ambient temperature range and  
the frequency accuracy. The device options, default frequencies and  
default VCXO pull range must be specified at the time of order and  
are programmed by IDT before the shipment. Table 8 specifies the  
available order codes, including the device options. Example part  
number: the order code 8N3SV75FC-0001CDI specifies a  
programmable VCXO with a voltage supply of 2.5V, a ±50 ppm  
crystal frequency accuracy, industrial temperature range, a lead-free  
(6/6 RoHS) 6-lead ceramic 5mm x 7mm x 1.55mm package and is  
factory-programmed to the default frequencies of 100 MHz and the  
VCXO pull range of min. ±100 ppm.  
Other default frequencies and order codes are available from IDT on  
request.  
Table 8. Order Codes  
Part/Order Number  
8N X X XXX X X - dddd XX X X  
Shipping Package  
8: Tape & Reel  
(no letter): Tray  
FemtoClock NG  
I/O Identifier  
Ambient Temperature Range  
“I”: Industrial: (TA = -40°C to 85°C)  
(no letter) : (TA = 0°C to 70°C)  
0: LVCMOS  
3: LVPECL  
4: LVDS  
Package Code  
CD: Lead-Free, 6/10-lead ceramic 5mm x 7mm x 1.55mm  
Number of Default Frequencies  
S: 1: Single  
D: 2: Dual  
Q: 4: Quad  
Default-Frequency and VCXO Pull Range  
See document FemtoClock NG Ceramic-Package XO and  
VCXO Ordering Product Information.  
dddd  
fXTAL (MHz) PLL feedback  
Use for  
VCXO, XO  
XO  
Part Number  
0000 to 0999  
1000 to 1999  
2000 to 2999  
114.285  
Fractional  
Integer  
OE fct. at  
Function #pins  
pin  
100.000  
Fractional  
XO  
001  
003  
V01  
V03  
V75  
V76  
V85  
085  
270  
271  
272  
273  
XO  
XO  
10  
10  
10  
10  
6
OE@2  
OE@1  
OE@2  
OE@1  
OE@2  
nOE@2  
—
Last digit = L: configuration pre-programmed and not  
changeable  
VCXO  
VCXO  
VCXO  
VCXO  
VCXO  
XO  
Die Revision  
C
6
6
Option Code (Supply Voltage and Frequency-Stability)  
6
OE@1  
OE@1  
OE@2  
nOE@2  
nOE@1  
A: VCC = 3.3V 5%, 100ppm  
B: VCC = 2.5V 5%, 100ppm  
XO  
6
E: VCC = 3.3V 5%,  
F: VCC = 2.5V 5%,  
K: VCC = 3.3V 5%,  
L: VCC = 2.5V 5%,  
50ppm  
50ppm  
20ppm  
20ppm  
XO  
6
XO  
6
XO  
6
NOTE: For order information, see the FemtoClock NG Ceramic-Package XO and VCXO Ordering Product Information document.  
IDT8N3SV75CCD REVISION A APRIL 26, 2012  
17  
©2012 Integrated Device Technology, Inc.  
IDT8N3SV75 Data Sheet  
LVPECL-FREQUENCY PROGRAMMABLE VCXO  
Table 9. Device Marking  
Industrial Temperature Range (TA = -40°C to 85°C)  
Commercial Temperature Range (TA = 0°C to 70°C)  
IDT8N3SV75yC-  
ddddCDI  
IDT8N3SV75yC-  
ddddCD  
Marking  
y = Option Code, dddd=Default-Frequency and VCXO Pull Range  
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the  
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal  
commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without  
additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support  
devices or critical medical instruments.  
IDT8N3SV75CCD REVISION A APRIL 26, 2012  
18  
©2012 Integrated Device Technology, Inc.  
IDT8N3SV75 Data Sheet  
LVPECL-FREQUENCY PROGRAMMABLE VCXO  
We’ve Got Your Timing Solution  
6024 Silver Creek Valley Road Sales  
Technical Support  
800-345-7015 (inside USA)  
netcom@idt.com  
San Jose, California 95138  
+408-284-8200 (outside USA) +480-763-2056  
Fax: 408-284-2775  
www.IDT.com/go/contactIDT  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,  
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not  
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the  
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any  
license under intellectual property rights of IDT or any third parties.  
IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT  
product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third  
party owners.  
Copyright 2012. All rights reserved.  
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