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CYK128K16MCCBU-70BVIT

型号：

CYK128K16MCCBU-70BVIT

品牌：

CYPRESS[ CYPRESS ]

页数：

9 页

PDF大小：

179 K

下载PDF手册
CYK128K16MCCB  
2-Mbit (128K x 16) Pseudo Static RAM  
can be put into standby mode when deselected (CE HIGH or  
both BHE and BLE are HIGH). The input/output pins (I/O0  
through I/O15) are placed in a high-impedance state when the  
chip is deselected (CE HIGH), or when the outputs are  
disabled (OE HIGH), or when both Byte High Enable and Byte  
Low Enable are disabled (BHE, BLE HIGH), or during a write  
operation (CE LOW and WE LOW).  
Features  
• Wide voltage range: 2.70V–3.30V  
• Access Time: 55 ns, 70 ns  
• Ultra-low active power  
— Typical active current: 1mA @ f = 1 MHz  
— Typical active current: 14 mA @ f = fmax (For 55-ns)  
— Typical active current: 8 mA @ f = fmax (For 70-ns)  
• Ultra low standby power  
Writing to the device is accomplished by asserting Chip  
Enable (CE LOW) and Write Enable (WE) input LOW. If Byte  
Low Enable (BLE) is LOW, then data from I/O pins (I/O0  
through I/O7), is written into the location specified on the  
address pins (A0 through A17). If Byte High Enable (BHE) is  
LOW, then data from I/O pins (I/O8 through I/O15) is written  
into the location specified on the address pins (A0 through  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Offered in a 48-ball BGA Package  
A16).  
Reading from the device is accomplished by asserting Chip  
Enable (CE LOW) and Output Enable (OE) LOW while forcing  
the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is  
LOW, then data from the memory location specified by the  
address pins will appear on I/O0 to I/O7. If Byte High Enable  
(BHE) is LOW, then data from memory will appear on I/O8 to  
I/O15. Refer to the truth table for a complete description of read  
and write modes.  
Functional Description[1]  
The CYK128K16MCCB is a high-performance CMOS Pseudo  
Static RAM organized as 128K words by 16 bits that supports  
an asynchronous memory interface. This device features  
advanced circuit design to provide ultra-low active current.  
This is ideal for providing More Battery Life™ (MoBL®) in  
portable applications such as cellular telephones. The device  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A 9  
A 8  
A 7  
A 6  
A 5  
A 4  
A 3  
128K × 16  
RAM Array  
I/O0 – I/O7  
I/O8 – I/O15  
A 2  
A 1  
A 0  
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
Power-Down  
Circuit  
BHE  
CE  
BLE  
Note:  
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05584 Rev. *C  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised January 27, 2005  
CYK128K16MCCB  
Pin Configuration[2, 3, 4]  
48-ball VFBGA  
Top View  
1
4
2
5
3
6
A
A
A
2
NC  
I/O  
OE  
BLE  
0
1
A
B
I/O BHE  
A
CE  
I/O  
A
0
8
3
4
I/O  
A
A
6
I/O  
I/O  
2
C
D
E
F
5
10  
9
1
A
V
SS  
Vcc  
Vss  
I/O  
I/O  
3
NC  
7
11  
A
V
CC  
I/O  
DNU  
I/O  
16  
12  
4
A
A
15  
I/O  
I/O  
I/O  
I/O  
14  
13  
5
14  
6
A
A
G
NC  
I/O  
I/O  
13  
12  
WE  
15  
7
A
A
A
11  
H
A
NC  
10  
9
8
NC  
Product Portfolio  
Power Dissipation  
Operating ICC (mA)  
f = 1MHz f = fmax Standby ISB2(µA)  
V
CC Range (V)  
Speed  
(ns)  
Product  
Min.  
2.70  
Typ.[5]  
Max.  
3.30  
Typ.[5]  
Max.  
Typ.[5]  
Max.  
22  
Typ.[5]  
Max.  
CYK128K16MCCB  
3.0  
55  
70  
1
5
14  
8
9
40  
15  
Notes:  
2. Ball D3, H1, G2 and ball H6 for the FBGA package can be used to upgrade to a 4-Mbit, 8-Mbit, 16-Mbit and a 32-Mbit density, respectively.  
3. NC “no connect”—not connected internally to the die.  
4. DNU (Do Not Use) pins have to be left floating or tied to Vss to ensure proper application.  
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V  
, T = 25°C.  
A
CC  
CC(typ.)  
Document #: 38-05584 Rev. *C  
Page 2 of 9  
CYK128K16MCCB  
Output Current into Outputs (LOW)............................. 20 mA  
Maximum Ratings  
Static Discharge Voltage.......................................... > 2001V  
(per MIL-STD-883, Method 3015)  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Latch-up Current.....................................................> 200 mA  
Storage Temperature ................................–65°C to + 150°C  
Operating Range  
Ambient Temperature with  
Power Applied............................................–55°C to + 125°C  
Ambient  
Temperature  
Supply Voltage to Ground Potential................. –0.4V to 4.6V  
Device  
Range  
VCC  
DC Voltage Applied to Outputs  
CYK128K16MCCB Industrial –25°C to +85°C 2.70V to  
3.30V  
in High-Z State[6, 7, 8]........................................ –0.4V to 3.7V  
DC Input Voltage[6, 7, 8] .................................... –0.4V to 3.7V  
Electrical Characteristics (Over the Operating Range)  
CYK128K16MCCB-55 CYK128K16MCCB-70  
Min. Typ.[5] Max. Min. Typ.[5] Max. Unit  
Parameter  
VCC  
Description  
Test Conditions  
Supply Voltage  
2.7  
3.0  
3.3  
2.7  
3.0  
3.3  
V
V
VOH  
Output HIGH Voltage IOH = –0.1 mA  
VCC = 2.70V VCC  
0.4  
–
VCC  
0.4  
–
VOL  
VIH  
Output LOW Voltage IOL = 0.1 mA  
VCC = 2.70V  
0.4  
0.4  
V
V
Input HIGH Voltage  
Input LOW Voltage  
VCC= 2.7V to 3.3V  
0.8 *  
VCC  
VCC 0.8 *  
+ 0.4V VCC  
VCC  
+ 0.4V  
VIL  
IIX  
–0.4  
–1  
0.4  
+1  
+1  
–0.4  
–1  
0.4  
+1  
+1  
V
Input Leakage Current GND < VIN < VCC  
µA  
µA  
IOZ  
Output Leakage  
Current  
GND < VOUT < VCC, Output Disabled  
–1  
–1  
ICC  
VCC Operating Supply f = fMAX = 1/tRC  
VCC = VCCmax  
IOUT = 0 mA  
CMOS levels  
14  
1
22  
5
8
1
15  
5
mA  
mA  
Current  
f = 1 MHz  
ISB1  
Automatic CE  
Power-Down Current VIN > VCC – 0.2V, VIN  
—CMOS Inputs  
CE > VCC − 0.2V  
0.2V) f = fMAX (Address  
and Data Only), f = 0  
(OE, WE, BHEandBLE),  
VCC = 3.3V  
40  
250  
40  
40  
250  
40  
µA  
µA  
<
VCC = 3.30V  
ISB2  
Automatic CE  
Power-Down Current VIN > VCC – 0.2V or VIN  
CE > VCC – 0.2V  
VCC = 3.3V  
9
9
<
—CMOS Inputs 0.2V, f = 0, VCC = 3.30V  
Capacitance[9]  
Parameter  
Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
Max.  
Unit  
pF  
CIN  
TA = 25°C, f = 1 MHz,  
VCC = VCC(typ)  
8
8
COUT  
pF  
Thermal Resistance[9]  
Parameter  
Description  
Test Conditions  
BGA  
Unit  
ΘJA  
Thermal Resistance  
(Junction to Ambient)  
Test conditions follow standard test methods and  
procedures for measuring thermal impedance, per EIA  
/ JESD51.  
55  
°C/W  
ΘJC  
Thermal Resistance  
(Junction to Case)  
17  
°C/W  
Notes:  
6. V  
7. V  
= –0.5V for pulse durations less than 20 ns.  
IL(MIN)  
= V + 0.5V for pulse durations less than 20 ns.  
IH(Max)  
CC  
8. Overshoot and undershoot specifications are characterized and are not 100% tested.  
9. Tested initially and after any design or process changes that may affect these parameters.  
Document #: 38-05584 Rev. *C  
Page 3 of 9  
CYK128K16MCCB  
AC Test Loads and Waveforms  
R1  
ALL INPUT PULSES  
90%  
10%  
VCC  
OUTPUT  
VCC  
GND  
90%  
10%  
Fall Time = 1 V/ns  
R2  
30 pF  
Rise Time = 1 V/ns  
Equivalent to:  
INCLUDING  
JIG AND  
SCOPE  
THÉVENINEQUIVALENT  
RTH  
OUTPUT  
VTH  
Parameters  
3.0V VCC  
22000  
22000  
11000  
1.50  
Unit  
Ω
R1  
R2  
Ω
RTH  
VTH  
Ω
V
Switching Characteristics Over the Operating Range [10]  
55 ns[14]  
Max.  
70 ns  
Parameter  
Read Cycle  
Description  
Min.  
55[14]  
5
Min.  
70  
Max.  
Unit  
tRC  
Read Cycle Time  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
Address to Data Valid  
55  
70  
tOHA  
tACE  
tDOE  
tLZOE  
tHZOE  
tLZCE  
tHZCE  
tDBE  
tLZBE  
tHZBE  
Data Hold from Address Change  
CE LOW to Data Valid  
10  
55  
25  
70  
35  
OE LOW to Data Valid  
OE LOW to LOW Z[11, 13]  
OE HIGH to High Z[11, 13]  
CE LOW to Low Z[11, 13]  
CE HIGH to High Z[11, 13]  
BLE/BHE LOW to Data Valid  
BLE/BHE LOW to Low Z[11, 13]  
BLE/BHE HIGH to HIGH Z[11, 13]  
Address Skew  
5
2
5
5
25  
25  
25  
55  
25  
70  
5
5
10  
0
25  
10  
[14]  
tSK  
Write Cycle[12]  
tWC  
tSCE  
tAW  
tHA  
Write Cycle Time  
55  
45  
45  
0
70  
60  
60  
0
ns  
ns  
ns  
ns  
ns  
ns  
CE LOW to Write End  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
tSA  
0
0
tPWE  
40  
45  
Notes:  
10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of V  
/2, input pulse levels  
CC(typ)  
of 0V to V  
, and output loading of the specified I /I as shown in the “AC Test Loads and Waveforms” section.  
CC(typ.)  
OL OH  
11. t  
, t  
, t  
, and t  
transitions are measured when the outputs enter a high impedance state.  
HZOE HZCE HZBE  
HZWE  
12. The internal Write time of the memory is defined by the overlap of WE, CE = V , BHE and/or BLE = V . All signals must be ACTIVE to initiate a write and any  
IL  
IL  
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates  
the write  
13. High-Z and Low-Z parameters are characterized and are not 100% tested.  
14. To achieve 55-ns performance, the read access should be CE controlled. In this case t  
is the critical parameter and t is satisfied when the addresses are  
SK  
ACE  
stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle.  
Document #: 38-05584 Rev. *C  
Page 4 of 9  
CYK128K16MCCB  
Switching Characteristics Over the Operating Range (continued)[10]  
55 ns[14]  
70 ns  
Parameter  
Description  
BLE/BHE LOW to Write End  
Data Set-Up to Write End  
Data Hold from Write End  
WE LOW to High-Z[11, 13]  
WE HIGH to Low-Z[11, 13]  
Min.  
50  
25  
0
Max.  
Min.  
60  
45  
0
Max.  
Unit  
ns  
tBW  
tSD  
tHD  
ns  
ns  
tHZWE  
tLZWE  
25  
25  
ns  
5
5
ns  
Switching Waveforms  
Read Cycle 1 (Address Transition Controlled)[15, 16, 17]  
tRC  
ADDRESS  
tAA  
tSK  
tOHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
Read Cycle 2 (OE Controlled)[16, 17]  
ADDRESS  
tRC  
t
SK  
CE  
tHZCE  
tACE  
BHE/BLE  
tDBE  
tHZBE  
tLZBE  
OE  
tHZOE  
tDOE  
tLZOE  
HIGH IMPEDANCE  
HIGH  
IMPEDANCE  
DATA OUT  
DATA VALID  
tLZCE  
ICC  
ISB  
V
CC  
50%  
50%  
SUPPLY  
CURRENT  
Notes:  
15. Device is continuously selected. OE, CE = V .  
IL  
16. WE is HIGH for Read Cycle.  
17. For the 55-ns Cycle, the addresses must not toggle once the read is started on the device. For the 70-ns Cycle, the addresses must be stable within 10 ns after  
the start of the read cycle.  
Document #: 38-05584 Rev. *C  
Page 5 of 9  
CYK128K16MCCB  
Switching Waveforms (continued)  
Write Cycle 1 (WE Controlled)[12, 13, 18, 19, 20]  
tWC  
ADDRESS  
CE  
tSCE  
tAW  
tHA  
tSA  
tPWE  
WE  
tBW  
BHE/BLE  
OE  
tSD  
tHD  
VALID DATA  
DATA I/O  
DON’T CARE  
tHZOE  
Write Cycle 2 (CE Controlled)[12, 13, 18, 19, 20]  
t WC  
ADDRESS  
CE  
tSCE  
t
SA  
tHA  
tAW  
tPWE  
WE  
tBW  
BHE/BLE  
OE  
tSD  
tHZOE  
tHD  
VALID DATA  
DATA I/O  
DON’T CARE  
Notes:  
18. Data I/O is high impedance if OE > V  
.
IH  
19. If Chip Enable goes INACTIVE with WE = V , the output remains in a high-impedance state.  
IH  
20. During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.  
Document #: 38-05584 Rev. *C  
Page 6 of 9  
CYK128K16MCCB  
Switching Waveforms (continued)  
Write Cycle 3 (WE Controlled, OE LOW)[19, 20]  
tWC  
ADDRESS  
CE  
tSCE  
tBW  
BHE/BLE  
tAW  
tHA  
tSA  
tPWE  
WE  
tSD  
tHD  
DON’T CARE  
DATAI/O  
VALID DATA  
tLZWE  
tHZWE  
Write Cycle 4 (BHE/BLE Controlled, OE LOW)[19, 20]  
tWC  
ADDRESS  
CE  
tSCE  
tAW  
tHA  
tBW  
BHE/BLE  
WE  
tSA  
tPWE  
tSD  
tHD  
DON’T CARE  
VALID DATA  
DATA I/O  
Truth Table [21]  
CE  
H
X
WE  
X
OE  
X
BHE  
X
BLE  
Inputs/Outputs  
Mode  
Power  
X
H
L
High Z  
High Z  
Deselect/Power-Down Standby (ISB  
)
X
X
H
Deselect/Power-Down Standby (ISB)  
L
H
L
L
Data Out (I/O0–I/O15  
Data Out (I/O0–I/O7);  
High Z (I/O8–I/O15  
)
Read  
Read  
Active (ICC  
)
L
H
L
H
L
Active (ICC)  
)
Note:  
21. H = Logic HIGH, L = Logic LOW, X = Don’t Care.  
Document #: 38-05584 Rev. *C  
Page 7 of 9  
CYK128K16MCCB  
Truth Table (continued)[21]  
CE  
WE  
OE  
BHE  
BLE  
Inputs/Outputs  
High Z (I/O0–I/O7);  
Mode  
Power  
Active (ICC)  
L
H
L
L
H
Read  
Data Out (I/O8–I/O15  
)
L
L
L
L
L
L
H
H
H
L
H
H
H
X
X
X
L
H
L
H
L
L
L
L
H
High Z  
Output Disabled  
Output Disabled  
Output Disabled  
Write  
Active (ICC  
Active (ICC  
Active (ICC  
Active (ICC  
Active (ICC  
)
High Z  
)
High Z  
)
L
Data In (I/O0–I/O15  
)
)
L
H
L
Data In (I/O0–I/O7); High Z (I/O8–I/O15  
High Z (I/O0–I/O7); Data In (I/O8–I/O15  
)
)
Write  
)
L
Write  
Active (ICC)  
Ordering Information  
Speed  
Package  
Operating  
Range  
(ns)  
Ordering Code  
Name  
BV48A  
BV48A  
Package Type  
55  
CYK128K16MCCBU-55BVI  
CYK128K16MCCBU-70BVI  
CYK128K16MCBU-55BVXI  
CYK128K16MCBU-70BVXI  
48-ball Very Fine Pitch BGA (6 mm × 8mm × 1.0 mm)  
48-ball Very Fine Pitch BGA (6 mm × 8mm × 1.0 mm)  
Industrial  
Industrial  
70  
55  
BV48A 48-ball Very Fine Pitch BGA (6 mm × 8mm × 1.0 mm) (Pb-Free) Industrial  
BV48A 48-ball Very Fine Pitch BGA (6 mm × 8mm × 1.0 mm) (Pb-Free) Industrial  
70  
Package Diagram  
48-Lead VFBGA (6 x 8 x 1 mm) BV48A  
51-85150-*B  
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor Corporation. All product and  
company names mentioned in this document may be the trademarks of their respective holders.  
Document #: 38-05584 Rev. *C  
Page 8 of 9  
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
CYK128K16MCCB  
Document History Page  
Document Title: CYK128K16MCCB 2-Mbit (128K x 16) Pseudo Static RAM  
Document Number: 38-05584  
Orig. of  
REV.  
**  
ECN NO. Issue Date Change  
Description of Change  
229571  
224474  
263150  
314013  
See ECN  
See ECN  
See ECN  
See ECN  
REF  
SYT  
PCI  
New data sheet  
*A  
Changed ball E3 on the package pinout from NC to DNU  
Changed from preliminary to final  
*B  
*C  
RKF  
Added Pb-Free parts to the Ordering information  
Document #: 38-05584 Rev. *C  
Page 9 of 9  
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