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S1R72C05***

Data Sheet

Rev.1.0

NOTICE

No part of this material may be reproduced or duplicated in any form or by any means without the written

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license from the Ministry of Economy, Trade and Industry or other approval from another government agency.

All other product names mentioned herein are trademarks and/or registered trademarks of their respective

companies.

Scope

This document applies to the “S1R72C05” USB 2.0 Device Host Controller LSI.

Table of Contents

1. OVERVIEW .....................................................................................................................1

2. FEATURES......................................................................................................................2

3. BLOCK DIAGRAM..........................................................................................................3

4. FUNCTIONS....................................................................................................................4

4.1 Power Supply................................................................................................................................4

4.2 Boundary Scan..............................................................................................................................4

4.2.1 Instructions Supported..............................................................................................................4

4.2.2 DEVICE_CODE........................................................................................................................5

4.2.3 Terminals Excluded from Boundary Scan.................................................................................5

4.3 Reset..............................................................................................................................................5

4.3.1 Hard Reset ...............................................................................................................................5

4.3.2 Soft Reset.................................................................................................................................5

4.4 Clock..............................................................................................................................................5

4.5 Power Management ......................................................................................................................6

4.6 CPU-I/F...........................................................................................................................................7

4.7 IDE-I/F ............................................................................................................................................7

4.8 USB Device I/F ..............................................................................................................................7

4.8.1 Speed Mode and Transfer Type................................................................................................7

4.8.2 Resources ................................................................................................................................7

4.8.2.1 Endpoint...................................................................................................................................................... 7

4.8.2.2 FIFO............................................................................................................................................................ 7

4.8.3 Data Flow .................................................................................................................................7

4.8.4 USB Device Port External Circuits............................................................................................9

4.9 USB Host I/F..................................................................................................................................9

4.9.1 Speed Mode and Transfer Type................................................................................................9

4.9.2 Resources ................................................................................................................................9

4.9.2.1 Channel....................................................................................................................................................... 9

4.9.2.2 FIFO............................................................................................................................................................ 9

4.9.3 Data Flow .................................................................................................................................9

4.9.4 USB Host Port External Circuits .............................................................................................11

4.10 FIFO............................................................................................................................................11

4.10.1 USB FIFO.............................................................................................................................11

4.10.2 Media FIFO...........................................................................................................................11

5. TERMINAL LAYOUT DIAGRAMS ................................................................................12

6. TERMINAL FUNCTIONS ..............................................................................................14

7. ELECTRICAL CHARACTERISTICS.............................................................................17

7.1 Absolute Maximum Ratings.......................................................................................................17

7.2 Recommended Operating Conditions.......................................................................................17

7.3 DC Characteristics......................................................................................................................18

7.3.1 Current Consumption .............................................................................................................18

7.3.2 Input Characteristics...............................................................................................................20

7.3.3 Output Characteristics............................................................................................................21

7.3.4 Terminal Capacitance .............................................................................................................22

7.4 AC Characteristics......................................................................................................................22

7.4.1 Reset Timing...........................................................................................................................22

S1R72C05*** Data Sheet (Rev.1.00)

EPSON

i

7.4.2 Clock Timing...........................................................................................................................22

7.4.3 CPU/DMA I/F Access Timing..................................................................................................23

7.4.3.1 Specifications for CVDD = 1.65 V to 3.6 V................................................................................................ 23

7.4.3.2 Specifications When Limited to CVDD = 3.0 V to 3.6 V ............................................................................ 24

7.4.4 IDE I/F Timing.........................................................................................................................25

7.4.4.1 PIO Read Timing....................................................................................................................................... 25

7.4.4.2 PIO Write Timing....................................................................................................................................... 26

7.4.4.3 DMA Read Timing..................................................................................................................................... 27

7.4.4.4 DMA Write Timing ..................................................................................................................................... 28

7.4.4.5 Ultra DMA Read Timing............................................................................................................................. 29

7.4.4.6 Ultra DMA Write Timing............................................................................................................................. 31

7.4.5 USB I/F Timing .......................................................................................................................32

8. CONNECTION EXAMPLES..........................................................................................33

8.1 CPU I/F Connection Example.....................................................................................................33

8.2 USB I/F Connection Example.....................................................................................................34

8.2.1 For QFP15-128 (Device Periphery)........................................................................................34

8.2.2 For QFP15-128 (Host Periphery)............................................................................................35

8.2.3 For PFBGA8UX121/PFBGA10UX121 (Device Periphery) .....................................................36

8.2.4 For PFBGA8UX121/PFBGA10UX121 (Host Periphery).........................................................37

9. PRODUCT CODES .......................................................................................................38

10. EXTERNAL DIMENSION DIAGRAMS........................................................................39

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EPSON

S1R72C05*** Data Sheet (Rev.1.00)

1. OVERVIEW

The S1R72C05** is a USB host and device controller LSI that supports USB 2.0 high-speed mode. Separate

host and device ports are provided to allow use as a USB host or USB device, depending on how control is

switched.

An IDE I/F is also provided, making it ideal for mobile or car-mounted electronic devices with built-in

HDDs.

S1R72C05*** Data Sheet (Rev.1.00)

EPSON

1

2. FEATURES

<<USB 2.0 device functions>>

•

HS (480 Mbps) and FS (12 Mbps) transfer support

Built-in FS/HS termination (no external circuits required)

VBUS 5V I/F (requires external protection circuit)

Support for control, bulk, interrupt, and isochronous transfers

Support for bulk, interrupt, isochronous transfer endpoints x5 and endpoint 0

<<USB 2.0 host functions>>

•

Support for HS (480 Mbps), FS (12 Mbps), and LS (1.5 Mbps) transfers

Built-in pull-down resistor for downstream port (no external circuit required)

Built-in HS termination (no external circuit required)

Support for control, bulk, interrupt, and isochronous transfers

Channel architecture

Dedicated control transfer channel x1

Dedicated bulk transfer channel x1

Bulk, interrupt, and isochronous transfer channels x4

USB power switch interface

•

<<Media data transfer functions>>

•

Media FIFO independent of USB allows data transfer between IDE and CPU.

<<CPU I/F>>

•

Supports 16-bit width standard CPU I/F

Includes DMA 2ch. (Multi-word procedure)

Big Endian (Includes bus swapping function to support Little Endian CPUs)

I/F variable voltage (3.3 V to 1.8 V)

<<IDE I/F>>

•

Supports ATA/ATAPI6

PIO mode 0 to 4, Multi-word DMA, UDMA mode 0 to 5

<<Miscellaneous>>

•

Clock input: Supports 12 MHz or 24 MHz quartz oscillator. (Built-in oscillator circuit and 1

MΩ feedback resistor)

•

Power supply voltage: 3-voltage system, featuring 3.3 V, 1.8 V, and CPU I/F power supply (3.3

V to 1.8 V)

•

Supports Boundary-Scan

Package type: QFP15-128, PFBGA8UX121, PFBGA10UX121

Guaranteed operating temperature range: -40°C to 85°C

2

EPSON

S1R72C05*** Data Sheet (Rev.1.00)

3. BLOCK DIAGRAM

CPU I/F Controller

DMA Controller

VBUSEN_A

VBUSFLG_A

HDD[15:0]

HDMARQ

XHDMACK

XHIOR

DP_A

DM_A

Host

HTM

SIE

XHIOW

R1_A

IDE

XHCS[1:0]

HDA[2:0]

HIORDY

HINTRQ

XHRESET

XHDASP

XHPDIAG

Master

Controller

DP_B

DM_B

VBUS_B

Device

SIE

DTM

R1_B

OSC

&

XI

XO

60MHz

PLL60

Media

Channel/Endpoint

USB FIFO

Media FIFO

Test

Mux

Fig.3.1 Overall block diagram

S1R72C05*** Data Sheet (Rev.1.00)

EPSON

3

4. FUNCTIONS

4.1 Power Supply

This LSI has three power supply circuits and a common ground. The power supply circuits consist of HVDD

(3.3 V) for USB I/O, IDE I/O, and TEST I/O; CVDD (3.3 V to 1.8 V) for CPU I/F I/O; and LVDD (1.8 V) for

internal circuits. (See Fig.4.1)

LVDD

1.8V

HVDD

3.3V

H_SIE

D_SIE

HTM

DTM

CPU

USB

I

O

CPU

-I/F

FIFO

IDE

-I/F

IO

TEST

IO

CVDD

1.8V to 3.3V

IDE

Fig.4.1 S1R72C05 power supplies

Given below are the sequences for turning the power supplies on and off.

This LSI will not operate with only some of the power supplies turned on or off. The following restrictions

apply to the sequence for turning the CVDD/HVDD I/O power supplies and LVDD internal power supply on or

off. There are no restrictions on the sequence for turning the CVDD and HVDD power supplies on or off.

•

The LVDD must be turned on before turning on the CVDD and HVDD power supplies.

The CVDD and HVDD power supplies must be turned off before turning off the LVDD.

If adherence to this sequence is not possible for reasons related to power supply circuit characteristics or load,

the CVDD or HVDD must be on for no longer than 1 second while the LVDD is off.

4.2 Boundary Scan

Boundary scanning (JTAG) may be used when the TEST terminal is set to “Low” (default). Boundary

scanning consists of a BSR (Boundary Scan Register) conforming to the JTAG (IEEE 1149.1) specifications, a

connecting scan path, and a TAP controller. Boundary scan connection information may be provided in BSDL

format.

4.2.1 Instructions Supported

This LSI has a JTAG instruction bit width of 4 bits and supports the following JTAG instructions.

4

EPSON

S1R72C05*** Data Sheet (Rev.1.00)

4. FUNCTIONS

Table 4.1 JTAG instruction codes

Instruction

Description

Code

SAMPLE/PRELOAD Loads LSI internal status to BSR and sets data.

0010

1111

0000

0011

BYPASS

EXTEST

CLAMP

Bypasses the scan path using BSR.

Physical device connection check.

Bypasses the scan path while maintaining output

values.

HIGHZ

IDCODE

Sets all outputs to Hi-Z.

Outputs the specified DEVICE_CODE.

0100

0001

4.2.2 DEVICE_CODE

The DEVICE_CODE corresponding to an IDCODE instruction is composed of the following elements.

Table 4.2 DEVICE_CODE

Version

Part Number

1

0x0015

Manufacturer

0x0BE

The DEVICE_CODE response for an IDCODE instruction will therefore be 0001_0000000000010101_

00010111110_1.

4.2.3 Terminals Excluded from Boundary Scan

The following terminals do not include boundary scan cells and are therefore excluded from boundary

scanning in this LSI: DP_A, DM_A, DP_B, DM_B, R1_A, R1_B, XI, XO, VBUS_B, and TEST.

4.3 Reset

This LSI includes a hard reset function via the external XRESET terminal and soft reset function via register

settings.

4.3.1 Hard Reset

Start from reset status when power is turned on, then cancel the reset after confirming power on.

4.3.2 Soft Reset

All LSI circuits can be reset via software, or internal USB analog macros can be reset individually. The

ChipReset.AllReset bit is used to reset all circuits in this LSI, or the D_Reset.ResetDTM or H_Reset.ResetHTM

bits are used to reset the respective device analog macro or host analog macro. However, note that the analog

macro should be reset only in the SLEEP state.

4.4 Clock

This LSI contains an internal oscillator and feedback resistor (1 MΩ) and supports clock generation using an

external resonator. The oscillator frequency can be set to 12 MHz or 24 MHz via the register settings.

Fig.4.2 shows a typical connection arrangement for an oscillator circuit. Cd, Cg, and Rd in the oscillator

circuit must be matched based on the resonator. Contact the resonator manufacturer to obtain circuit constants.

S1R72C05*** Data Sheet (Rev.1.00)

EPSON

5

4. FUNCTIONS

Cd

Cg

Rd

XO

XI

Fig.4.2 Clock generation via the internal oscillator and external resonator

4.5 Power Management

This LSI includes a power management function that features six power management states: SLEEP,

SNOOZE, ACTIVE60, ACT_DEVICE, ACT_HOST, and ACT_ALL. (See Fig.4.3)

All function blocks are active in the ACT_ALL state (although the USB host function and USB device

function cannot be used simultaneously). In the SLEEP state, however, only the circuits necessary for restarting

from standby mode are active. Intermediate power management states exist between ACT_ALL and SLEEP,

depending on the required activation status.

H_SIE

D_SIE

HTM

DTM

CPU

-I/F

OSC

FIFO

PLL

ACT _ ALL

ACT _ HOST

ACT _ DEVICE

ACTIVE 60

SNOOZE

IDE-I/F

H_SIE

D_SIE

HTM

DTM

CPU

-I/F

OSC

FIFO

PLL

IDE-I/F

H_SIE

D_SIE

HTM

DTM

CPU

-I/F

OSC

FIFO

PLL

IDE-I/F

H_SIE

D_SIE

HTM

DTM

CPU

-I/F

OSC

FIFO

PLL

IDE-I/F

H_SIE

D_SIE

HTM

DTM

CPU

-I/F*

OSC

FIFO

PLL

IDE-I/F

H_SIE

D_SIE

HTM

DTM

CPU

FIFO

PLL

-I/F*

SLEEP

OSC

IDE-I/F

Active

Inactive

*The CPU-I/ F is only partially active in the SLEEP and SNOOZE

states, allowing access to the asynchronous access register.

Fig.4.3 Power management states

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EPSON

S1R72C05*** Data Sheet (Rev.1.00)

4. FUNCTIONS

4.6 CPU-I/F

This LSI is connected to the CPU via a 16-bit interface. Endian settings can be set as Big Endian or Little

Endian in 16-bit steps. For Big Endian, registers with even addresses can be accessed above the bus (CD[15:8]),

while registers with odd addresses can be accessed below the bus (CD[7:0]). For Little Endian, registers with

even addresses can be accessed below the bus (CD[7:0]), while registers with odd addresses can be accessed

above the bus (CD[15:8]).

The bus mode can be set to either Strobe mode for accessing using high/low strobe (XWRH/XWRL) or Byte

Enable mode for accessing using high/low byte enable (XBEH/XBEL) for writing in 8-bit. Endian and bus

mode are set by the CPUIF_MODE register immediately after resetting.

The CPU-I/F on this LSI includes 2-ch DMA (slave).

The registers that are accessible will depend on the power management state. For detailed information, refer

to the LSI Technical Manual.

4.7 IDE-I/F

This LSI includes an IDE host function supporting ATA/ATAPI6, which supports PIO modes 0 to 4, Multi

Word DMA, and UDMA modes 0 to 5 transfer modes.

4.8 USB Device I/F

This LSI supports high-speed specification USB device functions that comply with USB 2.0 (Universal Serial

Bus Specification Revision 2.0) standards.

4.8.1 Speed Mode and Transfer Type

This LSI supports HS (480 Mbps) and FS (12 Mbps) speed modes when operating USB devices. The speed

mode is automatically set by the speed negotiations performed when the bus is reset. For example, HS transfer

mode will be selected automatically by speed negotiations if connected to a USB host that supports HS speed

mode. (Note that FS speed mode can be set deliberately via register settings.)

All transfer types stipulated in the USB 2.0 standard are supported, including control transfer (endpoint 0),

bulk, interrupt, and isochronous transfers.

4.8.2 Resources

4.8.2.1 Endpoint

This LSI includes endpoint 0 and five standard endpoints. Endpoint 0 supports control transfer. The standard

endpoints support bulk, interrupt, and isochronous transfers. The standard endpoint numbers, maximum packet

size, and transfer direction (IN/OUT) can be set as desired.

4.8.2.2 FIFO

This LSI includes 4.5 kB of FIFO for use with USB data transfer. This forms the data transfer route with USB.

The FIFO capacity for each endpoint can be assigned as desired through software. For example, performance

can be improved by assigning an adequate FIFO area to the endpoints for bulk transfers.

4.8.3 Data Flow

Endpoints are assigned to USB FIFO areas on a one-to-one basis. Responses are returned to USB transactions

automatically, depending on the USB FIFO effective free capacity (for OUT transfer) or effective data quantity

(for IN transfer). Thus, the software need not be directly involved in individual transactions, allowing USB data

S1R72C05*** Data Sheet (Rev.1.00)

EPSON

7

4. FUNCTIONS

transfers to be controlled as data flow on the USB FIFO.

CPU

USB FIFO

Write Read

Endpoint

USB Host

IN transaction

(NAK response)

IN transaction

(Data reply)

IN transaction

(NAK response)

IN transaction

(Data reply)

Empty

Data

Fig.4.4 Typical data flow (with FIFO assigned for MaxPktSize and IN transfer)

CPU

USB FIFO

Read Write

Endpoint

USB Host

PING transaction

(ACK response)

OUT transaction

(Data receipt)

PING transaction

(NAK response)

PING transaction

(ACK response)

Empty

Data

Note: PING transactions are performed only in High

Speed mode.

Fig.4.5 Typical data flow (with FIFO assigned for MaxPktSize and OUT transfer)

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EPSON

S1R72C05*** Data Sheet (Rev.1.00)

4. FUNCTIONS

4.8.4 USB Device Port External Circuits

This LSI has internal FS and HS device termination resistors, eliminating the need for additional components

normally used to adjust impedance. This allows a DP/DM line to be connected between the LSI terminal and the

connector. The appropriate components should be used to protect against static electricity and implement EMI

precautions.

The VBUS terminal uses a 5 V input and does not require external voltage conversion. However, a protection

circuit is recommended since certain commercially available USB host and hub products may apply surge

voltages that exceed VBUS ratings.

Refer to the “PCB Design Guidelines for S1R72V Series USB 2.0 High-Speed Devices” provided separately.

4.9 USB Host I/F

This LSI supports high-speed specification USB host functions that comply with USB 2.0 (Universal Serial

Bus Specification Revision 2.0) standards.

4.9.1 Speed Mode and Transfer Type

This LSI supports HS (480 Mbps), FS (12 Mbps) and LS (1.5 Mbps) speed modes when operating USB hosts.

The speed mode is automatically set through speed negotiation performed when the bus is reset.

All transfer types stipulated in the USB 2.0 standard are supported, including control, bulk, interrupt, and

isochronous transfers.

4.9.2 Resources

4.9.2.1 Channel

In this LSI, the setting register sets for transfers with end points on a one-to-one basis are referred to as

channels. This LSI features one dedicated channel for control transfers, one dedicated channel for bulk transfers,

and four general channels that support bulk, interrupt, and isochronous transfers. The endpoint number,

maximum packet size, and transfer direction (in/out) can be set as desired for all channels. Transfers are also

possible for a number of endpoints exceeding the number of channels using time-multiplexing for channels via

software.

4.9.2.2 FIFO

This LSI includes 4.5 kB of FIFO for use with USB data transfers. This forms the data transfer route with

USB. The FIFO capacity for each channel can be assigned as desired via software. For example, performance

can be improved by assigning a sufficient FIFO area to the channels for bulk transfers.

4.9.3 Data Flow

The channels are assigned to FIFO areas on a one-to-one basis, and transactions are automatically sent via

USB, depending on the FIFO effective free capacity (for IN transfers) or effective data quantity (for OUT

transfers). The software need not be directly involved in individual transactions, allowing the USB data transfer

to be controlled as data flow on the FIFO.

S1R72C05*** Data Sheet (Rev.1.00)

EPSON

9

4. FUNCTIONS

CPU

FIFO

Channel

USB Device

Read

Write

IN transaction

(NAK response)

IN transaction

(Data reply)

Empty

Data

IN transaction

(NAK response)

Fig.4.6 Typical data flow (with FIFO assigned for MaxPktSize and IN transfers)

CPU

FIFO

Channel

USB Device

Write

Read

OUT transaction

Empty

Data

Fig.4.7 Typical data flow (with FIFO assigned for MaxPktSize and OUT transfers)

10

EPSON

S1R72C05*** Data Sheet (Rev.1.00)

4. FUNCTIONS

4.9.4 USB Host Port External Circuits

This LSI features internal USB host termination resistors, including HS termination resistors, eliminating the

need for the external components typically used to adjust impedance. This allows the connection of a DP/DM

line between the LSI terminal and the connector. However, note that the appropriate components should be used

to protect against static electricity and to implement EMI precautions. External VBUS control components are

required for VBUS.

4.10 FIFO

4.10.1 USB FIFO

This LSI includes 4.5 kB of USB FIFO for use with USB data transfers. This is shared between USB device

I/F and USB host I/F. The USB FIFO capacity for each endpoint or channel can be assigned as desired via

software.

Transfers are possible between the USB-I/F and CPU-I/F via the USB FIFO or directly between the USB-I/F

and IDE-I/F.

4.10.2 Media FIFO

This LSI includes 64 B of Media FIFO for use with IDE data transfers. This forms the data transfer route with

the IDE-I/F and CPU-I/F. Data cannot be transferred to or from the USB-I/F with Media FIFO.

S1R72C05*** Data Sheet (Rev.1.00)

EPSON

11

5. TERMINAL LAYOUT DIAGRAMS

96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

HDA1 97

XHPDIAG 98

HDA0 99

LVDD 100

VSS 101

HVDD 102

HDA2 103

XHCS0 104

XHCS1 105

XHDASP 106

VBUSFLG_A 107

VBUSEN_A 108

LVDD 109

VSS 110

64 CVDD

63 LVDD

62 CD15

61 CD14

60 CD13

59 CD12

58 CD11

57 CD10

56 CD9

55 CD8

54 VSS

53 CD7

52 CD6

51 CD5

50 VSS

49 CVDD

48 CD4

47 CD3

S1R72C05F00Axxx

QFP15-128

R1_A 111

VSS 112

HVDD 113

DM_A 114

VSS 115

46 CD2

DP_A 116

HVDD 117

LVDD 118

VSS 119

TEST 120

TDO 121

45 CD1

44 CD0

43 VSS

42 LVDD

41 XDACK1

40 XDREQ1

39 XDACK0

TCK 122

XDREQ0

XINT

HVDD 123

TMS 124

38

37

TDI 125

36 VSS

35 CVDD

TRST 126

LVDD 127

XI 128

VSS

33 XWRL

34

1

2

3

4

5

6

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

7

Fig.5.1 QFP package terminal layout diagram

12

EPSON

S1R72C05*** Data Sheet (Rev.1.00)

5. TERMINAL LAYOUT DIAGRAMS

S1R72C05/PFBGA8UX121,PFBGA10UX121

TOP View

1

2

3

4

5

6

7

8

9

10

11

NC

XI

LVDD

DP_A

DM_A

HVDD

R1_A

LVDD

HDA0

NC

A

B

C

D

E

F

G

H

J

XO

VSS

TRST

TDI

VSS

TCK

HVDD

TEST

HVDD

VSS

VBUSEN_A

VBUSFLG_A

VSS

XHCS1

XHIOR

VSS

HDA2

HDA1

HDD0

HDD2

VSS

XHPDIAG

HINTRQ

HDMARQ

HDD13

HVDD

LVDD

R1_B

HVDD

DM_B

DP_B

LVDD

CA8

XHCS0

VSS

TDO

XHDASP

LVDD

CA2

XHDMACK HIORDY

XHIOW

HDD12

VSS

TMS

VSS

HDD14

LVDD

XDACK1

CD3

HDD15

HDD3

HVDD

CD6

VSS

HDD1

HDD5

CD13

CD10

CD12

HVDD

VSS

VBUS_B

CVDD

CA1

CA3

XINT

HDD11

CVDD

CD7

HDD10

HDD8

HDD6

CD14

HDD4

CA4

XDACK0

XDREQ1

CA7

HDD9

XRESET

XCS

XBEL

CA6

CD0

CD4

HDD7

CA5

CD1

CD5

CD9

XHRESET

K

L

NC

1

XRD

2

XWRH

3

XWRL

4

XDREQ0

5

CD2

6

CVDD

7

CD8

8

CD11

9

CD15

10

NC

11

Fig.5.2 BGA package terminal layout diagram

S1R72C05*** Data Sheet (Rev.1.00)

EPSON

13

6. TERMINAL FUNCTIONS

OSC

Terminal

type

Ball

Name

I/O

RESET

Terminal description

Internal oscillator circuit input

(12 MHz, 24 MHz)

128

1

A2

B1

XI

IN

Analog

Internal oscillator circuit output

XO

OUT

TEST

Terminal

type

Ball

Name

I/O

RESET

Terminal description

120

121

122

124

125

126

C5

D3

C4

E2

C3

B3

TEST

TDO

TCK

TMS

TDI

IN

OUT

IN

Test terminal (Must be fixed at Low)

Boundary scan TDO terminal

Boundary scan TCK terminal

Boundary scan TMS terminal

Boundary scan TDI terminal

Boundary scan TRST terminal

Hi-Z

2mA

TRST

IN

If the boundary scan function is not used, the TEST, TCK, TMS, TDI, and TRST terminals should all be set to Low and

the TDO terminal left open.

PD: Pull Down

PU: Pull Up

USB

Terminal

Ball

A8

Name

R1_A

I/O

RESET

Terminal description

type

Internal operation reference current setting

terminal (Connect 6.2 kΩ ±1% resistance

between VSS)

111

IN

Analog

USB host data line (Data +)

USB host data line (Data -)

116

114

A5

A6

DP_A

DM_A

BI

Hi-Z

Analog

Schmitt

USB power switch fault detection signal

(1: Normal, 0: Error)

USB power switch control signal

107

108

C7

B7

VBUSFLG_A

VBUSEN_A

IN

(PU)

Lo

(PU)

OUT

2mA

Internal operation reference current setting

terminal (Connect 6.2 kΩ ±1% resistance

between VSS)

5

D1

R1_B

IN

Analog

USB device data line (Data +)

USB device data line (Data -)

USB device bus detection signal

11

9

13

G1

F1

G3

DP_B

DM_B

VBUS_B

BI

IN

Hi-Z

(PD)

Analog

(PD)

PD: Pull Down

PU: Pull Up

14

EPSON

S1R72C05*** Data Sheet (Rev.1.00)

6. TERMINAL FUNCTIONS

CPU I/F

Terminal

type

Pin Ball

Name

I/O

RESET

Terminal description

16bit Strobe mode

16bit BE mode

Bus Mode ⇒

20

31

J2

L2

XRESET

XRD

IN

Reset signal

Read strobe

33

L4

XWRL (XWR)

IN

Write strobe (lower)

Write strobe (upper)

Write strobe

32

30

L3

K2

XWRH (XBEH)

XCS

IN

High-byte enable

Chip select signal

2mA

37

G5

XINT

OUT

High

Interrupt signal

(Tri-state)

38

39

40

41

L5

H5

J5

XDREQ0

XDACK0

XDREQ1

XDACK1

OUT

IN

OUT

IN

2mA

DMA0 request

DMA0 acknowledge

DMA1 request

High

2mA

G6

DMA1 acknowledge

Must be fixed at High or

21

J4

XBEL

IN

Low-byte enable

Low

22

23

24

25

26

27

28

29

44

45

46

47

48

51

52

53

55

56

57

58

59

60

61

62

J3

CA1

CA2

CA3

CA4

CA5

CA6

CA7

CA8

CD0

CD1

CD2

CD3

CD4

CD5

CD6

CD7

CD8

CD9

CD10

CD11

CD12

CD13

CD14

CD15

IN

BI

F4

G4

H4

K3

K4

K5

K1

J6

K6

L6

H6

J7

K7

H7

J8

L8

K8

J9

CPU bus address

Hi-Z

2mA

CPU data bus

L9

K9

H9

K10

L10

The XINT terminal can be set to 1/0 or Hi-Z/0 mode, depending on register settings.

PD: Pull Down

PU: Pull Up

S1R72C05*** Data Sheet (Rev.1.00)

EPSON

15

6. TERMINAL FUNCTIONS

IDE I/F

Terminal

type

4mA

(PD)

4mA

(PU)

(PD)

4mA

(PU)

4mA(PU)

4mA(PD)

4mA(PU)

Ball

Name

HDA2

HDA1

I/O

RESET

Terminal description

IDE register address

103

97

99

105

104

93

92

91

95

94

96

68

106

98

90

87

84

82

77

75

72

70

69

71

74

76

81

83

86

88

B10

C10

A10

C9

C6

D9

D8

D11

D6

OUT

IN

OUT

IN

OUT

IN

BI

Hi-Z

(PD)

Hi-Z

(PU)

(PD)

Hi-Z

(PU)

Hi-Z

(PD)

Hi-Z

HDA0

XHCS1

XHCS0

XHIOR

XHIOW

HDMARQ

XHDMACK

HIORDY

HINTRQ

XHRESET

XHDASP

XHPDIAG

HDD15

HDD14

HDD13

HDD12

HDD11

HDD10

HDD9

HDD8

HDD7

HDD6

HDD5

HDD4

HDD3

HDD2

HDD1

Control register access chip select

Command block register access chip select

IDE read strobe

IDE write strobe

DMA transfer request

DMA transfer acknowledgement

IDE register ready signal

IDE interrupt request

IDE bus reset

Drive enable/slave drive available

D7

C11

K11

D4

B11

E7

E6

E11

E8

Diagnostic sequence end signal

G8

G10

H11

H10

J11

J10

G9

G11

F7

E10

F9

IDE data bus

BI

D10

HDD0

PU and PD can be turned on or off via register settings.

PD: Pull Down

PU: Pull Up

Note: The IDE I/F terminals are all 5-V tolerant.

POWER

Ball

Name

HVDD

CVDD

Voltage

Terminal description

Power supply for IDE I/F I/O, USB I/O, and

TEST I/O

8, 12, 65, 80, 89,

102, 113, 117, 123

19, 35, 49, 64

3, 14, 17, 42, 63,

66, 78, 100, 109,

118, 127

G7, D5, F11, E1,

G2, B5, A7

3.3V

H3, L7, H8

J1, E4, F6, H1, A3,

A4 , C1, A9

1.8 to 3.3 V

Power supply for CPU I/F I/O

LVDD

1.8V

OSC I/O and internal power supply

2, 4, 6, 7, 10, 15,

18, 34, 36, 43, 50,

54, 67, 73, 79, 85,

101, 110, 112, 115,

119

F3, E3, E5, F5, C8,

F8, E9, F10, H2,

F2, B2, B4, B6, B8,

D2, C2, B9

VSS

N.C.

0V

GND

16

A1, L1, A11, L11

NC terminal (connect to GND)

16

EPSON

S1R72C05*** Data Sheet (Rev.1.00)

7. ELECTRICAL CHARACTERISTICS

7.1 Absolute Maximum Ratings

Item

Symbol

HVDD

CVDD

LVDD

HVI

Rating

VSS - 0.3 to 4.0

VSS - 0.3 to 2.5

Units

V

Power supply voltage

Input voltage

VSS - 0.3 to HVDD + 0.5

VSS - 0.3 to CVDD + 0.5

VSS - 0.3 to 5.5

CVI*1

IVI*2

V

VVI*3

LVI*4

HVO

CVO*1

IOUT

Tstg

VSS - 0.3 to 6.0

V

mA

°C

VSS - 0.3 to LVDD + 0.5

VSS - 0.3 to HVDD + 0.5

VSS - 0.3 to CVDD + 0.5

±10

Output voltage

Output current/terminal

Storage temperature

-65 to 150

*1 CPU-I/F

*2 IDE-I/F

*3 VBUS_B

*4 XI

7.2 Recommended Operating Conditions

Item

Symbol

HVDD

CVDD

LVDD

HVI

CVI*1

IVI*2

VVI*3

LVI*4

Ta

Min.

Typ.

3.30

Max.

3.60

1.95

Units

V

Power supply voltage

3.00

1.65

-0.3

-40

1.80

Input voltage

HVDD+0.3

CVDD+0.3

5.5

6.0

LVDD+0.3

85

Ambient temperature

25

°C

*1 CPU-I/F

*2 IDE-I/F

*3 VBUS_B

*4 XI

Power to the IC should be turned on in the sequence shown below.

LVDD (internal) → HVDD, CVDD (IO section)

Likewise, power to the IC should be turned off in the sequence shown below.

HVDD, CVDD (IO section) → LVDD (internal)

Note: Avoid leaving the HVDD or CVDD on continuously (for more than 1 second) when the

LVDD is off, since doing so may affect the chip reliability.

S1R72C05*** Data Sheet (Rev.1.00)

EPSON

17

7. ELECTRICAL CHARACTERISTICS

7.3 DC Characteristics

7.3.1 Current Consumption

Item

Power supply feed

Symbol

*1

Condition

Min.

Typ.

Max.

Units

current

Power supply

current

IDDH

HVDD = 3.3V(typ), HVDD =

3.6V(max)

41

1

65

4

mA

IDDCH

IDDCL

IDDL

CVDD = 3.3V(typ), CVDD =

3.6V(max)

CVDD = 1.8V(typ), CVDD =

1.95V(max)

0.7

75

2

LVDD = 1.8V(typ), LVDD =

120

1.95V(max)

Stationary current

*2

Power supply

IDDS

VIN = HVDD,CVDD,LVDD or

VSS

current

HVDD = 3.6V

80

µA

CVDD = 3.6V

LVDD = 1.95V

Input leakage

IL

HVDD = 3.6V

CVDD = 3.6V

LVDD = 1.95V

HVIH = HVDD

CVIH = CVDD

LVIH = LVDD

VIL = VSS

current

-5

5

µA

Input leakage

ILIF

HVDD = 3.0V

CVDD = 1.65V

LVDD = 1.65V

HVOH = 5.5V

current

-10

10

(5-V tolerant)

*1: Typ values are measured with the USB-HDD connected as USB host and when transferring data between the

IDE-HDD and USB-HDD (actual transfer rate 30 MB/s). Max. values are estimated from these values.

*2: Stationary current with Ta = 25°C and both terminals in input mode.

18

EPSON

S1R72C05*** Data Sheet (Rev.1.00)

7. ELECTRICAL CHARACTERISTICS

Current consumption measurements for various power management states using Seiko Epson operating

conditions (Ta = 25°C)

Item

Condition

CPU bus operation *1 *2

Min.

Typ.

Max.

Units

SLEEP

Power supply power

HVDD = 3.3V

CVDD = 3.3V

LVDD = 1.8V

0.23

mW

SNOOZE

CPU bus operation *1 *2

Power supply power

HVDD = 3.3V

CVDD = 3.3V

LVDD = 1.8V

1.8

41

mW

*3

ACTIVE60(IDE⇔CPU)

Power supply power

HVDD = 3.3V

CVDD = 3.3V

LVDD = 1.8V

*4

ACT_DEVICE(IDE⇔USB)

Power supply power

HVDD = 3.3V

CVDD = 3.3V

LVDD = 1.8V

131

134

273

Copy *5

ACT_HOST(IDE⇔USB)

Power supply power

HVDD = 3.3V

CVDD = 3.3V

LVDD = 1.8V

Direct Copy *6

ACT_HOST(IDE⇔USB)

Power supply power

HVDD = 3.3V

CVDD = 3.3V

LVDD = 1.8V

*1: When the CPU is accessing memory (e.g., SRAM or ROM) connected to the CPU bus.

*2: Excluding current consumption due to internal S1R72C05 DP pull-up resistor (approx. 200 µA).

*3: When transferring data between the IDE-HDD and CPU (actual transfer rate 4 MB/s).

*4: When connected to the PC as a USB device and when transferring data between the IDE-HDD and USB (actual

transfer rate 25 MB/s).

*5: With the USB-HDD connected as USB host and when transferring data between the IDE-HDD and USB-HDD

(actual transfer rate 5.3 MB/s).

*6: With the USB-HDD connected as USB host and when transferring data between the IDE-HDD and USB-HDD

(actual transfer rate 30 MB/s).

S1R72C05*** Data Sheet (Rev.1.00)

EPSON

19

7. ELECTRICAL CHARACTERISTICS

7.3.2 Input Characteristics

Item

Symbol

Condition

Min.

Typ.

Max.

Units

Input characteristics

Terminal name: TEST, TDI, TCK, TRST, TMS

(LVCMOS)

H-level input voltage

L-level input voltage

VIH1

VIL1

HVDD = 3.6V

HVDD = 3.0V

2.2

V

0.8

Input characteristics

Terminal name: CA[8:1], CD[15:0], XCS, XRD, XWRL, XWRH, XBEL, XDACK0,

(LVCMOS)

XDACK1, XRESET

H-level input voltage

L-level input voltage

H-level input voltage

L-level input voltage

VIH2

VIL2

VIH3

VIL3

CVDD = 3.6V

CVDD = 3.0V

CVDD = 1.95V

CVDD = 1.65V

2.2

V

0.8

1.27

0.57

Input characteristics

Terminal name: HDD[15:0], HDMARQ, HIORDY, HINTRQ, XHDASP, XHPDIAG

(LVCMOS)

H-level input voltage

L-level input voltage

VIH4

VIL4

HVDD = 3.6V

HVDD = 3.0V

2.2

V

0.8

Schmitt input

Terminal name: VBUSFLG_A

characteristics

H-level trigger voltage

L-level trigger voltage

Hysteresis voltage

VT+

VT-

∆V

HVDD = 3.6V

HVDD = 3.0V

1.4

0.6

0.3

2.7

1.8

V

Schmitt input

Terminal name: DP_A, DM_A, DP_B, DM_B

characteristics (USB FS)

H-level trigger voltage

L-level trigger voltage

Hysteresis voltage

VT+(USB)

VT-(USB)

∆V(USB)

HVDD = 3.6V

HVDD = 3.0V

1.1

1.0

0.1

1.8

1.5

V

Input characteristics

Terminal name: DP_A + DM_A pair, DP_B + DM_B pair

(USB FS differential)

Differential input

sensitivity

VDS(USB)

HVDD = 3.0V

Differential input voltage

0.2V

V

= 0.8 V to 2.5 V

Input characteristics

(VBUS)

Terminal name: VBUS_B

H-level trigger voltage

L-level trigger voltage

Hysteresis voltage

Input characteristics

Pull-up resistor

Input characteristics

Pull-down resistor

Input characteristics

Pull-down resistor

VT+(VBUS)

VT-(VBUS)

∆V(VBUS)

HVDD = 3.6V

HVDD = 3.0V

1.86

1.48

0.31

2.85

2.23

0.64

V

Terminal name: HDD[15:8], HDD[6:0], HIORDY, XHDASP, XHPDIAG, VBUSFLG_A

RPLU

Terminal name: HDD[7], HDMARQ, HINTRQ

RPLD

Terminal name: VBUS_B

RPLDV

VIL = VSS

50

100

125

240

150

kΩ

VIH = HVDD

50

VIH = 5.0V

110

20

EPSON

S1R72C05*** Data Sheet (Rev.1.00)

7. ELECTRICAL CHARACTERISTICS

7.3.3 Output Characteristics

Item

Symbol

Condition

Min.

Typ.

Max.

Units

Output characteristics

Terminal name: CD[15:0], XDREQ0, XDREQ1, XINT

H-level output voltage

VOH1

VOL1

VOH2

VOL2

CVDD = 3.0V

IOH = -2mA

CVDD-

0.4

V

L-level output voltage

H-level output voltage

L-level output voltage

Output characteristics

H-level output voltage

L-level output voltage

CVDD = 3.0V

VSS+0.4

IOL = 2mA

CVDD = 1.65V

IOH = -1mA

CVDD-

0.4

CVDD = 1.65V

IOL = 1mA

Terminal name: HDD[15:0], HDA[2:0], XHCS1, XHCS0, XHIOR, XHIOW, XHDMACK,

XHRESET

VOH3

HVDD = 3.0V

HVDD-

V

IOH = -4mA

1.0

VOL3

HVDD = 3.0V

IOL = 4mA

VSS+0.4

Output characteristics

H-level output voltage

Terminal name: TDO, VBUSEN_A

VOH4

HVDD = 3.0V

HVDD-

0.4

V

IOH = -2mA

L-level output voltage

VOL4

HVDD = 3.0V

IOL = 2mA

VSS+0.4

0.3

Output characteristics

(USB FS)

Terminal name: DP_A, DM_A, DP_B, DM_B

H-level output voltage

L-level output voltage

VOH(USB) HVDD=3.0V

2.8

V

VOL(USB)

HVDD=3.6V

Output characteristics

Terminal name: DP_A, DM_A, DP_B, DM_B

(USB HS)

H-level output voltage

L-level output voltage

Output characteristics

VHSOH

(USB)

HVDD = 3.0V

HVDD = 3.6V

360

mV

VHSOL

10.0

5

(USB)

Terminal name: CD[15:0], XINT

IOZ

OFF-STATE leakage

HVDD = 3.6V

CVDD = 1.95V

CVOH = CVDD

VOL = VSS

current

-5

µA

Output characteristics

Terminal name: HDD[15:0], HDA[2:0], XHCS1, XHCS0, XHIOR, XHIOW, XHDMACK,

XHRESET

OFF-STATE leakage

current (5-V tolerant)

IOZHF

HVDD = 3.0V

HVOH = 5.5V

-10

10

µA

S1R72C05*** Data Sheet (Rev.1.00)

EPSON

21

7. ELECTRICAL CHARACTERISTICS

7.3.4 Terminal Capacitance

Item

Symbol

Condition

Min.

Typ.

Max.

Units

Terminal capacitance

Terminal name: All input terminals

Input terminal

CI

f = 10MHz

10

pF

capacitance

HVDD = CVDD = LVDD = VSS

Terminal capacitance

Terminal name: All output terminals

Output terminal

CO

f = 10MHz

10

pF

capacitance

HVDD = CVDD = LVDD = VSS

Terminal capacitance

Terminal name: All input/output terminals (except DP_A, DM_A, DP_B, DM_B)

Input/output terminal CIO1

f = 10MHz

10

capacitance 1

HVDD = CVDD = LVDD = VSS

Terminal capacitance

Terminal name: DP_A, DM_A, DP_B, DM_B

Input/output terminal CIO2

f = 10MHz

capacitance 2

HVDD = CVDD = LVDD = VSS

7.4 AC Characteristics

7.4.1 Reset Timing

tRESET

XRESET

Code

Description

Reset pulse width

Min.

Typ.

Max.

Units

40

ns

tRESET

7.4.2 Clock Timing

tCYC

tCYCL

tCYCH

XI

Code

Description

Min.

Typ.

Max.

Units

Clock cycle (ClkSelect=0)

Clock cycle (ClkSelect=1)

Clock duty

11.999

12

12.001

MHz

tCYC

23.998

45

24

24.002

55

MHz

%

tCYC

tCYCH

tCYCL

22

EPSON

S1R72C05*** Data Sheet (Rev.1.00)

7. ELECTRICAL CHARACTERISTICS

7.4.3 CPU/DMA I/F Access Timing

7.4.3.1 Specifications for CVDD = 1.65 V to 3.6 V

tcas

tcah

tcch

CA(I)

tccn

tccs

XCS(I)

XRD(I)

trcy

tras

trng

trdf

trbh

Read

Write

trbd

trdh

CD(O)

Valid

twcy

XWRH/L(I)

XWR

twas

twng

twbs

twbh

XBEH/L(I)

twah

twds

twdh

CD(I)

tdrn

XDREQ0/1(O)

XDACK0/1(I)

tdaa

tdan

(CL=30pF)

Code

tcas

tcah

tccs

tcch

tccn

trcy

Item

Min.

6

Typ.

Max.

unit

ns

Address setup time

Address hold time

XCS setup time

XCS hold time

6

XCS Negate time (Only when CPUIF mode is set*)

Read cycle

15

80

40

25

1

Read strobe assert time

tras

Read strobe negate time

trng

trbd

trdf

Read data output start time

Read data confirmation time

Read data hold time

35

10

3

trdh

trbh

twcy

twas

twng

twbs

twbh

twds

twdh

twah

tdrn

tdaa

tdan

Read data output delay time

Write cycle

80

40

25

6

Write strobe assert time

Write strobe negate time

Write byte enable setup time

Write byte enable hold time

Write data acknowledge delay time

Write data hold time (after strobe negation)

Write data hold time (after strobe assertion)

XDREQ0/1 negate delay time

XDACK0/1 setup time

6

10

35

6

50

6

XDACK0/1 hold time

* For details of CPUIF mode setting, refer to “Technical Manual.”

S1R72C05*** Data Sheet (Rev.1.00)

EPSON

23

7. ELECTRICAL CHARACTERISTICS

7.4.3.2 Specifications When Limited to CVDD = 3.0 V to 3.6 V

tcas

tcah

CA(I)

tccn

tccs

tcch

XCS(I)

XRD(I)

trcy

tras

trng

trdf

trbh

Read

Write

trbd

trdh

CD(O)

Valid

twcy

XWRH/L(I)

XWR

twas

twng

twbs

twbh

twdh

XBEH/L(I)

twah

twds

CD(I)

tdrn

XDREQ0/1(O)

XDACK0/1(I)

tdaa

tdan

(CL=30pF)

Max.

Code

tcas

tcah

tccs

tcch

tccn

trcy

Item

Min.

6

Typ.

unit

ns

Address setup time

Address hold time

XCS setup time

XCS hold time

6

XCS Negate time (Only when CPUIF mode is set*)

Read cycle

15

75

37

25

1

Read strobe assert time

tras

Read strobe negate time

trng

trbd

trdf

Read data output start time

Read data confirmation time

Read data hold time

30

10

3

trdh

trbh

twcy

twas

twng

twbs

twbh

twds

twdh

twah

tdrn

tdaa

tdan

Read data output delay time

Write cycle

75

37

25

6

Write strobe assert time

Write strobe negate time

Write byte enable setup time

Write byte enable hold time

Write data acknowledge delay time

Write data hold time (after strobe negation)

Write data hold time (after strobe assertion)

XDREQ0/1 negate delay time

XDACK0/1 setup time

6

10

30

6

50

6

XDACK0/1 hold time

* For details of CPUIF mode setting, refer to “Technical Manual.”

24

EPSON

S1R72C05*** Data Sheet (Rev.1.00)

7. ELECTRICAL CHARACTERISTICS

7.4.4 IDE I/F Timing

7.4.4.1 PIO Read Timing

DATA

Data transfer direction:

S1R72C05

XHCS0(O)

T321

T322

HDA[2:0](O)

T323

T324

T325

T326

XHIOR(O)

T327

stable

T328

HDD[15:0](I)

stable

T329

HIORDY(I)

Code

Description

XHCS0 ↓ → HDA

Min.

Typ.

Max.

Units

T321

T322

T323

T324

T325

T326

T327

T328

T329

0

ns

HDA output delay time

XHCS0 ↑ → HDA

0

ns

HDA hold time

XHCS0 ↓ → XHIOR ↓

80

XHCS0 setup time

(AP+4) *

XHIOR ↓ → XHIOR ↑

16.7 - 3

XHIOR assert pulse width

(NP+4) *

XHIOR ↑ → XHIOR ↓

16.7 + 3

XHIOR negate pulse width

XHIOR ↑ → XHCS0 ↑

50

10

0

XHCS0 hold time

HDD → XHIOR ↑

Data setup time

XHIOR ↑ → HDD

Data hold time

HIORDY ↑ → XHIOR ↑

25

XHIOR output delay time

*1: AP = IDE_Tmod.AssertPulseWidth, NP = IDE_Tmod.NegatePulseWidth

For detailed information, refer to “IDE Transfer Mode” in the register description.

S1R72C05*** Data Sheet (Rev.1.00)

EPSON

25

7. ELECTRICAL CHARACTERISTICS

7.4.4.2 PIO Write Timing

DATA

Data transfer direction

S1R72C05

XHCS0(O)

T331

T332

HDA[2:0](O)

T333

T334

T335

T336

XHIOW(O)

T337

T338

HDD[15:0](O)

valid

T339

HIORDY(I)

Code

Description

Min.

Typ.

Max.

Units

XHCS0 ↓ → HDA

T331

0

ns

HDA output delay time

XHCS0 ↑ → HDA

T332

T333

T334

T335

T336

T337

T338

T339

0

ns

HDA hold time

XHCS0 ↓ → XHIOW ↓

80

XHCS0 setup time

(AP+4) *

XHIOW ↓ → XHIOW ↑

16.7 - 3

XHIOW assert pulse width

(NP+4) *

XHIOW ↑ → XHIOW ↓

16.7 + 3

XHIOW negate pulse width

XHIOW ↑ → XHCS0 ↑

50

0

XHCS0 hold time

XHIOW ↓ → HDD

10

45

25

Data output delay time

XHIOW ↑ → HDD

33

Data bus negate time

HIORDY ↑ → XHIOW ↑

XHIOW output delay time

*1: AP = IDE_Tmod.AssertPulseWidth, NP = IDE_Tmod.NegatePulseWidth

For detailed information, refer to “IDE Transfer Mode” in the register description.

26

EPSON

S1R72C05*** Data Sheet (Rev.1.00)

7. ELECTRICAL CHARACTERISTICS

7.4.4.3 DMA Read Timing

DATA

Data transfer direction:

S1R72C05

XHCS[1:0](O)

HDA[2:0](O)

HDMARQ(I)

XHDMACK(O)

XHIOR(O)

T342

T341

T344

T343

T346

T347

T348

T345

T349

stable

T34a

HDD[15:0](I)

stable

Code

Description

Min.

Typ.

Max.

Units

XHCS ↑, HDA → XHDMACK ↓

T341

T342

T343

T344

T345

T346

T347

T348

T349

T34a

70

ns

Address setup time

XHIOR ↑ → XHCS ↑, HAD

50

17

0

ns

Address hold time

HDMARQ ↑ → XHDMACK ↓

↓ XHDMACK response time

XHIOR ↓ → HDMARQ negate

HDMARQ hold time

XHDMACK ↓ → XHIOR ↓

0

XHDMACK setup time

(AP+4) *

XHIOR ↓ → XHIOR ↑

XHIOR assert pulse width

16.7 - 3

(NP+4) *

XHIOR ↑ → XHIOR ↓

XHIOR negate pulse width

16.7 + 3

XHIOR ↑ → XHDMACK ↑

30

10

0

90

XHDMACK hold time

HDD → XHIOR ↑

Data setup time

XHIOR ↑ → HDD

Data bus hold time

*1: AP = IDE_Tmod.AssertPulseWidth, NP = IDE_Tmod.NegatePulseWidth

For detailed information, refer to “IDE Transfer Mode” in the register description.

S1R72C05*** Data Sheet (Rev.1.00)

EPSON

27

7. ELECTRICAL CHARACTERISTICS

7.4.4.4 DMA Write Timing

DATA

Data transfer direction:

S1R72C05

XHCS[1:0](O)

HDA[2:0](O)

T352

HDMARQ(I)

T351

T354

XHDMACK(O)

T353

T356

T357

T358

XHIOW(O)

T355

T359

T35a

HDD[15:0](O)

valid

Code

Description

Min.

Typ.

Max.

Units

XHCS ↑, HDA → XHDMACK ↓

T351

70

50

17

0

ns

Address setup time

XHIOW ↑ → XHCS ↑, HDA

T352

T353

T354

T355

T356

T357

T358

T359

T35a

Address hold time

HDMARQ ↑ → XHDMACK ↓

XHDMACK response time

XHIOW ↓ → HDMARQ negate

HDMARQ hold time

XHDMACK ↓ → XHIOW ↓

0

XHDMACK setup time

(AP+4) *

XHIOW ↓ → XHIOW ↑

16.7 - 3

XHIOW assert pulse width

(NP+4) *

XHIOW ↑ → XHIOW ↓

16.7 + 3

XHIOW negate pulse width

XHIOW ↑ → XHDMACK ↑

30

0

90

10

45

XHDMACK hold time

XHIOW ↓ → HDD

Data output delay time

XHIOW ↑ → HDD

33

Data bus hold time

*1: AP = IDE_Tmod.AssertPulseWidth, NP = IDE_Tmod.NegatePulseWidth

For detailed information, refer to “IDE Transfer Mode” in the register description.

28

EPSON

S1R72C05*** Data Sheet (Rev.1.00)

7. ELECTRICAL CHARACTERISTICS

7.4.4.5 Ultra DMA Read Timing

DATA

Data transfer direction:

S1R72C05

Initiating

Host Pausing

XHCS[1:0](O)

HDA[2:0](O)

T361

HDMARQ(I)

T362

XHDMACK(O)

T363

XHIOW(O)

(STOP)

T363

XHIOR(O)

(HDMARDY)

T368

T366

HIORDY(I)

(DSTROBE)

T366

T364

T365

T367

HDD[15:0](I)

stable

Code

Description

Min.

Typ.

Max.

Units

XHCS ↑, HDA → XHDMACK ↓

T361

80

ns

Address setup time

HDMARQ ↑ → XHDMACK ↓

T362

T363

T364

T365

T366

T367

T368

65

28

4

ns

XHDMACK response time

XHDMACK ↓ → XHIOR(W) ↓

40

Envelope time

HDD → HIORDY

Data setup time

HIORDY → HDD

4

Data hold time

HIORDY → HIORDY

15

30

HIORDY cycle time

HIORDY → HIORDY

HIORDY cycle time x2

IDE spec.

tRFS

XHIOR ↑ → HIORDY

Final STROBE time

S1R72C05*** Data Sheet (Rev.1.00)

EPSON

29

7. ELECTRICAL CHARACTERISTICS

Ultra DMA Read Timing (continued)

DATA

CRC

Data transfer direction:

S1R72C05

Host Terminating

XHCS[1:0](O)

Device Terminating

HDA[2:0](O)

T377

HDMARQ(I)

T373

T375

XHDMACK(O)

T371

T372

XHIOW(O)

(STOP)

T37a

XHIOR(O)

(XHDMARDY)

T376

T37b

HIORDY(I)

(DSTROBE)

T378

T379

T378

T379

T374

HDD[15:0](O)

(CRC)

CRC

stable

Code

Description

Min.

Typ.

Max.

Units

XHIOR ↑ → XHIOW ↑

T371

T372

T373

T374

T375

T376

T377

T378

T379

T37a

T37b

180

ns

Time to STOP assert

IDE spec.

tRFS

XHIOR ↑ → HIORDY

ns

Final STROBE time

IDE spec.

tLI

XHIOW ↑ → HDMARQ ↓

Restricted interlock time

HDMARQ ↓ → HDD

70

160

110

35

Output delay time

HDMARQ ↓ → XHDMACK ↑

Minimum interlock time

HIORDY → XHDMACK ↑

Minimum interlock time

XHDMACK ↑ → XHCS0, 1

XHCS0, 1 hold time

HDD(CRC) → XHDMACK ↑

75

CRC data setup time

XHDMACK ↑ → HDD(CRC)

12

CRC data hold time

HDMARQ ↓ → XHIOR ↑

20

38

Restricted interlock time

HIORDY → XHDMACK ↑

110

Minimum interlock time

30

EPSON

S1R72C05*** Data Sheet (Rev.1.00)

7. ELECTRICAL CHARACTERISTICS

7.4.4.6 Ultra DMA Write Timing

DATA

Data transfer direction:

S1R72C05

Initiating

Device Pausing

XHCS[1:0](O)

HDA[2:0](O)

HDMARQ(I)

T381

T382

XHDMACK(O)

T384

T385

XHIOW(O)

(STOP)

T389

XHIOR(O)

T386

(HSTROBE)

T38a

HIORDY(I)

T38b

(XDDMARDY)

T387

T388

HDD[15:0](O)

valid

Code

Description

Min.

Typ.

Max.

Units

XHCS ↑, HDA → XHDMACK ↓

T381

T382

T384

T385

T386

T387

T388

T389

T38a

T38b

80

ns

Address setup time

HDMARQ ↑ → XHDMACK ↓

65

28

ns

XHDMACK response time

XHDMACK ↓ → XHIOW ↓

40

Envelope time

IDE spec.

tLI

IDE spec.

tLI

XHIOW ↓ → HIORDY ↓

Restricted interlock time

HIORDY ↓ → XHIOR ↓

20

Unrestricted interlock time

(cyc+1) *

HDD → XHIOR ↓

16.7

Data setup time

(cyc+1) *

XHIOR ↓ → HDD

16.7

Data hold time

(cyc+2) *

XHIOR → XHIOR

16.7

XHIOR cycle time

XHIOR → XHIOR

T389 * 2

XHIOR cycle time x2

HIORDY ↑ → XHIOR

20

38

Final STROBE time

*1: cyc = UltraDMAcycle

For detailed information, refer to “IDE Ultra-DMA Transfer Mode” in the register description.

S1R72C05*** Data Sheet (Rev.1.00)

EPSON

31

7. ELECTRICAL CHARACTERISTICS

7.4.5 USB I/F Timing

Conforms to USB 2.0 standard

<Universal Serial Bus Specification Revision 2.0 Released on April 27, 2000>.

32

EPSON

S1R72C05*** Data Sheet (Rev.1.00)

8. CONNECTION EXAMPLES

8.1 CPU I/F Connection Example

Address[8:1]

CA[8:1]

XBEL

DATA[15:0]

XCS

DATA[15:0]

XCS

XRD

XWRH

XWRL

XWRH/XBEH

XWRL/XWR

XDREQ0 *1

XDACK0 *2

XDREQ1 *1

XDACK1 *2

XINT

XDREQ0

XDACK0

XDREQ1

XDACK1

XINT

*1: Open when DMA is not used

*2: Fixed at inactive level when

DMA is not used

16-bit CPU (XWRH/XWRL) connection example

Address[8:1]

XBEL

CA[8:1]

XBEL

DATA[15:0]

XCS

DATA[15:0]

XCS

XRD

XBEH

XWR

XWRH/XBEH

XWRL/XWR

XDREQ0 *1

XDACK0 *2

XDREQ1 *1

XDACK1 *2

XINT

XDREQ0

XDACK0

XDREQ1

XDACK1

XINT

*1: Open when DMA is not used

*2: Fixed at inactive level when

DMA is not used

16-bit CPU (XBEH/XBEL) connection example

S1R72C05*** Data Sheet (Rev.1.00)

EPSON

33

8. CONNECTION EXAMPLES

8.2 USB I/F Connection Example

8.2.1 For QFP15-128 (Device Periphery)

S1R72C05

QFP15-128

Top View

1u

127 LVDD

128 XI

Cg

Cd

Rd

6.2k

±1%

1u

0.1u

HVDD(3.3V±0.3V)

LVDD(1.8V±0.15V)

VSS

Static protection varistor

1u

10

Cg, Cd, Rd: As required

to USB B_Connector

The oscillator circuit must match the quartz

resonator. Contact the quartz resonator

manufacturer for detailed information on circuit

constants.

For detailed information on USB peripheral circuits,

refer to the "PCB Design Guidelines for S1R72V

Series USB 2.0 High-Speed Devices."

Select power supply elements carefully; their performance will affect USB signal waveform quality.

34

EPSON

S1R72C05*** Data Sheet (Rev.1.00)

8. CONNECTION EXAMPLES

8.2.2 For QFP15-128 (Host Periphery)

VBUS control circuit

OUT

FLG

ENB

107 VBUSFLG_A

108 VBUSEN_A

109 LVDD

110 VSS

1u

6.2k

±1%

111 R1_A

112 VSS

113 HVDD

114 DM_A

115 VSS

116 DP_A

117 HVDD

118 LVDD

119 VSS

S1R72C05

QFP15-128

0.1u

Top View

Static protection varistor

1u

VCC(5.0V±0.5V)

HVDD(3.3V±0.3V)

LVDD(1.8V±0.15V)

VSS

For detailed information on USB peripheral circuits,

refer to the "PCB Design Guidelines for S1R72V

Series USB 2.0 High-Speed Devices."

The VBUS circuit is shown for reference purposes

only and should not be interpreted as a recommended

configuration. Select components and circuit type to

suit individual system requirements.

Caution is required with components using FET

switches, since a current flows from the OUT terminal

to the IN terminal if the OUT terminal voltage exceeds

the IN terminal voltage, whether enabled or disabled

by the parasitic diode between the source and drain.

Select power supply elements carefully; their performance will affect USB signal waveform quality.

S1R72C05*** Data Sheet (Rev.1.00)

EPSON

35

8. CONNECTION EXAMPLES

8.2.3 For PFBGA8UX121/PFBGA10UX121 (Device Periphery)

Cd

Cg

Rd

1u

A2

^A3LV

DD

XI

B1

^B2VS

S

XO

^C1LV

DD

^C2VS

S

S1R72C05

1u

PFBGA8UX121

PFBGA10UX121

D1

R1_

^D2VS

S

B

Top View

6.2k

±1%

^E1HV

DD

0.1u

F1

DM

^F2VS

S

Static protection varistor

_B

G1

G2

G3

VBU

S_B

DP

HV

_B

DD

^H1LV

DD

^H2VS

S

0.1u

10

1u

C11, C12, Rd: As required

The oscillator circuit must match the quartz

resonator. Contact the quartz resonator

manufacturer for detailed information on circuit

constants.

HVDD(3.3V±0.3V)

For detailed information on USB peripheral circuits,

refer to the "PCB Design Guidelines for S1R72V

Series USB 2.0 High-Speed Devices."

LVDD(1.8V±0.15V)

VSS

Select power supply elements carefully; their performance will affect USB signal waveform quality.

36

EPSON

S1R72C05*** Data Sheet (Rev.1.00)

8. CONNECTION EXAMPLES

8.2.4 For PFBGA8UX121/PFBGA10UX121 (Host Periphery)

to USB A_Connector

OUT

FLG

ENB

0.1u

Static

protection

varistor

0.1u

1u

6.2k

±1%

A8

R1_

^A4LV

DD

^A5DP

_A

^A7HV

DD

^A9LV

DD

A6

DM

_A

A

B6

VS

^B4VS

S

^B5HV

DD

^B8VS

S

^B9VS

S

B7

VBU

SEN

_A

S

C6

VBU

SFL

G_A

S1R72C05

PFBGA8UX121

PFBGA10UX121

Top View

For detailed information on USB peripheral circuits,

refer to the "PCB Design Guidelines for S1R72V

Series USB 2.0 High-Speed Devices."

The VBUS circuit is shown for reference purposes

only, and should not be interpreted as a

recommended configuration. Select the components

and circuit type to suit individual system requirements.

Caution is required with components using FET

switches, since a current flows from the OUT terminal

to the IN terminal if the OUT terminal voltage exceeds

the IN terminal voltage, whether enabled or disabled

by the parasitic diode between the source and drain.

VCC(5.0V±0.5V)

HVDD(3.3V±0.3V)

LVDD(1.8V±0.15V)

VSS

Select power supply elements carefully; their performance will affect USB signal waveform quality.

S1R72C05*** Data Sheet (Rev.1.00)

EPSON

37

9. PRODUCT CODES

Table 9.1 Product codes

Product code

Product type

S1R72C05B08****

S1R72C05B10****

S1R72C05F15****

PFBGA8UX121 package

PFBGA10UX121 package

QFP15-128 package

38

EPSON

S1R72C05*** Data Sheet (Rev.1.00)

10. EXTERNAL DIMENSION DIAGRAMS

Refer the attached diagrams on the end of this document.

ꢀ QFP Package(QFP15-128)

ꢀ BGA Package (PFBGA8UX121)

ꢀ BGA Package (PFBGA10UX121)

S1R72C05*** Data Sheet (Rev.1.00)

EPSON

39

EXTERNAL DIMENSION DIAGRAMS

Revision History

Description of revision

Page

Date

Rev.

Classification

New

Description

(old issue)

08/21/2007

1.00

All pages

New issue

40

EPSON

S1R72C05*** Data Sheet (Rev.1.00)

Top View

D

A1 Corner

Index

Bottom View

e

D

Z

Symbol

Nom

10

-

Max

-

Min

L

K

J

H

G

F

E

D

C

B

A

-

D

E

A

-

1.2

-

1

-

0.3

0.8

-

A

e

b

x

y

Z

-

0.38

0.48

0.08

0.1

-

D

E

1

-

A1 Corner

1 2 3 4 5 6 7 8 9 1011

P-TFBGA-121-1010-0.80(PFBGA10U-121)

2900-0002-01(Rev.1.1)

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FAX: +82-54-454-6093

SEIKO EPSON CORPORATION

SEMICONDUCTOR OPERATIONS DIVISION

IC Sales Dept.

IC International Sales Group

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Phone: +81-42-587-5814

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Document Code: 411234700

First Issue September 2007

Printed in JAPAN

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