CYRF8935_13,PDF,CYRF8935_13 PDF资料,Datasheet,下载CYRF8935

CYRF8935

WirelessUSB™-NL 2.4 GHz

Low Power Radio

WirelessUSB™-NL 2.4 GHz Low Power Radio

using a differentiated single-mixer, closed-loop modulation

design that optimizes power efficiency and interference

immunity. Closed-loop modulation effectively eliminates the

problem of frequency drift, enabling WirelessUSB-NL to transmit

up to 255-byte payloads without repeatedly having to pay power

penalties for re-locking the phase locked loop (PLL) as in

open-loop designs.

Features

■ Fully integrated 2.4-GHz radio on a chip

■ 1-Mbps over-the-air data rate

■ Transmit power typical: 0 dBm

■ Receive sensitivity typical: –87 dBm

■ 1 µA typical ^[1]current consumption in sleep state

■ Closed-loop frequency synthesis

Among the advantages of WirelessUSB-NL are its fast lock times

and channel switching, along with the ability to transmit larger

payloads. Use of longer payload packets, compared to multiple

short payload packets, can reduce overhead, improve overall

power efficiency, and help alleviate spectrum crowding.

■ Supports frequency-hopping spread spectrum

Combined with Cypress's enCoRe™ family of USB and wireless

microcontrollers, WirelessUSB-NL also provides the lowest bill

of materials (BOM) cost solution for PC peripheral applications

such as wireless keyboards and mice, as well as best-in-class

wireless performance in other demanding applications such as

toys, remote controls, fitness, automation, presenter tools, and

gaming.

■ On-chip packet framer with 64-byte first in first out (FIFO) data

buffer

■ Built-in auto-retry-acknowledge protocol simplifies usage

■ Built-in cyclic redundancy check (CRC), forward error

correction (FEC), data whitening

■ Supports DC ~ 12-MHz SPI bus interface

Applications

■ Additional outputs for interrupt request (IRQ) generation

■ Digital readout of received signal strength indication (RSSI)

■ Wireless keyboards and mice

■ Handheld remote controls

■ Wireless game controllers

■ Hobby craft control links

■ 4 × 4 mm quad flat no-leads (QFN) package, bare die, or wafer

sales

Product Description

■ Home automation

WirelessUSB™-NL, optimized to operate in the 2.4-GHz ISM

band, is Cypress's third generation of 2.4-GHz low-power RF

technology, bringing the next level of low-power performance

■ Industrial wireless links and networks

■ Cordless audio and low-rate video

into

a

small 4-mm × 4-mm footprint. WirelessUSB-NL

implements a Gaussian frequency-shift keying (GFSK) radio

Note

1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = 3 VDC, Ta = +25 °C.

IN

Cypress Semiconductor Corporation

Document Number: 001-61351 Rev. *J

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 21, 2013

CYRF8935

Logic Block Diagram

V_DD1...V_DD7

V_IN

V_OUT

V_{DD_IO}

LDO Linear

Regulator

GFSK

Modulator

PKT

PA

FIFO

SPI_SS

CLK

ANT

VCO

Synthesizer

ANTb

MISO

MOSI

RST_n

Pwr/ Reset

[2]

BRCLK

GFSK

Demodulator

X

Xtal Osc

LNA + BPF

Image

Rej. Mxr.

XTALi

XTALo

GND GND

Note

2. BRCLK signal is available on bare die only, not packaged parts.

Document Number: 001-61351 Rev. *J

Page 2 of 40

CYRF8935

Contents

Pin Configuration .............................................................4

Pin Descriptions ...............................................................4

Functional Description .....................................................5

Power-on and Register Initialization Sequence ...........5

Enter Sleep and Wakeup ............................................6

Packet Data Structure .................................................6

FIFO Pointers ..............................................................6

Packet Payload Length ...............................................6

Framer: Packet Length Handling .................................7

MCU or Application Handles Packet Length ...............9

Typical Application .........................................................12

Setting the Radio Frequency .....................................13

Crystal Oscillator .......................................................13

Minimum Pin Count ...................................................14

Reset Pull-up .............................................................14

Transmit Power Control .............................................14

Reading RSSI ............................................................14

Automatic ACK ..........................................................15

Receive CRC and FEC Result ..................................15

Sync Word Selection .................................................15

Scramble On/Off Selection ........................................16

Measuring Receiver Sensitivity .................................16

Receive Spurious Responses ...................................17

RF VCO Calibration ...................................................17

Regulatory Compliance .................................................18

United States FCC ....................................................18

Register Settings for Test Purposes ..........................19

Recommendations for PCB Layout ..............................19

Antenna Type and Location ..........................................19

IR Reflow Standard .........................................................20

Register Definitions ........................................................21

Recommended Register Values ................................26

Absolute Maximum Ratings ..........................................28

Operating Range .............................................................28

Electrical Characteristics ...............................................28

SPI ....................................................................................31

SPI Transaction Formats and Timing ........................31

Specifications ............................................................32

Electrical Operating Characteristics .............................33

State Diagram .................................................................34

Ordering Information ......................................................35

Ordering Code Definitions .........................................35

Package Diagram ............................................................36

Acronyms ........................................................................37

Document Conventions .................................................37

Units of Measure .......................................................37

Document History Page .................................................38

Sales, Solutions, and Legal Information ......................40

Worldwide Sales and Design Support .......................40

Products ....................................................................40

PSoC® Solutions ......................................................40

Cypress Developer Community .................................40

Technical Support .....................................................40

Document Number: 001-61351 Rev. *J

Page 3 of 40

CYRF8935

Pin Configuration

Figure 1. 24-pin QFN pinout (Top View)

1

2

18

VDD1

VDD2

ANTb

ANT

RST_n

MISO

MOSI

CLK

17

16

3

25 GND

4

5

15

14

13

VDD3

Test2

PKT

6

SPI_SS

Pin Descriptions

Table 1. CYRF8935 24-pin QFN (4 × 4 mm) pinout

Pin Number

Pin Name

Type

--

Description

6, 7

1, 2, 5, 8, 9, 19, 22

3, 4

Test2, Test3

Reserved for factory test. Do not connect.

V_DD1to V_DD7

PWR

RF

Core power supply voltage. Connect all V_DDpins to V_OUTpin.

ANTb, ANT

Differential RF input/output. See Typical Application on page 12 for recom-

mended antenna hookup. Each of these pins must be DC grounded, 20 k or

less

10

12, 25

11

FIFO

GND

O

FIFO status indicator bit

GND

Ground connection

V_{DD_IO}

SPI_SS

PKT

PWR

V_DDfor the digital interface

13

I

O

I

Enable input for SPI, active low. Also used to bring device out of sleep state.

Transmit/receive packet status indicator bit

Clock input for SPI interface

14

15

CLK

16

MOSI

MISO

RST_n

I

Data input for the SPI bus

17

O/High-Z Data output (tristate when not active)

18

I

RST_n Low: Chip shutdown to conserve power. Register values lost

RST_n High: Turn on chip, registers restored to default value

20

21

V_IN

PWR

Unregulated input voltage to the on-chip low drop out (LDO) voltage regulator

V_OUT

+1.8 V output from on-chip LDO. Connect to all V_DDpins, do not connect to

external loads.

23

24

XTALo

XTALi

AO

AI

Output of the crystal oscillator gain block

Input to the crystal oscillator gain block

Document Number: 001-61351 Rev. *J

Page 4 of 40

CYRF8935

On-chip transmit and receive FIFO registers are available to

buffer the data transfer with MCU. Over-the-air data rate is

always 1 Mbps even when connected to a slow, low-cost MCU.

Built-in CRC, FEC, data whitening, and automatic

retry/acknowledge are all available to simplify and optimize

performance for individual applications.

Functional Description

The CYRF8935 RF transceiver can add wireless capability to a

wide variety of applications.

The product is a low-cost, fully-integrated CMOS RF transceiver,

GFSK data modem, and packet framer, optimized for use in the

2.4-GHz ISM band. It contains transmit, receive, RF synthesizer,

and digital modem functions, with few external components. The

transmitter supports digital power control. The receiver uses

extensive digital processing for excellent overall performance,

even in the presence of interference and transmitter

impairments.

Power-on and Register Initialization Sequence

For proper initialization at power up, V_INmust ramp up at the

minimum overall ramp rate no slower than shown by T_VINspeci-

fication in the following figure. During this time, the RST_n line

must track the V_INvoltage ramp-up profile to within approxi-

mately 0.2 V. Since most MCU GPIO pins automatically default

to a high-Z condition at power up, it only requires a pull-up

resistor, as shown in Figure 11 on page 14. When power is stable

and the MCU POR releases, and MCU begins to execute instruc-

tions, RST_n must then be pulsed low as shown in Figure 2,

followed by writing Reg[27] = 0x4200. During or after this SPI

transaction, the State Machine status can be read to confirm

FRAMER_ST= 1, indicating a proper initialization.

The product transmits GFSK data at approximately 0-dBm

output power. Sigma-Delta PLL delivers high-quality DC-coupled

transmit data path.

The low-IF receiver architecture produces good selectivity and

image rejection, with typical sensitivity of –87 dBm or better on

most channels. Sensitivity on channels that are integer multiples

of the crystal reference oscillator frequency (12 MHz) may show

approximately 5 dB degradation. Digital RSSI values are

available to monitor channel quality.

Figure 2. Power-on and Register Programming Sequence

T_VIN

V_IN

RST_n

Clock stable

SPI Activity

BRCLK

SPI_SS

Clock unstable

T_RPW

T_RSU

Write Reg[27]=

(not drawn to scale)

0x4200

T_CMIN

Table 2. Initialization Timing Requirements

Timing Parameter

Min

Max

Unit

Notes

20

ms

Reset setup time necessary to ensure

complete reset

2 < T

≤ 6.5 [ms/V]

VIN

T

–

RSU

T

1

3

–

10

–

µs

ms

Reset pulse width necessary to ensure complete reset

RPW

T

Minimum recommended crystal oscillator and APLL settling time

CMIN

T

6.5

ms/V

Maximum ramp time for V , measured from 0 to 100% of final voltage. For

IN

VIN

example, if V = 3.3 V, the max ramp time is 6.5 × 3.3 = 21.45 ms. If V =

IN

1.9 V, the max ramp time = 6.5 × 1.9 = 12.35 ms.

■ After RST_n transitions from 0 to 1, BRCLK^[3]begins running at 12-MHz clock.

■ After register initialization, CYRF8935 is ready to transmit or receive.

Note

3. BRCLK signal is available on bare die only, not packaged parts.

Document Number: 001-61351 Rev. *J

Page 5 of 40

CYRF8935

Figure 3. Initialization Flowchart

Initialize

Registers,

beginning with

Reg[27]

Initialize

CYRF8935 at

power-up

MCU generates

negative- going

RST_n pulse

Wait Crystal

Enable Time

Initialization

Done

RST_n pulls up

along with Vin

Enter Sleep and Wakeup

When the MCU or application writes to the CYRF8935 register 35[14] to enter sleep mode and deasserts SPI_SS, CYRF8935 enters

the sleep state where current consumption is extremely low.

Later, when SPI_SS is reasserted, CYRF8935 automatically wakes up from the sleep state. At this time the crystal oscillator is

reactivated. The crystal oscillator takes 1 to 3 ms to become fully stable. During wakeup, there is no requirement to clear register

35[14] and no requirement to hold SPI_SS asserted.

[4]

There are two sleep current choices available, selectable by Reg[27] setting: 1 µA and 8 µA. If you use the 1-µA setting, Vin must

be greater than or equal to 3.0 VDC. If Vin is ever expected to be < 3.0 VDC during Sleep, use the 8-µA setting. The 1-µA Sleep

setting should only be used for long-term sleep such as 8 to 10 seconds or more.

To achieve the lowest sleep current, a special sleep state firmware patch is required. The patch is as follows:

SLEEP PATCH: Before writing register 35 to enter sleep, write Reg[10]= 0x8FFD, wait 30 µs or more, then write Reg[10] back to the

default value of 0x7FFD. Next, write Reg[35] to enter sleep, as usual.

Packet Data Structure

Figure 4. Packet Structure

Preamble

Sync word(s) Trailer

<== P a y l o a d ==>

CRC

Each over-the-air CYRF8935 packet is structured as follows:

■ Preamble: 1 to 8 bytes, programmable

■ SYNC: 16/32/48/64 bits, programmable as device sync word

■ Trailer: 4 to 18 bits, programmable

The FIFO write pointer is automatically cleared when the

receiver receives SYNC.

The FIFO read pointer is automatically cleared when the receiver

receives SYNC, or after transmitting SYNC in transmit mode.

Packet Payload Length

■ Payload: TX/RX data

There are two ways to handle the TX/RX packet lengths in

CYRF8935. If register 41[13] is equal to 1, the CYRF8935

internal framer detects the packet length based on the value of

the first payload byte. If register 41[13] is equal to 0, the first byte

of the payload has no particular meaning, and packet length is

determined by either TX FIFO running empty or TX_EN bit

cleared (see Table 3).

■ CRC:16-bit CRC (Optional)

FIFO Pointers

The FIFO write pointer must be cleared before the application

writes data to FIFO for transmit. This is done by writing '1' to

register 52[15].

After receiving a packet, the write pointer at register 52[13:8]

indicates how many bytes of receive data are waiting in the FIFO

buffer to be read by the user MCU or the application.

Note

4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = 3 VDC, Ta = +25 °C.

IN

Document Number: 001-61351 Rev. *J

Page 6 of 40

CYRF8935

Table 3. CYRF8935 Configuration for Packet Length

Register 41[13]

PACK_LENGTH_EN

Register 41[12]

FW_TERM_TX

CYRF8935 Framer Start/Stop

0

1

Transmit stops only when Register 7 TX_EN = 0.

See FW_TERM_TX = 0 (Transmit) on page 10 for details.

Receive stops only when Register 7 RX_EN = 0.

(MCUorapplicationhandles

packet length)

See FW_TERM_TX= 0 (Receive) on page 11 for details.

Transmit automatically stops whenever FIFO runs empty.

Receive stops only when Register 7 RX_EN = 0.

See Receive Timing on page 8.

1

x

The first byte of payload is regarded as packet length, 0 to 255 bytes.

Transmit automatically stops when all 0 to 255 bytes are transmitted.

See Framer: Packet Length Handling on page 7 for details.

(CYRF8935 framer handles

packet length)

(do not care)

The following sections show the detailed timing diagrams. All timing diagrams show active high for PKT and FIFO flags. Active low is

also available through register 41[10] setting.

The MCU or application must load transmit data into the FIFO

register before the framer sends trailer bits. You can do this by

loading the transmit payload data into the FIFO register either

before or after writing TX_EN = 1. For slower applications, it is

easier to load the FIFO register, and then write TX_EN = 1. For

the higher frame rate (faster) applications, write register 7

TX_EN = 1, and then load the FIFO register with payload data

during the Tx on delay time, as shown in Figure 5.

Framer: Packet Length Handling

The CYRF8935 framer handles packet length by setting register

41[13] = 1. The first byte of the payload is regarded as packet

length (this length byte is not counted in the packet length). The

CYRF8935 supports packet lengths up to 255 bytes. The framer

handles Tx/Rx start and stop.

Transmit Timing

If the packet length exceeds the FIFO length, the MCU must

write FIFO data multiple times. The FIFO flag indicates whether

FIFO is empty in transmit state.

The Tx timing diagram is shown in Figure 5. After MCU writes

register 7[8]= TX_EN = 1, the framer automatically generates the

Tx packet using payload data from the FIFO register. The

frequency (RF channel) will be as specified in register 7 at the

time TX_EN is written to 1.

Figure 5. Tx Timing Diagram when Register 41[13] = 1 (Framer Handles Packet Length)

PKT and FIFO Flags are Active High

Write Reg. 7

SPI_SS

Internal

Tx On

2 µs

Tx On Delay

PA Ramp Up

Transmit Data

Tx Packet

PKT

PKT = 1 after Tx packet has been sent.

FIFO

MCU fills FIFO before framer sends trailer bits.

FIFO = 1 when FIFO is empty

Document Number: 001-61351 Rev. *J

Page 7 of 40

CYRF8935

Receive Timing

If a valid syncword is found, the CYRF8935 framer processes the

packet automatically. When the received packet processing is

complete, the CYRF8935 framer sets the state to IDLE.

Figure 6 shows the Rx timing diagram. The receive process

begins when the MCU writes register 7[7] = 1. At this time, the

CYRF8935 framer turns on the receiver and waits while

attempting to detect a valid syncword. The receive frequency is

specified within register 7. The two register 7 fields of interest,

RX_EN and RF_PLL_CH_NO, may be sent to CYRF8935 during

the same SPI transaction. If sent in separate SPI transactions,

send the RF_PLL_CH_NO first, followed by RX_EN.

If the received packet length is longer than 63 bytes, the FIFO

flag goes active, which means the MCU must read out data from

the FIFO.

A valid syncword might not always be found, either due to a weak

signal, multi-path cancellation, or devices being out of range. To

accommodate such a condition and to prevent lockup, the

application or the MCU must incorporate a 'receive timeout' timer

to clear RX_EN and return to the IDLE state.

Figure 6. Rx Timing Diagram when Register 41[13] = 1 (Framer Handles Packet Length)

PKT and FIFO Flags are Active High

Write Reg. 7

SPI_SS

Internal Rx_on

2 µs

Receive On Delay

Received Data

Rx Packet

PKT = 1 when Rx packet has been

received by Framer.

PKT

FIFO

FIFO = 1 when FIFO is full.

Document Number: 001-61351 Rev. *J

Page 8 of 40

CYRF8935

MCU or Application Handles Packet Length

When register 41[13] = 0, the first byte of the payload data has no special significance and the packet length depends on register

41[12].

FW_TERM_TX = 1

If register 41[12] = 1, the CYRF8935 framer continues to compare the FIFO write point and the FIFO read point during packet

transmission. If the MCU or application stops writing data to FIFO, the framer eventually detects that there is no data to send (FIFO

is empty), and CYRF8935 exits ‘cease transmission’ automatically (see Figure 7).

Figure 7. Tx Timing When Register 41[13:12] = '01b PKT and FIFO Flags are Set as Active High

Write Reg. 7

TX_ EN =1

SPI_SS

Internal

Tx on

2µs

Tx On Delay

Framer will terminate Tx when FIFO

write point equals FIFO read po.int

PA On Delay

Internal

Packet Tx

Tx Data

PKT

FIFO

FIFO= 1 when

FIFO is empty.

MCU fills FIFO before framer sends trailer b. its

Note When register 41[13] = 0 (MCU or application handles packet length), never let FIFO underflow or overflow. FIFO full and empty

thresholds can be controlled using register 40 FIFO_EMPTY_THRESHOLD and FIFO_FULL_THRESHOLD settings. The best value

depends on SPI speed and the speed at which the MCU or application can stream the data into FIFO.

Document Number: 001-61351 Rev. *J

Page 9 of 40

CYRF8935

FW_TERM_TX = 0 (Transmit)

When register 41[13:12] = '00b, the CYRF8935 framer does not stop packet transmission until MCU or application writes register 7[8]

TX_EN bit = 0. Packet transmission continues even if FIFO is empty (see Figure 8).

Figure 8. TX Timing Diagram when Register 41[13:12] = '00b PKT and FIFO Flags are Shown Active High

Write Reg. 7

TX_ EN = 1

Write Reg. 7

TX_ EN =0

SPI_SS

2µs

Internal Tx

2µs

Transmit Delay

Framer terminates Tx when MCU or

application writes Reg. 7 TX_ EN =0.

PA On Delay

Internal Tx Data

Packet TX

PKT

FIFO

FIFO= 1

when FIFO is empt.y

MCU fills FIFO before framer sends trailer b. its

Note When register 41[13] = 0 (MCU or application handles packet length), never let FIFO underflow or overflow. FIFO full and empty

thresholds can be controlled through register 40 FIFO_EMPTY_THRESHOLD and FIFO_FULL_THRESHOLD settings. The best

value depends on SPI speed and the speed at which the MCU or application can stream the data into FIFO.

Document Number: 001-61351 Rev. *J

Page 10 of 40

CYRF8935

FW_TERM_TX= 0 (Receive)

PKT flag remains active until the MCU or application reads out

the first byte of data from the FIFO register. After the MCU or

application reads the first byte of receive data, the PKT flag goes

inactive until the next Tx/Rx period.

When register 41[13] = 0, packet reception starts when MCU or

application writes register 7[7] RX_EN = 1. At this time, the

framer automatically turns on the receiver to the frequency and

channel specified in register 7. After waiting for the internal

synthesizer and receiver delays, the framer circuitry of the

CYRF8935 begins searching the incoming signal for a syncword.

When the syncword is detected, the framer sets the PKT flag

active, and then starts to fill the FIFO with receive data bytes. The

With register 41[13:12] = '00b or '01b, the CYRF8935 framer

always needs the MCU or application to write register 7[7] to 0

to stop the Rx state.

The Rx timing diagram is shown in Figure 9.

Figure 9. RX Timing Diagram when Register 41[13:12] = '00b or '01b

PKT_flag and FIFO_flag are Active High

Write

Reg. 7

SPI_SS

Internal Rx On

2 µs

Internal Rx On Delay

Packet Rx Data

Internal Rx Data

PKT

PKT = 1 when syncword received.

PKT = 0 when MCU/application reads first byte from FIFO register.

FIFO

FIFO = 1 when FIFO is full.

Document Number: 001-61351 Rev. *J

Page 11 of 40

CYRF8935

Typical Application

FIFO_flag

+1.8V

C4

+3.3V

0.10uF

U1

13

14

15

16

17

18

6

5

4

3

2

1

SPI_ss

SPI_SS

PKT

Test2

VDD3

ANT

R4

50 Ohm

PKT_flag

SPI_CLK

SPI_mosi

SPI_miso

RST_n

20k

Antenna conn.

C3

Note 1

1.0pF

L1

1

J1

SMA

CLK

25

GND

2.2nH

R1

51

MOSI

MISO

RST_n

ANTb

VDD2

VDD1

C1

0.10uF

+1.8V

R5

10k

+3.3V

CYRF8935

+3.3V

Note 2

C5

0.10uF

Notes:

+1.8V

1. ANT pin requires DC path to ground. If

antenna or RF test equipment does not provide

this, R4= 20k Ohm is required.

R2

C6

4.7uF

2. Max. input noise on Vin: 50 mV pk.

680k

Ceramic

ESR < 4 Ohms

R3

2.2k

C7

C8

15pF

Y1

15pF

Quartz xtal 12MHz

Document Number: 001-61351 Rev. *J

Page 12 of 40

CYRF8935

Some sample Register 7 examples are as shown in Table 4.

Setting the Radio Frequency

During Regulatory Compliance testing, you can jump directly to

another frequency any time without going through IDLE state. If

you change between Tx and Rx, however, you must pass

through IDLE state. For IDLE state, write Register 7 to clear bits

8 and 7. Tx or Rx operation is initiated when Register 7 bit 8 or

7 is set. Radio frequency is also determined at that time.

Programming by channel number is the easiest way to set

frequency. In the CYRF8935, RF carrier frequency and RF

channel number are always related by the expression:

Freq. = 2402 + Ch. #

Channel number is loaded into bits [6:0] of Register 7. Bits 7 and

8 initiate the desired Rx or Tx operation, respectively.

Table 4. Sample Register 7 Settings

DUT Channel

Number

(hex)

Tx setting:

Reg. 7 value

for TX_EN= 1

Rx setting:

Reg. 7 value

for RX_EN= 1

Carrier Frequency,

MHz

DUT Channel Number

(decimal)

2402

2403

2404

|

0

1

00

01

02

|

0100

0101

0102

|

0080

0081

0082

|

2

|

2434

|

32

|

20

|

0120

|

00A0

|

2441

|

39

|

27

|

0127

|

00A7

|

2480

78

4E

014E

00CE

Table 5. Crystal Specifications

Crystal Parameter

Crystal Oscillator

The CYRF8935 contains the on-chip gain block for the quartz

crystal frequency standard.

Specification

Frequency

12.000 MHz

±15 ppm

Quartz Crystal Application

Initial frequency tolerance

As shown in Figure 10 on page 14, the series resistor Rs limits

power to the crystal and contributes to the phase-shift necessary

for oscillation. The ideal Rs value may need to be determined

empirically, adjusted for certain crystal manufacturer part

numbers and designs. The series equivalent combinations of C1

and C2 largely determine the capacitive load seen by the crystal,

which should match the crystal vendor's specification. These

capacitor values are chosen to center the crystal oscillator

frequency at the correct value, 12 MHz. The feedback resistor Rf

from the buffer output to input serves to self-bias the on-chip

buffer to the center of the linear region for maximum gain.

Frequency tolerance over

temperature

±15 ppm

±5 ppm

±40 ppm

Frequency tolerance after

aging

Frequency drift due to load

cap. drift

Total

Equivalent series resistance 80  max

Resonance mode

Load capacitance

Fundamental, parallel resonant

Verifying correct crystal oscillator frequency may require special

test methods. Because connecting a frequency counter probe to

either XTALi or XTALo adds capacitive loading and alters the

crystal oscillation frequency, other methods must be used. For

bare die applications involving COB packaging, use the

Inaccordancewithexternalload

capacitors (see C1 and C2 in

Figure 10)

Note For proper operation, the total frequency error must not

exceed what is shown in Table 5. Individual error contributions

can be adjusted; for example 10+20+5+5=40, or 5+30+2+3=40.

[5]

BRCLK test point to verify correct frequency of oscillation. This

requires register 32[3:1] set accordingly (see Register Defini-

tions on page 21). For 24-QFN packaged parts, the correct

crystal frequency is determined by transmitting a continuous

carrier frequency (see Register Settings for Test Purposes on

page 19) and using a RF frequency counter to ensure correct

frequency. Irrespective of which method is used, initial tolerance

should be within budget as recommended in Table 5, such that

the total frequency error stays within budget.

Note

5. BRCLK signal is available on bare die only, not packaged parts.

Document Number: 001-61351 Rev. *J

Page 13 of 40

CYRF8935

Figure 10. Simplified Schematic of Crystal Oscillator

Figure 11. Reset Pull-up Circuit

CRYSTAL

C2

C1

Vin

Rs

Rf

U1

R5

10k

13

6

SPI_SS

Test2

Clock

Logic

14

5

PKT

VDD3

Xtal. Osc.

Gain Block

15

4

CLK

ANT

CYRF8935

25

GND

16

17

18

3

MOSI

MISO

RST_n

ANTb

Connect to

2

VDD2

Frequency Counter

to verify correct

crystal osc. frequency.

BRCLK

(bare die only)

1

RST_n

VDD1

Note When crystal oscillator is constructed as shown in Typical

Application on page 12, Table 5 on page 13, and Figure 10, the

oscillation frequency should be stable within 3 mS (max) after

startup.

CYRF8935

Vin

Minimum Pin Count

Transmit Power Control

When a low-cost MCU drives the CYRF8935, the MCU pin count

must be minimized.

Table 6 lists recommended settings for register 9 for short-range

applications, where reduced transmit RF power is a desirable

trade off for lower current.:

■ FIFO pin: Only needed when the Tx or Rx packet length is

greater than around 63 bytes, up to infinity. For short packets

(< 63 bytes), FIFO is not needed.

Table 6. Transmit Power Control

Typical

Transmit

Power

Value of Register 9

■ PKT pin: Gives a hardware indication of a packet received. If

you are willing to poll register 48 for this information, then this

pin is not needed.

Power Setting

Description

Silicon ID

0x1002 ^[6]

Silicon ID

0x2002 ^[6]

(dBm)

■ SPI lines: All four lines are needed.

PA0 - Highest power

PA2 - High power

PA4 - High power

PA8 - Low power

PA12 - Lower power

+1

0

0x1820

0x1920

0x1A20

0x1C20

0x1E20

0x7820

0x7920

0x7A20

0x7C20

0x7E20

Reset Pull-up

–3

For proper power-up initialization, the RST_n pin must have a

pull-up to VIN, as shown in Figure 11. The exact value of the 10-k

pull-up resistor is not critical. The pull-up resistor ensures proper

operation of the CYRF8935 internal-level shifter circuitry while

power is applied. Subsequently, the RST_npulse resets the

internal registers to their default state.

–7.5

–11.2

Reading RSSI

The CYRF8935 contains internal RSSI circuitry that is roughly

linearized to 1 dB for every LSB. Results are read from register

6[15:10], RAW_RSSI. See Register Definitions on page 21 for

details.

The framer must read the RSSI register after the receiver is

enabled and set on frequency using register 7, and after the RF

PLL has settled according to the correct receive frequency.

Note

6. Silicon Id can be read from Register 31.

Document Number: 001-61351 Rev. *J

Page 14 of 40

CYRF8935

The wait time between programming RX_EN, and reading

Register 6, can be determined by any of the following methods,

or any desired combination, depending on the application:

Receive CRC and FEC Result

The CYRF8935 returns CRC and FEC error check status in

register 48[15:14]. For convenience, the entire top byte of

register 48 is returned in the SPI status word. These eight bits

are normally available from the SPI hardware block of the MCU

or application, saving the time necessary to do an additional read

of register 48 for the same information.

■ Wait in accordance with RF PLL Settling Time spec. to be sure

RF PLL is settled.

■ Read register 3[12] RF_SYNTH_LOCK to be sure CYRF8935

RF PLL is settled.

CRC is calculated only on the payload portion of the packet.

■ Read register 48[7] SYNCWORD_RECV to indicate the signal

being received is a desired packet.

CRC_ERROR only clears after another valid syncword is

detected by the receiver or after transmission of a packet

payload.

Note that RSSI can be read without receiving a syncword. In

other words, CYRF8935 RSSI circuitry also responds to CW and

interference signals.

Sync Word Selection

If the RSSI feature is not needed, disable it to conserve receiver

DC current budget. When register 11[9] is changed from 0 to 1,

the receiver current consumption decreases by about 0.3 mA.

At the beginning of each packet, after transmission of a

01010101 preamble, is a sync word, programmable to be 16, 32,

48, or 64 bits long. For the devices to communicate, these must

be programmed to the same value at both ends of the link. The

sync word can be thought of as a MAC address in this respect.

Figure 12. Typical Room Temperature RSSI Response

In the CYRF8935 receiver, there is an adjustable tolerance for

sync word bit errors that may occur. This adjustment is called

SYNCWORD_THRESHOLD, set via Register 40, bits 5:0. If set

too tight, performance is good but less-than-optimum receive

sensitivity and link budget is obtained. If set too loose, Frame

Errors increase because of false synchronization.

The situation can sometimes be further complicated if the

chosen sync word, combined with the 01010101 preamble, has

unusually high auto correlation, or correlation with other devices

that may be on the air on a different sync word network. This

undesired condition is likely to happen when the sync word bits

that immediately follow the 01010101 preamble continues the

1010... sequence. In such cases, it becomes difficult for the

receiver to separate the actual sync word from the preamble. The

solution is to either tighten the SYNCWORD_THRESHOLD, or

choose a better sync word. Sometimes increasing the sync word

length is also an option.

Register 36 sets the sync word for the bits that immediately follow

the preamble. If a false sync problem is observed, try changing

this word first.

The following table summarizes some recommended settings.

Following is the pseudocode for measuring RSSI:

Table 7. RecommendedSYNCWORD_THRESHOLDSettings

Recommended

Write Reg11 = 0x0208

;disable RSSI before reading

Read RSSI = Reg6[15:10] ;do the read

Sync Word

Application Length (see

Register 32)

Reg. 40

Sync Word

Selection

Write Reg11 = 0x0008 ;enable RSSI for next measurement

SYNCWORD_THR

ESHOLD setting

(decimal)

Automatic ACK

Simple

32

64

Better

1

The CYRF8935 provides an automatic retry/acknowledge

feature. This means that if the TX packet does not successfully

arrive at the receiving end, the TX end automatically attempts a

given number of retries. In a weak signal environment, this

feature makes the bit error rate (BER) appear to be zero at the

expense of the frame error rate (FER). Refer to State Diagram

on page 34 for details.

(almost every sync

word must work)

Good

(Most sync words

work)

2

6 or tighter

7

Advanced

Better

(almost every sync

word must work)

To use automatic retry/acknowledge, see Register Definitions on

page 21 for register 41[11] and register 35[11:8].

Good

(Most sync words

work)

Document Number: 001-61351 Rev. *J

Page 15 of 40

CYRF8935

Scramble On/Off Selection

Measuring Receiver Sensitivity

The CYRF8935 incorporates a built-in hardware data scrambling

and descrambling function. This function is designed to make the

transmit data more random, removing long strings of continuous

mark or space. When enabled, it causes payload data to be

modified by a PN code that is initialized according to the setting

of Register 35 SCRAMBLE_DATA.

Receive sensitivity and BER can be measured using these

methods:

Method 1: Link Budget Method

In this method, another CYRF8935 or a compatible transceiver

is used as a transmit packet source. It connects to the device

under test (DUT) through a calibrated attenuation path. The

transmit power should also be known or measured. The receiver

sensitivity can be calculated from the following equation, based

on the largest RF attenuation that can be sustained between Tx

and Rx, while maintaining adequate link performance.

Systems based on CYRF8935 will normally function either way,

scramble on or off.

Setting SCRAMBLE_ON=1 will indeed cause a small 'token'

increase in over-the-air security, similar to what WEP adds to

WiFi. In other words, it renders the OTA data coded, but it should

not be considered highly secure. For truly secure applications,

consider using scramble combined with other security

algorithms.

Link_Budget = (TxP – RxSens) [dB]

Where

TxP = Transmit Power [dBm]

RxSens = Receive Sensitivity [dBm]

To function properly, both ends of the RF link need the same

setting, enabled or disabled. Both ends must also have the same

Register 35 SCRAMBLE_DATA setting.

Figure 13. Measuring Overall Link Budget, Method 1

CYRF

8935

DUT

CYRF

MCU

8935

MCU

Variable atten.

Trilithic BMA-35110

or equiv.

Packet RX

Packet TX

When using this method, make sure that the RF signal is not

leaking around the attenuator or coupling directly into the

receiver, which renders the attenuation setting meaningless. You

can verify this by simply increasing the attenuation and verifying

that the packets cease to be received at higher attenuator

settings.

Test Variations

■ Automatic loopback can be added to test both Tx and Rx in the

same test.

■ Frequency hopping can be added to test over the design

frequency range.

RF leakage around the attenuator can be caused by:

■ Loose RF cable connector

Method 2: Packet Signal Generator method

In this method, an RF signal generator is used as the packet

source. The shielded, adjustable RF output of the signal

generator connects to the receiver input. The signal generator

must have digital pattern storage ability for the modulation. A

packet of valid data is downloaded into the signal generator, and

these packets are repetitively sent to the CYRF8935 receiver

under test. An MCU or PC program monitors the CYRF8935 PKT

flag signal, which causes the MCU or PC to download each

packet as it is received, compare the packet against the

expected values, and report the packet statistics to the end user.

■ Poorly shielded RF cables

■ Poor PCB layout at either Tx or Rx

■ RF boards too close together

■ Coupling by or over the DC power leads

Note that interference from other 2.4-GHz services could be

leaking into the test setup and degrade the BER measurement.

When properly set up and working, the link budget method is a

simple and reliable way to test and characterize CYRF8935 RF

performance.

Document Number: 001-61351 Rev. *J

Page 16 of 40

CYRF8935

Figure 14. Measuring Receiver Sensitivity with Signal Generator, Method 2

CYRF

RS-232

Term.

MCU

RF Signal Generator

PC

Programmer

8935

DUT

bd.

With Pattern Gen.

Packet Transmitter

Packet Receiver

Packet data pattern downloaded

into signal generator

In this setup, the signal generator is set as follows:

RF VCO Calibration

Modulation: GFSK, 2-level, Bt = 0.5, peak deviation 320 kHz,

symbol rate 1 Msps.

Over-the-air Transmit and Receive frequencies for the

CYRF6935 RF transceiver are derived from the 12 MHz crystal

oscillator, multiplied up by the internal fractional-N RF PLL. Low

Frequency, amplitude: As required for test.

phase noise is obtained by keeping the PLL K

relatively low.

VCO

In order for the VCO to cover the desired frequency range over

Receive Spurious Responses

the expected V , temperature, and process extremes, the VCO

DD

This receiver, like many other low-cost receivers, may exhibit

spurious responses in-band, often at multiples of certain digital

frequencies. In the case of the CYRF8935, this response

sometimes occurs at multiples of 4 MHz or four channels, offset

from the desired receiver passband. During frequency hopping,

a signal may be found on the wrong frequency, causing incorrect

hopping synchronization.

must be calibrated prior to use. The CYRF8935 contains a fully

automatic calibration algorithm, but the algorithm does require

approximately 150 us extra time, compared to automatic

calibration turned off.

The workaround for this is to program one of the payload bytes

to contain the channel number on which the packet is being

transmitted. When a packet is received, this byte is checked to

determine if it matches the receive channel setting. If not, the

packet should be discarded.

Document Number: 001-61351 Rev. *J

Page 17 of 40

CYRF8935

Regulatory Compliance

United States FCC

When operating in the 2402- to 2480-MHz band, the second and third harmonics always fall into what is defined in 47CFR, section

15.205 as ‘restricted bands of operation’. The field strength of radiated emissions greater than 1 GHz in a restricted band must not

exceed 500 µV/m at a distance of 3 meters. Using the equation for free space propagation, you can translate the field strength to an

equivalent RF power level at the DUT, if an assumption is made regarding the effective antenna gain at the second and third harmonic

frequencies.

Figure 15. Calculation of Maximum Spurious Level

Unit of

Parameter

Field Strength

Measure

54.0 dBµV/m

or

501 µV/m

0.501 mV/m

Tx antenna gain over isotropic

Impedance of free space

distance

6 dBi

377 ohms

0.003 km

or

3.981071706 power ratio

120*pi ohms

3 m

Result

Tx pwr, desired signal

Tx pwr, undesired spurious

or

0 dBm

-47.2 dBm

-47.2 dBc

or

0.001 W

1.89287E-08 W

The antenna gain assumption of +6 dBi is based on the fact that the measurement requires that the position of the DUT and

measurement antennae be maximized to yield the highest spurious signal. Since the second and third harmonics, by definition, fall

on integer multiples of the carrier wavelength, many common DUT antennae may have good, usable gain at higher frequencies such

as 0 dBi. Accounting for the maximization of the measurement, +6 dBi is a good, conservative antenna gain for harmonic frequencies.

In practice, harmonic emissions are much less of a problem, primarily because the antenna is not specifically optimized for such

harmonics.

The calculation in Figure 15 shows the maximum spurious level at the antenna as –47 dBm. Because the typical second harmonic is

specified as –45 dBm, it follows that an additional 2 dB attenuation could be required. However, no additional attenuation is required

to pass the FCC-radiated emissions test. Individual test results may vary.

Table 8 lists a summary of FCC precompliance test results. The antenna used is a common half-wave end-fed dipole. The results

easily pass the U.S. FCC test for a Part 15.247 device. If there is a problem with qualification because of spurious emissions in

restricted bands, you can add a filter, or perhaps reduce Tx Power through Register 9.

Table 8. FCC Test Results

Run

No.

Power

Setting

Measured

Power

Mode

Channel

Test Performed

Limit

Result/Margin

1a

Non hopping

2402 MHz

Default

NA

Restricted band edge

(2390 MHz)

FCC Part 15.209 /

15.247(c)

46.8 dbV/m at

2390.0 MHz (–7.2 dB)

Radiated emissions

(1–0 GHz)

FCC Part 15.209 /

15.247(c)

45.7 dbV/m at

4804.1 MHz (–8.3 dB)

1b

1c

Non hopping

2441 MHz

2480 MHz

Radiated emissions

(1–18 GHz)

FCC Part 15.209 /

15.247(c)

45.0 dbV/m at

4882.2 MHz (–9.0 dB)

Restricted band edge

(2483.5 MHz)

FCC Part 15.209 /

15.247(c)

47.8 dbV/m at

2484.1 MHz (–6.2 dB)

Radiated emissions

(1–10 GHz)

FCC Part 15.209 /

15.247(c)

45.3 dbmV/m at

4960.1 MHz (–8.7 dB)

Document Number: 001-61351 Rev. *J

Page 18 of 40

CYRF8935

Register Settings for Test Purposes

To pass various regulatory agency EMC tests, the DUT may need to enter various test states as shown below. After loading the

recommended register values shown in Table 12 on page 26, load the registers in the order shown in the following table.

Table 9. Register Settings for Test Purposes

Test State

Tx continuously,

CW mode

Notes

Register Settings

Reg. 11= 0x8008

(CW_MODE= 1)

Primarily used to verify proper crystal oscillator

frequency.

The Tx turns on and stays on continuously. There will Reg. 41= 0xC000

be no on/off bursting of the carrier. Modulation will be (SCRAMBLE_ON= 1,

absent. Carrier frequency will be half-way between

mark and space.

PACK_LENGTH_EN= 0, and

FW_TERM_TX= 0)

Occasionally used during EMC testing.

Reg. 7 as shown in Table 4 on page 13.

Tx continuously,

Random data mode

During EMC testing, this is the most commonly used Reg. 11= 0x0008

Tx test. (CW_MODE= 0)

Modulation will be normal, GFSK. Tx data will continu- Reg. 41= 0xC000

ously cycle through the FIFO data bits. A data scram- (SCRAMBLE_ON= 1,

bling function will be applied. In other words, even if the PACK_LENGTH_EN= 0, and

FIFO has all zeros (not yet loaded with data), Tx data FW_TERM_TX= 0)

will appear random. Radiated emissions resemble

normal operation except that the carrier is on continu-

ously, which significantly speeds up testing.

Reg. 7 as shown in Table 4 on page 13.

Rx continuously

Sometimes required for EMC testing.

When neither Tx nor Rx is desired.

Reg. 41= 0xC000

(PACK_LENGTH_EN= 0, and

FW_TERM_TX= 0)

Reg. 7 as shown in Table 4 on page 13.

Tx and Rx off

(IDLE state)

Reg. 7:

clear bits 8 and 7.

Reg. 7 binary:

xxxx xxx0 0xxx xxxx

(x = don’t care)

Recommendations for PCB Layout

Antenna Type and Location

Though the PCB layout is not too critical, here are some

recommendations:

The most significant factor affecting RF performance for the

CYRF8935 or any other over-the-air RF device is the antenna

type, placement, and orientation. Antenna gain is normally

measured with respect to isotropic, that is, an ideal radiator that

sends or receives power equally to or from any direction. An ideal

antenna choice for most low-power, short-range wireless

applications is the theoretical isotropic reference antenna.

Unfortunately, these do not exist in practice. A simple dipole with

a theoretical gain of +2 dBi is usually a good choice. However,

you should take care when placing the antenna, because dipole

antennas have a radiation pattern where the null can be very

deep.

■ RF path: Adhere closely to the recommended reference design

circuit.

■ Clock traces: Keep the quartz crystal traces simple and direct.

The self-bias resistor should be close to the XTALi and XTALo

pins. The oscillation loop, consisting of the series resistor and

crystal, should be a simple, small loop. The crystal-loading

capacitors should be near the crystal. The ground connection

to these capacitors must be good, clean, and quiet. This

prevents noise from being injected into the oscillator. It is best

to have one ground plane for the entire RF section.

The antenna must be kept away from human tissue, particularly

sensitive spots like the heart, brain, and eyes. Violating this

design principle makes the end product perform poorly and can

be dangerous for the user. Refer to www.fcc.gov/oet/rfsafety for

guidance on this subject. For best operation, design the product

so that the main antenna radiation is away from the body, or at

least not proximity-loaded by the human body or dielectric

objects within the product.

■ Power distribution and decoupling: Capacitors should be

located near the V pins, as shown in Typical Application on

DD

page 12.

■ Antenna placement: When using an antenna, follow the

manufacturer's recommendation regarding layout.

■ Digital interface: To provide a good ground return for the digital

lines, it is a good idea to provide at least two pins for ground

on the digital interface connector. Good grounding between RF

and MCU can help reduce noise 'seen' at the antenna, thus

improving performance.

Remember to keep the antenna away from clock lines and digital

bus signals; otherwise, harmonics of the clock frequency will jam

certain receive frequencies.

Document Number: 001-61351 Rev. *J

Page 19 of 40

CYRF8935

IR Reflow Standard

■ Reference: IPC/JEDEC J-STD-020D.1

Figure 16. Recommended IR Reflow Profile

Temp: °C

30 seconds

(See Jedec J-STD-020 latest rev.)

Tp = 250 +0, -5

Ramp-down

Ramp-up

6 °C per sec. (max)

3 °C per second (max)

Liquidous temp.

TL= 217

60 to 150

seconds

Tsmax = 200

Tsmin = 150

60 to 120

seconds

T= 25

Time

8 minutes max.

Document Number: 001-61351 Rev. *J

Page 20 of 40

CYRF8935

Register Definitions

The following registers are accessed using the SPI protocol.

Some of the internal registers and bit fields are not intended for end-user adjustment. Such registers are not described here and

should not be altered from the factory-recommended value

Table 10. RF Register Information

Bit No.

Bit Name

Register 3 – Read only

Description

15:13

12

(Reserved)

RF_SYNTH_LOCK

Indicates the phase lock status of RF synthesizer.

1: Locked

0: Unlocked

11:0

(Reserved)

Register 6 – Read only

15:10

RAW_RSSI[5:0]

Indicates 6-bit raw RSSI value from analog circuit.

Each LSB is approximately 1 dB. See Reading

RSSI on page 14 for details.

9:0

(Reserved)

Register 7

15:9

8

(Reserved)

TX_EN

(Reserved)

Initiates the transmit sequence for state machine

control.

Note that TX_EN and RX_EN cannot be set to ‘1’

at the same time.

7

RX_EN

Initiates the receive sequence for state machine

control.

Note that TX_EN and RX_EN cannot be set to ‘1’

at the same time.

6:0

RF_PLL_CH_NO [6:0]

Sets Tx and Rx RF channel number, for example:

Write 0 for channel 0 (2402 MHz)

Write 39 for channel 39 (2441 MHz)

Write 78 for channel 78 (2480 MHz)

Register 9

15:11

10:7

6:0

(Reserved)

PA_GN[3:0]

(Reserved)

PA power level control

(Reserved)

Register 10

15:1

0

(Reserved)

XTAL_OSC_EN

1: Enable crystal oscillator gain block

0: Disable crystal oscillator gain block

15:1

15

(Reserved)

CW_MODE

(Reserved)

Register 11

1: Disables Tx modulation; CW only.

0: Normal Tx mode

14:10

9

(Reserved)

RSSI_DIS

(Reserved)

1: Disable RSSI

0: RSSI operates normally.

8:0

(Reserved)

Document Number: 001-61351 Rev. *J

Page 21 of 40

CYRF8935

Table 10. RF Register Information (continued)

Bit No.

Bit Name

Description

Register 23

15:3

2

(Reserved)

TXRX_VCO_CAL_EN

1: enable automatic VCO calibration with every

Tx/Rx.

0: disable feature

1:0

(Reserved)

Register 27

15:11

LDO_SP_SLEEP

Sets LDO sleep current. See Electrical

Characteristics on page 28 for Register 27

settings.

10:0

(Reserved)

Register 29 - Read only - 0x00xx

15:8

7:4

(Reserved)

RF_VER_ID [3:0]

This field is used to identify minor RF revisions to

the design.

3

(Reserved)

2:0

Digital version

This field is used to identify minor digital revisions

to the design.

Register 30 - Read only - 0xf413

15:0

(Reserved)

Silicon ID

(Reserved)

Register 31 - Read only

This field is used to identify Silicon ID. Valid values

are 0x1002 and 0x2002

Document Number: 001-61351 Rev. *J

Page 22 of 40

CYRF8935

Table 11. Framer Register Information

Bit No.

Bit Name

R/W

Description

Default

Register 32

000b: 1 byte

15:13

PREAMBLE_LEN

R/W

010b

001b: 2 bytes

010b: 3 bytes

.

111b: 8 bytes

12:11

10:8

SYNCWORD_LEN

TRAILER_LEN

R/W

11b: 64 bits

11b

{{Reg39[15:0],Reg38[15:0],Reg37[15:0],Reg36[15:0]}

10b: 48 bits, {Reg39[15:0],Reg38[15:0],Reg36[15:0]}

01b: 32 bits, {Reg39[15:0],Reg36[15:0]

00b: 16 bits,{Reg36[15:0]}

000b: 4 bits

001b: 6 bits

010b: 8 bits

011b: 10 bits

.

000b

.

111b: 18 bits

7:6

5:4

DATA_PACKET_TYPE

FEC_TYPE

R/W

00b: Non return to zero (NRZ) law data

00b

00b: No FEC

01b: Reserved

10b: FEC23

11b: Reserved

[7]

3:1

BRCLK_SEL

R/W

Selects output clock signal to BRCLK pin:

011b

000b: Keep low

001b: Crystal buffer out

010b: Crystal divided by 2

011b: Crystal divided by 4

100b: Crystal divided by 12

101b: TXCLK 1 MHz

110b: APLL_CLK (12 MHz during Tx, Rx)

111b: Keep low

0

(Reserved)

W/R

W

(Reserved)

Register 35

(Reserved)

0B

15

14

(Reserved)

SLEEP_MODE

1: Enter SLEEP state (set crystal gain block to off. Keep LDO 0B

regulator on (register values will be preserved).

Wakeup begins when SPI_SS goes low. This restarts the on-chip

clock oscillator to begin normal operation.

0: Normal (IDLE) state

13

12

(Reserved)

BRCLK_ON_SLEEP

R/W

1: Crystal running at sleep mode

Draws more current but enables fast wakeup

0: Crystal stops during sleep mode

1B

Saves current but takes longer to wake up

Note

7. BRCLK signal is available on bare die only, not packaged parts.

Document Number: 001-61351 Rev. *J

Page 23 of 40

CYRF8935

Table 11. Framer Register Information (continued)

Bit No.

11:8

Bit Name

RE-TRANSMIT_TIMES

MISO_TRI_OPT

R/W

Description

Default

Max retransmit packet attempts when AUTO_ACK= 1.

3H

7

R/W

1: MISO drives low-Z even when SPI_SS = 1 (Only one SPI slave 0B

device on the SPI)

0: MISO goes tristate when SPI_SS = 1 (Allows multiple SPI

slave devices on the SPI)

6:0

SCRAMBLE_DATA

R/W

Whitening seed for data scramble. Must be set the same at both 00H

ends of radio link (Tx and Rx). Must be nonzero.

Register 36

15:0

15:11

SYNC_WORD[15:0]

SYNC_WORD[31:16]

SYNC_WORD[47:32]

SYNC_WORD[63:48]

R/W

Least significant bits of sync word are sent first

Register 37

0000H

Least significant bits of sync word are sent first

Register 38

0000H

Least significant bits of sync word are sent first

Register 39

Least significant bits of sync word are sent first

Register 40

FIFO_EMPTY_THRESHOLD R/W

FIFO_FULL_THRESHOLD R/W

SYNCWORD_THRESHOLD R/W

During Tx, this field adjusts the point at which the FIFO flag signal 00100B

notifies the MCU or application to indicate that the FIFO register

is almost empty.

The best value depends on the individual application and the

speed at which the MCU or application can access the FIFO.

10:6

5:0

During Rx, this field adjuststhe point at which the FIFOflag signal 00100B

notifies the MCU or application to indicate that the FIFO register

is almost full.

The best value depends on the individual application and the

speed at which the MCU or application can access the FIFO.

Sets maximum number of received syncword bits that may be in 07H

error to start a packet receive. The number of bits is

(SYNCWORD_THRESHOLD - 1). For example, a setting of 7

means up to 6 sync word bits can be in error

Register 41

15

14

CRC_ON

R/W

1: CRC on

0: CRC off

1B

0B

SCRAMBLE_ON

Removes long patterns of continuous 0 or 1 in transmit data.

Automatically restores original unscrambled data on receive.

1: Scramble on

0: Scramble off

13

12

PACK_LENGTH_EN

FW_TERM_TX

R/W

1: CYRF8935 regards the first byte of payload as packet length 1B

descriptor byte.

1: When FIFO write point equals read point, CYRF8935

terminates Tx when the FW handles packet length.

0: FW (MCU) handles length and terminates Tx

1B

11

AUTO_ACK

R/W

1: After receiving data, automatically send ACK to acknowledge 1B

that the packet was received correctly.

0: After receiving data, do not send ACK; just go to IDLE.

Document Number: 001-61351 Rev. *J

Page 24 of 40

CYRF8935

Table 11. Framer Register Information (continued)

Bit No.

10

Bit Name

R/W

Description

1: PKT flag, FIFO flag active low

Default

PKT_FIFO_POLARITY

0B

0: Active high

9:8

7:0

(Reserved)

R/W

(Reserved)

00B

00H

CRC_INITIAL_DATA

Initialization constant for CRC calculation

Register 48 – Read only

Received CRC error

Indicate FEC23 error

Framer status

15

14

13:8

7

CRC_ERROR

R

FEC23_ERROR

FRAMER_ST

SYNCWORD_RECV

1: syncword received. It is only available in receive status,

After out receive status, always set to ‘0’

6

PKT_FLAG

FIFO_FLAG

(Reserved)

R

PKT flag indication

FIFO flag indication

(Reserved)

5

4:0

Register 50

15:0

TXRX_FIFO_REG

R/W

For MCU read/write data between the FIFO

Reading this register removes data from FIFO;

Writing to this register adds data to FIFO.

00H

Note MCU or application access to the FIFO register is

byte by byte (8 bits at a time), not 16 bits as with other registers.

Register 52

15

CLR_W_PTR

W

1: Clear Tx FIFO pointer to 0 when writing this bit to ‘1’

It is not available in RX status.

0B

14

13:8

7

(Reserved)

W

R

FIFO_WR_PTR

CLR_R_PTR

FIFO write pointer

W

1: Clear Rx FIFO point to 0 when writing this bit to ‘1’

It is not available in Tx status.

6

(Reserved)

5:0

FIFO_RD_PTR

R

FIFO read pointer (number of bytes to be read by MCU)

Document Number: 001-61351 Rev. *J

Page 25 of 40

CYRF8935

Recommended Register Values

The following register values are recommended for most typical applications. Some changes may be required depending on the

application.

Table 12. Recommended Register Values

Recommended value for applications (hex)

Power-up Reset Value

(hex)

Register No.

Notes

Silicon ID 0x1002 ^[8]

Silicon ID 0x2002 ^[8]

0

1

2

4

5

7

6FEF

5681

6619

5447

F000

0030

6FE1

5681

5517

9CC9

6647

0000

6FE1

5681

5517

9CD4

651F

0000

Internal Usage

Use for setting RF frequency, and to

start/stop Tx/Rx packets.

Register details in Table 10

8

9

71AF

3000

6C90

1920

6C90

7920

Internal Usage

Sets Tx power level.

Register details in Table 10

10

11

7FFD

4008

7FFD

0008

7FFD

0008

Crystal oscillator enabled. Used for

sleep patch.

Register details in Table 10

RSSI enabled

Register details in Table 10

12

13

22

23

24

25

26

27

0000

4855

C0FF

8005

307b

1659

1833

9100

0000

4880

00FF

0005

0067

1659

19E0

4200

0000

48BF

00FF

0005

0067

1659

1A30

4200

Internal Usage

Register details in Table 10

Internal Usage

8 µA sleep current

Register details in Table 10

28

32

1800

1806

1800

1000

1800

1000

Internal Usage

Packet data type: NRZ, no FEC,

[9]

BRCLK = 12 divided by 4 = 3 MHz

Register details in Table 11

33

34

35

6307

030B

1300

32A0

1000

0F01

32A0

1000

0F01

Internal Usage

AutoACK max Tx retries = 3

Register details in Table 11

36

37

0000

Unique sync word

Similar to a MAC address

Register details in Table 11

Similar to a MAC address

Register details in Table 11

38

Similar to a MAC address

Register details in Table 11

39

Similar to a MAC address

Register details in Table 11

Notes

8. Silicon Id can be read from Register 31.

9. BRCLK signal is available on bare die only, not packaged parts.

Document Number: 001-61351 Rev. *J

Page 26 of 40

CYRF8935

Table 12. Recommended Register Values (continued)

Recommended value for applications (hex)

Power-up Reset Value

(hex)

Register No.

Notes

Configure FIFO flag

Silicon ID 0x1002 ^[8]

Silicon ID 0x2002 ^[8]

40

2107

2047

Register details in Table 11

41

B800

F800

CRC on. SCRAMBLE off

First byte is packet length

AutoACK off

Register details in Table 11

42

43

FD6B

000F

FDFF

000F

FDFF

000F

Internal Usage

Document Number: 001-61351 Rev. *J

Page 27 of 40

CYRF8935

Current into outputs (LOW) ........................................ 10 mA

Absolute Maximum Ratings

Electrostatic discharge voltage, HBM (QFN package only)

RF pins (ANT, ANTb) ..........................................>500 V

Analog pins XTALi, XTALo ..................................>500 V

All other pins ....................................................... 2000 V

Exceeding maximum ratings may shorten the useful life of the

device. User guidelines are not tested.

[10, 11]

Storage temperature ................................ –55 °C to +125 °C

Latch up current (JEDEC JESD78B, Class II) ........ ±140 mA

Ambient temperature with

power applied .......................................... –55 °C to +125 °C

Supply voltage on V relative to GND ............0 to + 1.98 V

DD

Operating Range

Supply voltage on V

DD_IO

or V relative to GND ........................................0 to +3.63 V

Ambient

IN

Range

V_IN

V_{DD_IO}

Temperature

DC voltage applied to outputs

Commercial

0 °C to 70 °C

+1.9 to 3.6 V +1.9 to 3.6 V

in tristate .................................. (V – 0.5) to (V

+ 0.5)

SS

DD_IO

DC input voltage ...................... (V – 0.5) to (V

SS

Electrical Characteristics

For wafer and die products, RF and AC specifications are guaranteed by characterization only – not production tested.

Symbol

Description

Supply voltage

Min

Typ

Max

Units

Test Condition and Notes

V

DC power supply voltage range

Current consumption

1.9

–

3.6

VDC Input to V

and V pins

IN

DD_IO

IN

[13]

I

Current consumption – Tx

–

18.5

13.7

18

–

mA Transmit power PA2. BRCLK

off.

DD_TX2

DD_TX12

DD_RX

[13]

mA Transmit power PA12. BRCLK

off

[13]

Current consumption – Rx

Current consumption – idle

Current consumption – sleep

mA BRCLK

off

[13]

1.1

1

mA Configured for BRCLK

output off

DD_IDLE1

DD_SLPx

[12]

µA

Temperature = +25 °C.

Using firmware sleep patch. (Enter

Sleep and Wakeup on page 6)

Register 27 = 0x1200, for

V

≥ 3.00 VDC only

IN

I

–

8

–

µA

Temperature = +25 °C; using

firmware sleep patch (Enter Sleep

and Wakeup on page 6)

DD_SLPr

Register 27 = 0x4200.

38

µA

Temperature = +70 °C

‘C’ grade part; using firmware sleep

patch (Enter Sleep and Wakeup on

page 6)

DD_SLPh

Register 27 = 0x4200

V

Logic input high

0.8 V

–

8

1.2 V

DDIO

V

IH

DDIO

Logic input low

0

–

0.8

10

–

IL

I

Input leakage current

Logic output high

µA

V

_LEAK_IN

V

0.8 V

I

= 100 µA source

= 100 µA sink

OH

DD_IO

OH

OL

Logic output low

–

0.4

10

25

V

OL

I

Output leakage current

Rise/fall time (SPI MISO)

µA

ns

MISO in tristate

7 pF cap. load

_LEAK_OUT

T

_RISE_OUT

Notes

10. Absolute maximum ratings indicate limits beyond which damage to the device may occur. Recommended operating conditions indicate conditions for which the device

is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see Electrical Characteristics.

11. These devices are electrostatic-sensitive. Devices should be transported and stored in anti-static containers. Equipment and personnel contacting the devices need

to be properly grounded. Cover workbenches with grounded conductive mats.

12. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = 3 VDC, Ta = +25 °C.

IN

13. BRCLK signal is available on bare die only, not packaged parts.

Document Number: 001-61351 Rev. *J

Page 28 of 40

CYRF8935

Electrical Characteristics (continued)

For wafer and die products, RF and AC specifications are guaranteed by characterization only – not production tested.

Symbol

Description

Rise/fall time (SPI MOSI)

CLK rise, fall time (SPI)

Min

–

Typ

–

Max

25

Units

ns

Test Condition and Notes

T

_RISE_IN

T

–

25

ns

Requirement for error-free register

reading, writing.

r_spi

F

Operating frequency range

2400

–

2482

MHz Usage on-the-air is subject to local

regulatory agency restrictions

_OP

regarding operating frequency.

V

Antenna port mismatch

–

<2:1

–

VSWR Receive mode. Measured using LC

matching circuit shown in Typical

Application on page 12

SWR_I

(Z = 50 )

0

VSWR

VSWR Transmit mode. Measured using LC

matching circuit shown in Typical

Application on page 12

_O

Receive section

Measured using LC matching circuit

shown in

Typical Application on page 12

For BER  0.1%

RxS

Receiver sensitivity

(FEC off)

–

–87

–84

–

dBm Room temperature only

0-ppm crystal frequency error.

base

temp

ppm

dBm Over temperature;

0-ppm crystal frequency error.

dBm Room temperature only

80-ppm total frequency error

(± 40-ppm crystal frequency error,

each end of RF link)

RxS

–

–80

–

dBm Over temperature;

80-ppm total frequency error

(± 40-ppm crystal frequency error,

each end of RF link)

temp+ppm

R

Maximum usable signal

Data (Symbol) rate

–20

–

0

1

–

dBm Room temperature only

µs

xmax-sig

Ts

Minimum Carrier/Interference ratio

For BER  0.1%.

Room temperature only.

CI

Co-channel interference

–

+9

+6

–

dB

–60-dBm desired signal

_cochannel

Adjacent channel interference,

1-MHz offset

_1

CI

Adjacent channel

interference, 2-MHz offset

–

–12

–24

–

dB

–60-dBm desired signal

–67-dBm desired signal

_2

_3

CI

Adjacent channel

interference, 3-MHz offset

[14]

OBB

Out-of-band blocking

 –27

dBm 30 MHz to 12.75 GHz

Measured with ACX BF2520

[15]

ceramic filter

on ant. pin.

–67-dBm desired signal,

BER  0.1%.

Room temperature only.

Notes

14. The test is run at one midband frequency, typically 2460 MHz. With blocking frequency swept in 1-MHz steps, up to 24 exception frequencies are allowed. Of these,

no more than five will persist with blocking signal reduced to –50 dBm. For blocking frequencies below desired receive frequency, in-band harmonics of the out-of-band

blocking signal are the most frequent cause of failure, so be sure blocking signal has adequate harmonic filtering.

15. In some applications, this filter may be incorporated into the antenna, or be approximated by the effective antenna bandwidth.

Document Number: 001-61351 Rev. *J

Page 29 of 40

CYRF8935

Electrical Characteristics (continued)

For wafer and die products, RF and AC specifications are guaranteed by characterization only – not production tested.

Symbol

Description

Min

Typ

Max

Units

Test Condition and Notes

Transmit section

Measured using a LC matching

circuit as shown in Typical

[16]

Application on page 12

P

RF output power

–

+1

–

dBm PA0 (PA_GN = 0,

Reg9 = 0x1820

AVH

[17]

for Silicon ID

0x1002 /

Reg9 = 0x7820

[17]

for Silicon ID

0x2002).

Room temperature only.

P

–

–11.2

–

dBm PA12 (PA_GN = 12,

AVL

Reg9 = 0x1E20

[17]

for Silicon ID

0x1002 /

0x2002).

Reg9 = 0x7E20

[17]

for Silicon ID

Room temperature only.

TxP

Second harmonic

–

–45

–

dBm Measured using a LC matching

circuit as shown in

fx2

Typical Application on page 12.

Room temperature only.

Third and higher harmonics

–45

dBm Measured using a LC matching

circuit as shown in

fx3

Typical Application on page 12.

Room temperature only.

Modulation characteristics

Df1

Df2

–

263

255

–

kHz Modulation pattern: 11110000...

kHz Modulation pattern: 10101010...

avg

In-band spurious emission

IBS_2

IBS_3

IBS_4

2-MHz offset

3-MHz offset

 4-MHz offset

–

–20

–30

–

dBm

–30

RF VCO and PLL section

F

Channel (Step) size

SSB phase noise

1

–75

–105

–

MHz

step

100k

1M

L

dBc/Hz 100-kHz offset

dBc/Hz 1-MHz offset

–

dF

Crystal oscillator frequency

error

–40

–

+40

ppm Relative to 12-MHz crystal reference

frequency

X0

[18]

T

RF PLL settling time

100

250

150

350

µs

Settle to within 30 kHz of final value.

AutoCAL off.

HOP

–

µs

Settle to within 30 kHz of final value.

AutoCAL on.

HOP_AC

LDO voltage regulator section

Dropout voltage

V

–

0.17

0.3

V

Measured during receive state

DO

Notes

16. Transmit power measurement is at output of matching circuit shown in Typical Application on page 12.

17. Silicon Id can be read from Register 31.

18. Max PLL settling time is guaranteed by design (not production tested).

Document Number: 001-61351 Rev. *J

Page 30 of 40

CYRF8935

SPI

The CYRF8935 supports a 4-wire slave SPI. All of the function control is under SPI command.

There are four pins in the SPI.

■ SPI_SS: Slave selection input (active low)

■ CLK: Serial clock input

■ MOSI: Master out slave in

■ MISO: Master in slave out

SPI Transaction Formats and Timing

SPI read and write data is always in multiples of bytes. The first byte (MSB) consists of the R/W direction bit, followed by a 7-bit register

address. Following this byte, there are one or more data bytes.

When using the SPI to access the internal registers, note that some registers are accessed differently than others. Table 13 shows

the three types of registers:

Table 13. SPI Access Methods for Various Registers

Register

Group No.

Description

Access Method

Number(s)

Group 1

0 to 31

RF/analog registers

Write an even number of data bytes

Read out any number of data bytes; Register high

byte is read out first

Group 2

Group 3

32 to 42, 52

50

State and framer configuration registers

FIFO read/write

Read/writeable any data bytes

Always byte by byte

Figure 17. Single-Byte Data Format

TSSS

TSS_HD

TSSH

T1

SPI_SS

CLK

MOSI

MISO

A2

S2

W/R A6

A5

S5

A4

S4

A3

S3

A0

S0

D7

d7

D6

d6

D5

d5

D4

d4

D3

d3

D0

d0

A1

S1

D2

d2

D1

d1

S7

S6

Figure 18. Two-Byte Data Format

TSS_HD

TSSS

TSSH

T1

SPI_SS

CLK

A2

S2

MOSI

MISO

W/R A6

A5

S5

A4

S4

A3

S3

A0

S0

D7

d7

D6

d6

D5

d5

D4

d4

D3

d3

D0

d0

D7

d7

D6

d6

D5

d5

D4

d4

D3

d3

D2

d2

D1

d1

D0

d0

A1

S1

D2

d2

D1

d1

S7

S6

Figure 19. Multi-Byte Data Format^[19]

TSS_HD

TSSS

TSSH

T1

SPI_SS

CLK

A2

S2

MOSI

MISO

W/R A6

A5

S5

A4

S4

A3

S3

A0

S0

D7

d7

D6

d6

D0

D0 D7

d0 d7

D0 D7

d0 d7

D0

d0

D7

d7

D0

d0

A1

S1

D7

S7

S6

d0 d7

address+1

address+n

address

Note

19. For all registers except register 50, the internal register address auto-increments by one whenreading or writing more than two bytes of data in a single SPI transaction.

This is an optional, built-in feature designed to save time when reading or writing multiple registers in ascending sequence.

Document Number: 001-61351 Rev. *J

Page 31 of 40

CYRF8935

Specifications

■ W/R bit:

❐ 0: Write SPI

❐ 1: Read SPI

■ Dx: Data bits from SPI master. When reading, these bits are ignored.

■ dx: Data bits from SPI slave. When writing, dx is the same as Sx.

■ Sx: Data from Reg48[15:8], MSB first (status byte).

Figure 20. SPI Timing Diagram

SPI_SS

T

SS_SU

TSCK

TSSS

T

SSH

T

SCKL

CLK

T

SCKH

T

SSU

TSHD

MOSI

TSDO

T

SDO2

MISO

TSDO1

Table 14. SPI Timing Requirements

Timing Parameter

Min

20

200

40

83

30

10

200

–

Max

–

Unit

ns

Notes

T

Setup time from assertion of SPI_SS to CLK edge

Hold time required deassertion of SPI_SS

CLK minimum high time

SSS

T

–

SSH

–

SCKH

SCKL

SCK

–

CLK minimum low time

–

Maximum CLK clock is 12 MHz

MOSI setup time

–

SSU

–

MOSI hold time

SHD

–

Before SPI_SS enable, CLK hold low time requirement

Minimum SPI inactive time

SS_SU

SS_HD

SDO

–

35

5

MISO setup time, ready to read

–

If MISO is configured as tristate, MISO assertion time

SDO1

SDO2

–

250

–

If MISO is configured as tristate, MISO deassertion time

When reading register 50 (FIFO)

T1 Min_R50

T1 Min

350

83

–

When writing Register 50 (FIFO), or reading/writing any registers other than register 50.

Document Number: 001-61351 Rev. *J

Page 32 of 40

CYRF8935

Electrical Operating Characteristics

Figure 21. Typical Transmit EVM, EVM spectrum, Tx eye

Figure 22. EVM equip. setup

Document Number: 001-61351 Rev. *J

Page 33 of 40

CYRF8935

State Diagram

OFF

Sleep

VCO_Wait

IDLE

VCO_SEL

Wake Up

ACK

no CRC error

received

RX_en

TX_en

RX

packet

TX

packet

TX ack

RX ack

Document Number: 001-61351 Rev. *J

Page 34 of 40

CYRF8935

Ordering Information

[20]

Ordering Code

Package

Temperature Range

CYRF8935A-24LQXC

CYRF8935A-4X14C

CYRF8935A-4XW14C

24 pin (4 × 4 × 0.55 mm) Sawn QFN

Die (14-mil) in waffle pack

Die (14-mil) in wafer form

Commercial

Ordering Code Definitions

/ XXX )

(C , I , E)

8935 A ( 24 LQX

CY RF

Thermal Rating

C = Commercial, I = Industrial, E = Extended

KGD Level /Package Type/Die Thickness

24-pin Sawn QFN package

X =Pb- free

Internal revision code

Part Number

Marketing code:

RF = Wireless

product family

(

radio frequency

)

: CY= Cypress

Company ID

Note

20. For die and wafer sales, consult your Cypress sales representative.

Document Number: 001-61351 Rev. *J

Page 35 of 40

CYRF8935

Package Diagram

Figure 23. 24-pin QFN (4 × 4 × 0.55 mm) LQ24A 2.65 × 2.65 E-Pad (Sawn) Package Outline, 001-13937

001-13937 *E

Document Number: 001-61351 Rev. *J

Page 36 of 40

CYRF8935

Acronyms

Document Conventions

Table 15. Acronyms Used in this Document

Units of Measure

Acronym

ACK

BER

BOM

CMOS

COB

CRC

DUT

EMC

EVM

FEC

FER

GFSK

HBM

ISM

Description

Acknowledge (packet received, no errors)

Bit Error Rate

Table 16. Units of Measure

Symbol

°C

Unit of Measure

degree Celsius

decibels

Bill Of Materials

dB

Complementary Metal Oxide Semiconductor

Chip On Board

dBc

dBm

Hz

decibel relative to carrier

decibel-milliwatt

hertz

Cyclic Redundancy Check

Device Under Test

KB

Kbit

kHz

k

1024 bytes

1024 bits

Electromagnetic Compatibility

Error Vector Magnitude

Forward Error Correction

Frame Error Rate

kilohertz

kilohm

MHz

M

A

megahertz

megaohm

Gaussian Frequency-Shift Keying

Human Body Model

microampere

microsecond

microvolts

s

Industrial, Scientific, and Medical

Interrupt Request

V

IRQ

Vrms

W

mA

ms

mV

nA

microvolts root-mean-square

microwatts

MAC

MCU

NRZ

OTA

PLL

Media Access Control

Microcontroller Unit

milliampere

millisecond

millivolts

Non Return to Zero

Over-the-Air

nanoampere

nanosecond

nanovolts

Phase Locked Loop

ns

PN

Pseudo-Noise

nV

QFN

RSSI

RF

Quad Flat No-leads



ohm

Received Signal Strength Indication

Radio Frequency

pp

peak-to-peak

parts per million

picosecond

samples per second

volts

ppm

ps

Rx

Receive

Tx

Transmit

sps

V

VCO

WEP

Voltage Controlled Oscillator

Wired Equivalent Privacy

VDC

volts direct current

Document Number: 001-61351 Rev. *J

Page 37 of 40

CYRF8935

Document History Page

Document Title: CYRF8935, WirelessUSB™-NL 2.4 GHz Low Power Radio

Document Number: 001-61351

Orig. of

Change

Submission

Date

Rev.

ECN No.

Description of Change

**

2963911

3039285

HEMP

06/28/2010 New data sheet.

*A

09/27/2010 Updated Block diagram

Updated Init, Xtal Osc, RxSens measurement.

Revised state diagram and package diagram.

Updated Functional Description.

Payload format NRZ only. Revised power control table; showed absolute, not

relative power.

Deleted reference to NAK.

Added RSSI curve.

Corrected Reg. 7, 32, 41 definition.

Updated recommended register values table.

Updated Absolute Maximum voltages and temperature range.

Updated Rx I typical value.

Used PAxx to show power level settings.

Updated third harmonics and V values.

DO

Added die information to ordering code.

*B

*C

3112690

3296429

HEMP

12/16/2010 No technical updates; integrated with EROS.

HEMP /

KKCN

06/29/2011 Removed Preliminary status from datasheet.

Modified product description.

Changed GND1...GND5 to GND in the Logic Block Diagram.

Added note about BRCLK’s availability only on bare die.

Replaced 32-pin with 24-pin and package details.

Updated ‘Enter Sleep and Wakeup’ functional description.

Updated figures 7 and 8.

Updated typical application diagram.

Adding ‘Setting the Radio Frequency’ section.

Modified ‘Crystal Oscillator’ section

Deleted BRCLK pin, CKPHA signal, and FEC13 mode.

Updated ‘Reading RSSI’ section.

Updated register definitions

Updated various electrical specs.

Updated ordering information.

*D

*E

3363798

3440958

HEMP

09/07/2011 Added information on die and wafer parts in Features, Ordering Information,

and Ordering Code Definitions.

11/17/2011 Updated Power-on and Register Initialization Sequence section.

Updated Initialization Timing Requirements table.

Updated Initialization Flowchart.

Updated Typical Application and Reset Pull-up Circuit diagram.

Added Reset Pull-up section.

Added Register 27 in RF Register Information table.

Added footnote for RF PLL settling time.

Updated T

max value.

SDO

*F

3794924

SELV

12/10/2012 Updated Logic Diagram.

Added notes 1, 3, 4, 5, 7, 9, and 13.

Updated values of T_SCKH, T_SCKL, T

parameters in Table 14.

SSU

Updated Package Diagram as per spec 001-13937 *E.

Document Number: 001-61351 Rev. *J

Page 38 of 40

CYRF8935

Document History Page (continued)

Document Title: CYRF8935, WirelessUSB™-NL 2.4 GHz Low Power Radio

Document Number: 001-61351

Orig. of

Change

Submission

Date

Rev.

ECN No.

Description of Change

*G

3841304

SELV

01/10/2013 Updated Typical Application:

Updated Table 6 under Transmit Power Control to include values of Register 9

for each Silicon ID.

Added Note 6 and referred the same Note in both Silicon ID columns.

Updated Register Definitions:

Updated details of “Register 31 - Read only” in Table 10.

Updated Table 12 under Recommended Register Values to include

recommended value for applications for each Silicon ID.

Added Note 8 and referred the same Note for Silicon ID columns.

Updated Electrical Characteristics:

Updated Test Condition and Notes of P

and P

parameters to include

AVH

AVL

values of Register 9 for each silicon ID.

Added Note 17 and referred the same Note for Silicon IDs in P

and P

AVL

AVH

parameters.

*H

*I

3928385

3980337

SELV

03/11/2013 Updated Enter Sleep and Wakeup, Receive Timing, and Reset Pull-up

sections.

04/24/2013 Updated Register Definitions:

Updated Table 12 under Recommended Register Values with new values in

columns “Silicon ID 0x1002” and “Silicon ID 0x2002” for Registers 7, 23, 32,

33, 34, 35, and 41.

*J

4036152

SELV

06/21/2013 Updated Register Definitions:

Updated Table 12 under Recommended Register Values with new value in

column “Silicon ID 0x2002” for Register 26.

Completing Sunset Review.

Document Number: 001-61351 Rev. *J

Page 39 of 40

CYRF8935

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

Products

PSoC^®Solutions

Automotive

cypress.com/go/automotive

cypress.com/go/clocks

cypress.com/go/interface

cypress.com/go/powerpsoc

cypress.com/go/plc

psoc.cypress.com/solutions

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP

Clocks & Buffers

Interface

Cypress Developer Community

Lighting & Power Control

Community | Forums | Blogs | Video | Training

Technical Support

Memory

cypress.com/go/memory

cypress.com/go/psoc

cypress.com/go/support

PSoC

Touch Sensing

USB Controllers

Wireless/RF

cypress.com/go/touch

cypress.com/go/USB

cypress.com/go/wireless

any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for

medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress

integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-61351 Rev. *J

Revised June 21, 2013

Page 40 of 40

WirelessUSB and enCoRe are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.

厂商	型号	描述	页数
KYOCERA AVX	CYR10	玻璃电容器CYR10 ， 15 （可靠性指标） M23269 / 01 ， 02 （ QPL至MIL-PRF- 23269 ）[ Glass Capacitors CYR10, 15 (Established Reliability) M23269/01, 02 (QPL to MIL-PRF-23269) ]	2 页
FOXCONN	CYR2-AP03MJ04	[ Interconnection Device ]	1 页
KYOCERA AVX	CYR51	玻璃电容器CYR51 ， 52 ， 53 （可靠性指标） M23269 / 10 （ QPL至MIL-PRF- 23269 ）[ Glass Capacitors CYR51, 52, 53 (Established Reliability) M23269/10 (QPL to MIL-PRF-23269) ]	2 页
KYOCERA AVX	CYR52	玻璃电容器CYR51 ， 52 ， 53 （可靠性指标） M23269 / 10 （ QPL至MIL-PRF- 23269 ）[ Glass Capacitors CYR51, 52, 53 (Established Reliability) M23269/10 (QPL to MIL-PRF-23269) ]	2 页
KYOCERA AVX	CYR53	玻璃电容器CYR51 ， 52 ， 53 （可靠性指标） M23269 / 10 （ QPL至MIL-PRF- 23269 ）[ Glass Capacitors CYR51, 52, 53 (Established Reliability) M23269/10 (QPL to MIL-PRF-23269) ]	2 页
CYPRESS	CYRF69103	无线可编程片上低功耗[ Programmable Radio on Chip Low Power ]	73 页
CYPRESS	CYRF69103-40LFXC	无线可编程片上低功耗的16位自由运行定时器[ Programmable Radio on Chip Low Power 16-bit free running timer ]	68 页
CYPRESS	CYRF69103-40LTXC	无线可编程片上低功耗[ Programmable Radio on Chip Low Power ]	72 页
CYPRESS	CYRF69103A-40LFXC	无线可编程片上低功耗[ Programmable Radio on Chip Low Power ]	68 页
CYPRESS	CYRF69103_08	无线可编程片上低功耗[ Programmable Radio on Chip Low Power ]	65 页