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CYP15G0101DXB

CYV15G0101DXB

Single-channel HOTLink II™ Transceiver

■ Compatible with

❐ Fiber-optic modules

❐ Copper cables

Features

■ Second-generation HOTLink^®technology

❐ Circuit board traces

■ Compliant to multiple standards

❐ ESCON^®, DVB-ASI, fibre channel and gigabit ethernet

■ JTAG boundary scan

(IEEE802.3z)

❐ CPRI™ compliant

■ Built-in self-test (BIST) for at-speed link testing

❐ CYV15G0101DXB compliant to SMPTE 259M and SMPTE

■ Per-channel link quality indicator

❐ Analog signal detect

❐ Digital signal detect

292M

❐ 8B/10B encoded or 10-bit unencoded data

■ Single-channel transceiver operates from 195 to 1500 MBaud

serial data rate

■ Low power 1.25 W at 3.3 V typical

■ Single 3.3 V supply

■ Selectable parity check/generate

■ Selectable input clocking options

■ Selectable output clocking options

■ 100-ball BGA

■ Pb-free package option available

■ 0.25 µ BiCMOS technology

■ MultiFrame™ Receive Framer

❐ Bit and byte alignment

❐ Comma or full K28.5 detect

❐ Single- or multi-byte framer for byte alignment

❐ Low-latency option

Functional Description

The CYP15G0101DXB^[1]single-channel HOTLink II™

transceiver is a point-to-point communications building block

allowing the transfer of data over a high-speed serial link (optical

fiber, balanced, and unbalanced copper transmission lines) at

signaling speeds ranging from 195 to 1500 MBaud.

■ Synchronous LVTTL parallel input and parallel output interface

■ Internal phase-locked loops (PLLs) with no external PLL

components

The transmit channel accepts parallel characters in an input

register, encodes each character for transport, and converts it to

serial data. The receive channel accepts serial data and converts

it to parallel data, frames the data to character boundaries,

decodes the framed characters into data and special characters,

and presents these characters to an output register. Figure 1

illustrates typical connections between independent host

systems and corresponding CYP(V)15G0101DXB parts. As a

second-generation HOTLink device, the CYP(V)15G0101DXB

extends the HOTLink II family with enhanced levels of

integration and faster data rates, while maintaining serial-link

compatibility (data, command, and BIST) with other HOTLink

devices.

■ Dual differential PECL-compatible serial inputs

❐ Internal DC-restoration

■ Dual differential PECL-compatible serial outputs

❐ Source matched for driving 50  transmission lines

❐ No external bias resistors required

❐ Signaling-rate controlled edge-rates

■ Optional elasticity buffer in receive path

■ Optional phase align buffer in transmit path

Figure 1. HOTLink II System Connections

10

Serial Link

10

Backplane or Cabled

Connections

Note

1. CYV15G0101DXB refers to SMPTE 259M and SMPTE 292M compliant devices. CYP15G0101DXB refers to devices not compliant to SMPTE 259M and SMPTE

292M pathological test requirements. CYP(V)15G0101DXB refers both devices.

Cypress Semiconductor Corporation

Document Number: 38-02031 Rev. *N

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 17, 2012

CYP15G0101DXB

CYV15G0101DXB

The CYV15G0101DXB satisfies the SMPTE 259M and SMPTE

292M compliance as per the EG34-1999 pathological test

The parallel I/O interface may be configured for numerous forms

of clocking to provide the highest flexibility in system

architecture. In addition to clocking the transmit path interfaces

from one or multiple sources, the receive interface may be

configured to present data relative to a recovered clock or to a

local reference clock.

requirements. The

transmit

(TX)

section

of

the

CYP(V)15G0101DXB single-channel HOTLink II consists of a

byte-wide channel. The channel can accept either eight-bit data

characters or pre-encoded 10-bit transmission characters. Data

characters are passed from the transmit input register to an

embedded 8B/10B encoder to improve their serial transmission

characteristics. These encoded characters are then serialized

and output from dual positive ECL (PECL)-compatible

differential transmission-line drivers at a bit-rate of either 10 or

20 times the input reference clock.

The transmit and the receive channels contain BIST pattern

generators and checkers, respectively. This BIST hardware

allows at-speed testing of the high-speed serial data paths in

both transmit and receive sections, as well as across the

interconnecting links.

HOTLink II devices are ideal for a variety of applications where

parallel interfaces can be replaced with high-speed,

point-to-point serial links. Some applications include

interconnecting backplanes on switches, routers, base-stations,

servers and video transmission systems.

The receive (RX) section of the CYP(V)15G0101DXB

single-channel HOTLink II consists of a byte-wide channel. The

channel accepts

a serial bit-stream from one of two

PECL-compatible differential line receivers and, using a

completely integrated PLL clock synchronizer, recovers the

timing information necessary for data reconstruction. The

recovered bit-stream is deserialized and framed into characters,

8B/10B decoded, and checked for transmission errors.

Recovered decoded characters are then written to an internal

elasticity buffer, and presented to the destination host system.

The integrated 8B/10B encoder/decoder may be bypassed for

systems that present externally encoded or scrambled data at

the parallel interface.

The CYV15G0101DXB is verified by testing to be compliant to

all the pathological test patterns documented in SMPTE

EG34-1999, for both the SMPTE 259M and 292M signaling

rates. The tests ensure that the receiver recovers data with no

errors for the following patterns:

1. Repetitions of 20 ones and 20 zeros.

2. Single burst of 44 ones or 44 zeros.

3. Repetitions of 19 ones followed by 1 zero or 19 zeros followed

by 1 one.

Transceiver Logic Block Diagram

x10

x11

Phase

Align

Buffer

Elasticity

Buffer

Decoder

8B/10B

Encoder

8B/10B

Framer

Serializer

Deserializer

RX

TX

Document Number: 38-02031 Rev. *N

Page 2 of 43

CYP15G0101DXB

CYV15G0101DXB

= Internal Signal

TRSTZ

Logic Block Diagram

REFCLK+

REFCLK–

TXRATE

Character-Rate Clock

Transmit PLL

Clock Multiplier

Bit-Rate Clock

SPDSEL

Character-Rate Clock

TXCLKO+

TXCLKO–

2

Transmit

Mode

TXMODE[1:0]

TXPER

SCSEL

12

10

12

OUT1+

OUT1–

TXD[7:0]

8

TXOP

OUT2+

OUT2–

2

TXCT[1:0]

TXLB

TXCKSEL

H M L

2

TXCLK

TXRST

4

Output

Enable

Latch

PARCTL

BOE[1:0]

OELE

BIST Enable

Latch

RX PLL Enable

Latch

BISTLE

RXLE

Character-Rate Clock

SDASEL

LPEN

INSEL

Receive

Signal

LFI

Monitor

IN1+

IN1–

8

RXD[7:0]

IN2+

IN2–

Clock &

Data

Recovery

PLL

RXOP

3

RXST[2:0]

TXLB

FRAMCHAR

RFEN

RXCLK+

RXCLK–

Clock

Select

2

RFMODE

Delay

DECMODE

RXRATE

RXCLKC+

RXMODE

RXCKSEL

TMS

TCLK

TDI

JTAG

Boundary

Scan

Controller

TDO

Document Number: 38-02031 Rev. *N

Page 3 of 43

CYP15G0101DXB

CYV15G0101DXB

Contents

Pin Configuration ............................................................5

Pin Descriptions ...............................................................6

CYP(V)15G0101DXB HOTLink II Operation ..................12

CYP(V)15G0101DXB Transmit Data Path ................12

Transmit Modes .........................................................13

Transmit BIST ...........................................................15

Serial Output Drivers .................................................16

Transmit PLL Clock Multiplier ....................................16

CYP(V)15G0101DXB Receive Data Path .......................16

Serial Line Receivers ................................................16

Signal Detect/Link Fault ............................................17

Clock/Data Recovery .................................................18

Deserializer/Framer ...................................................18

10B/8B Decoder Block ..............................................19

Receive BIST Operation ............................................19

Receive Elasticity Buffer ............................................20

Receive Modes ..........................................................20

Power Control ............................................................20

Output Bus ................................................................21

Parity Generation ......................................................22

JTAG Support ............................................................23

Maximum Ratings ...........................................................25

Power-up Requirements ............................................25

DC Electrical Characteristics ........................................25

AC Test Loads and Waveforms .....................................26

CYP(V)15G0101DXB AC Characteristics ......................27

Switching Waveforms for the HOTLink II Transmitter .29

X3.230 Codes and Notation Conventions ....................33

Notation Conventions ................................................33

8B/10B Transmission Code .......................................33

Transmission Order ...................................................33

Valid and Invalid Transmission Characters ...............33

Use of the Tables for Generating Transmission

Characters ........................................................................34

Use of the Tables for Checking the Validity of

Received Transmission Characters ..................................34

Ordering Information ......................................................40

Ordering Code Definitions .........................................40

Package Diagram ............................................................41

Acronyms ........................................................................41

Document Conventions ................................................41

Document History Page .................................................42

Sales, Solutions, and Legal Information ......................43

Worldwide Sales and Design Support .......................43

Products ....................................................................43

PSoC Solutions .........................................................43

Document Number: 38-02031 Rev. *N

Page 4 of 43

CYP15G0101DXB

CYV15G0101DXB

Pin Configuration

Top View

5

1

2

3

4

6

7

8

9

10

V_CC

IN2+

V_CC

OUT2– RXMODE TXMODE[1]

OUT2+ TXRATE TXMODE[0]

RXCLKC+ RXRATE SDASEL

IN1+

V_CC

OUT1–

V_CC

A

V_CC

IN2–

TDO

IN1–

SPDSEL

GND

#NC^[2]

OUT1+

V_CC

INSEL

TDI

B

RFEN

LPEN

RXLE

PARCTL RFMODE

C

BOE[0]

BOE[1] FRAMCHAR

GND

LFI

GND

TMS

TRSTZ

D

BISTLE DECMODE

OELE

RXST[0]

RXD[5]

RXD[6]

RXD[7]

V_CC

GND

TCLK

RXCKSEL TXCKSEL

E

RXST[2]

RXST[1]

RXD[1]

RXD[2]

RXD[3]

RXD[4]

GND

TXPER REFCLK– REFCLK+

F

RXOP

GND

TXOP

TXCLK

TXD[0]

V_CC

TXCLKO+ TXCLKO–

G

RXD[0]

TXCT[1]

TXD[6]

TXD[5]

TXD[4]

TXD[3]

TXD[2]

TXD[1]

TXRST

#NC^[2]

SCSEL

#NC^[2]

V_CC

H

V_CC

RXCLK– TXCT[0]

J

V_CC

RXCLK+

TXD[7]

V_CC

K

Bottom View

5

10

9

8

7

6

4

3

2

1

V_CC

OUT1–

V_CC

IN1+

TXMODE[1] RXMODE OUT2–

TXMODE[0] TXRATE OUT2+

SDASEL RXRATE RXCLKC+

V_CC

IN2+

V_CC

A

B

C

D

E

F

V_CC

OUT1+

#NC^[2]

IN1–

SPDSEL

GND

TDO

IN2–

V_CC

INSEL RFMODE PARCTL

RXLE

LPEN

RFEN

BOE[0]

TDI

TRSTZ

TMS

GND

LFI

FRAMCHAR BOE[1]

TXCKSEL RXCKSEL

TCLK

GND

OELE

RXST[0]

RXD[5]

RXD[6]

RXD[7]

V_CC

DECMODE BISTLE

REFCLK+ REFCLK– TXPER

GND

RXST[1]

RXD[1]

RXD[2]

RXD[3]

RXD[4]

RXST[2]

RXOP

RXD[0]

V_CC

TXCLKO– TXCLKO+

TXOP

TXCLK

TXD[0]

V_CC

GND

G

H

J

#NC^[2]

V_CC

TXRST

#NC^[2]

SCSEL

TXD[3]

TXD[2]

TXD[1]

TXD[6]

TXD[5]

TXD[4]

TXCT[1]

TXCT[0] RXCLK–

TXD[7] RXCLK+

V_CC

K

Note

2. #NC = Do Not Connect.

Document Number: 38-02031 Rev. *N

Page 5 of 43

CYP15G0101DXB

CYV15G0101DXB

Pin Descriptions

CYP(V)15G0101DXB single-channel HOTLink II

Pin Name

I/OCharacteristics Signal Description

Transmit Path Data Signals

TXPER

LVTTL output,

Transmit path parity error. Active HIGH. Asserted (HIGH) if parity checking is enabled

changes relative to (PARCTL  LOW) and a parity error is detected at the encoder. This output is HIGH for one

REFCLK^[3]

transmit character-clock period to indicate detection of a parity error in the character

presented to the encoder.

If a parity error is detected, the character in error is replaced with a C0.7 character to force a

corresponding bad-character detection at the remote end of the link. This replacement takes

place regardless of the encoded/un-encoded state of the interface.

When BIST is enabled for the specific transmit channel, BIST progress is presented on this

output. Once every 511 character times (plus a 16-character Word Sync Sequence when the

receive channel is clocked by REFCLK, i.e., RXCKSEL = LOW), the TXPER signal pulses

HIGH for one transmit-character clock period (if RXCKSEL = MID) or seventeen

transmit-character clock periods (if RXCKSEL = LOW or HIGH) to indicate a complete pass

through the BIST sequence. For RXCKSEL = LOW or HIGH, If TXMODE[1:0] = LL, then no

Word Sync Sequence is sent in BIST, and TXPER pulses HIGH for one transmit-character

clock period.

This output also provides an indication of a phase-align buffer underflow/overflow condition.

When the phase-align buffer is enabled (TXCKSEL  LOW, or TXCKSEL = LOW and

TXRATE = HIGH), and an underflow/overflow condition is detected, TXPER is asserted and

remains asserted until either an atomic Word Sync Sequence is transmitted or TXRST is

sampled LOW to recenter the phase-align buffer.

TXCT[1:0]

LVTTL input,

synchronous,

sampled by

TXCLK or

REFCLK^[3]

Transmit control. These inputs are captured on the rising edge of the transmit interface clock

as selected by TXCKSEL, and are passed to the encoder or transmit shifter. They identify

how the TXD[7:0] characters are interpreted. When the encoder is enabled, these inputs

determine if the TXD[7:0] character is encoded as data, a special character code, a K28.5 fill

character or a Word Sync Sequence. When the encoder is bypassed, these inputs are

interpreted as data bits. See Table 1 for details.

TXD[7:0]

TXOP

LVTTL input,

synchronous,

sampled by

TXCLK or

REFCLK^[3]

Transmit data inputs. These inputs are captured on the rising edge of the transmit interface

clock as selected by TXCKSEL, and passed to the encoder or transmit shifter.

When the encoder is enabled (TXMODE[1]  LOW), TXD[7:0] specify the specific data or

command character to be sent. When the encoder is bypassed, these inputs are interpreted

as data bits of the 10-bit input character. See Table 1 for details.

LVTTL input,

synchronous,

internal pull-up,

sampled by

Transmit path odd parity. When parity checking is enabled (PARCTL  LOW), the parity

captured at this input is XORed with the data on the TXD bus (and sometimes TXCT[1:0]) to

verify the integrity of the captured character. See Table 2 for details.

TXCLK or

REFCLK^[3]

SCSEL

LVTTL input,

synchronous,

Special character select. Used in some transmit modes along with TXCTx[1:0] to encode

special characters or to initiate a Word Sync Sequence. When the transmit path is configured

internal pull-down, to select TXCLK to clock the input register (TXCKSEL = MID or HIGH), SCSEL is captured

sampled by

TXCLK or

REFCLK^[3]

relative to TXCLK.

Note

3. When REFCLK is configured for half-rate operation (TXRATE = HIGH), this input is sampled (or the outputs change) relative to both the rising and falling edges of

REFCLK.

Document Number: 38-02031 Rev. *N

Page 6 of 43

CYP15G0101DXB

CYV15G0101DXB

Pin Descriptions

CYP(V)15G0101DXB single-channel HOTLink II (continued)

Pin Name

I/OCharacteristics Signal Description

TXRST

LVTTL input,

asynchronous,

internal pull-up,

sampled by

Transmit clock phase reset. Active LOW. When sampled LOW, the transmit phase-align

buffer is allowed to adjust its data-transfer timing (relative to the selected input clock) to allow

clean transfer of data from the input register to the encoder or transmit shifter. When TXRST

is sampled HIGH, the internal phase relationship between the TXCLK and the internal

character-rate clock is fixed and the device operates normally.

REFCLK^[4]

When configured for half-rate REFCLK sampling of the transmit character stream (TXCKSEL

= LOW and TXRATE = HIGH), assertion of TXRST is only used to clear phase-align buffer

faults caused by highly asymmetric reference clock periods or reference clocks with excessive

cycle-to-cycle jitter. During this alignment period, one or more characters may be added to or

lost from all the associated transmit paths as the transmit phase-align buffers are adjusted.

TXRST must be sampled LOW by a minimum of two consecutive rising edges of REFCLK to

ensure the reset operation is initiated correctly on all channels. This input is ignored when

both TXCKSEL and TXRATE are LOW, since the phase align buffer is bypassed. In all other

configurations, TXRST should be asserted during device initialization to ensure proper

operation of the phase-align buffer. TXRST should be asserted after the assertion and

deassertion of TRSTZ, after the presence of a valid TXCLK and after allowing enough time

for the TXPLL to lock to the reference clock (as specified by parameter t_TXLOCK).

Transmit Path Clock and Clock Control

TXCKSEL

3-level select static Transmit clock select. Selects the clock source used to write data into the transmit input

control input^[5]

register of the transmit channel. When LOW, the input register is clocked by REFCLK.^[4]

When HIGH or MID, TXCLK is the input register clock for TXD[7:0] and TXCT[1:0].

When TXRATE=HIGH, configuring TXCKSEL = HIGH or MID is an invalid mode of operation.

TXCLKO

LVTTL output

Transmit clock output. This true and complement output clock is synthesized by the transmit

PLL and is synchronous to the internal transmit character clock. It has the same frequency

as REFCLK (when TXRATE = LOW), or twice the frequency of REFCLK (when

TXRATE = HIGH). This output clock has no direct phase relationship to REFCLK.

TXRATE

LVTTL input,

Transmit PLL clock rate select. When TXRATE = HIGH, the transmit PLL multiplies

static control input, REFCLK by 20 to generate the serial bit-rate clock.

internal pull-down

When TXRATE = LOW, the transmit PLL multiplies REFCLK by 10 to generate the serial

bit-rate clock. See Table 9 for a list of operating serial rates.

When REFCLK is selected to clock the receive parallel interfaces (RXCKSEL = LOW), the

TXRATE input also determines if the clocks on the RXCLK and RXCLKC outputs are full

or half-rate. When TXRATE = HIGH (REFCLK is half-rate), the RXCLK± and RXCLKC+ output

clocks are also half-rate clocks and follow the frequency and duty cycle of the REFCLK input.

When TXRATE = LOW (REFCLK is full-rate), the RXCLK± and RXCLKC+ output clocks are

also full-rate clocks and follow the frequency and duty cycle of the REFCLK input.

When TXRATE=HIGH, configuring TXCKSEL = HIGH or MID is an invalid mode of operation.

TXCLK

LVTTL clock input, Transmit path input clock. This clock must be frequency-coherent to TXCLKO, but may

internal pull-down

be offset in phase. The internal operating phase of the input clock (relative to REFLCK or

TXCLKO+) is adjusted when TXRST = LOW and locked when TXRST = HIGH.

Transmit Path Mode Control

TXMODE[1:0] 3-level select^[5]

Transmit operating mode. These inputs are interpreted to select one of nine operating

static control inputs modes of the transmit path. See Table 3 for a list of operating modes.

Notes

4. When REFCLK is configured for half-rate operation (TXRATE = HIGH), this input is sampled (or the outputs change) relative to both the rising and falling edges of

REFCLK.

5. 3-level select inputs are used for static configuration. They are ternary (not binary) inputs that make use of non-standard logic levels of LOW, MID, and HIGH. The

LOW level is usually implemented by direct connection to V (ground). The HIGH level is usually implemented by direct connection to V (power). When not

SS

CC

connected or allowed to float, a 3-level select input will self-bias to the MID level.

Document Number: 38-02031 Rev. *N

Page 7 of 43

CYP15G0101DXB

CYV15G0101DXB

Pin Descriptions

CYP(V)15G0101DXB single-channel HOTLink II (continued)

Pin Name

I/OCharacteristics Signal Description

Receive Path Data Signals

RXD[7:0]

RXST[2:0]

RXOP

LVTTL output,

synchronous to the interface clock.

Parallel data output. These outputs change following the rising edge of the selected receive

RXCLK output (or

When the decoder is enabled (DECMODE = HIGH or MID), these outputs represent either

received data or a special character. The status of the received data is represented by the

values of RXST[2:0].

REFCLKinput^[6]

when

RXCKSEL = LOW)

When the decoder is bypassed (DECMODE = LOW), RXD[7:0] become the higher order bits

of the 10-bit received character. See Table 13 for details.

LVTTL output,

synchronous to the receive interface clock.

Parallel status output. These outputs change following the rising edge of the selected

RXCLK output (or

When the decoder is bypassed (DECMODE = LOW), RXST[1:0] become the two low-order

bits of the 10-bit received character, while RXST[2] = HIGH indicates the presence of a

comma character in the output register.

REFCLKinput^[6]

when

RXCKSEL = LOW)

When the decoder is enabled (DECMODE = HIGH or MID), RXST[2:0] provide status of the

received signal. See Table 16 for a list of receive character status.

3-state,

Receive path odd parity. When parity generation is enabled (PARCTL  LOW), the parity

output is valid for the data on the RXD bus bits.

LVTTL output,

synchronous to the

RXCLK output (or

REFCLKinput^[6]

when

When parity generation is disabled (PARCTL = LOW), this output driver is disabled (high Z).

RXCKSEL = LOW)

Receive Path Clock and Clock Control

RXCLK

3-state,

Receive character clock output. When configured such that the output data path is clocked

LVTTL output clock by the recovered clock (RXCKSEL = MID), these true and complement clocks are the receive

interface clocks which are used to control timing of output data (RXD[7:0], RXST[2:0] and

RXOP). This clock is output continuously at either the dual-character rate (1/20^ththe serial

bit-rate) or character rate (1/10^ththe serial bit-rate) of the data being received, as selected by

RXRATE.

When configured such that the output data path is clocked by REFCLK instead of recovered

clock (RXCKSEL = LOW), the RXCLK output drivers present a buffered and delayed form

of REFCLK. In this mode, RXCLK and RXCLKC+ are buffered forms of REFCLK that are

slightly different in phase, but follow the frequency and duty cycle of REFCLK. This phase

difference allows the user to select the optimal set-up/hold timing for their specific interface.

RXCLKC+

RXRATE

3-state, LVTTL

output

Delayed REFCLK+ when RXCKSEL = LOW. Delayed form of REFCLK+, used for transfer

of output data to a host system. This output is only enabled when the receive parallel interface

is configured to present data relative to REFCLK (RXCKSEL = LOW). When RXCKSEL =

LOW, the RXCLKC+ follows the frequency and duty cycle of REFCLK+.

LVTTL input

Receive clock rate select. When LOW, the RXCLK recovered clock outputs are

static control input, complementary clocks operating at the recovered character rate. Data for the receive channel

internal pull-down

should be latched on either the rising edge of RXCLK+ or falling edge of RXCLK–.

When HIGH, the RXCLK recovered clock outputs are complementary clocks operating at

half the character rate. Data for the receive channel should be latched alternately on the rising

edge of RXCLK+ and RXCLK–.

When the output register is operated with REFCLK clocking (RXCKSEL = LOW), RXRATE is

not interpreted and RXCLK± follows the frequency and duty cycle of REFCLK.

RFEN

LVTTL input,

asynchronous,

internal pull-down

Reframe enable. Active HIGH. When HIGH, the Framer in the receive channel is enabled to

frame per the presently enabled framing mode and selected framing character.

Note

6. When REFCLK is configured for half-rate operation (TXRATE = HIGH), this input is sampled (or the outputs change) relative to both the rising and falling edges of

REFCLK.

Document Number: 38-02031 Rev. *N

Page 8 of 43

CYP15G0101DXB

CYV15G0101DXB

Pin Descriptions

CYP(V)15G0101DXB single-channel HOTLink II (continued)

Pin Name

I/OCharacteristics Signal Description

RXMODE

3-level select^[7]

static control input

Receive operating mode. This input selects one of two RXST channel status reporting

modes and is only interpreted when the decoder is enabled (DECMODE  LOW). See

Table 19 for details.

FRAMCHAR 3-level select^[7]

static control input

Framing character select. Used to select the character or portion of a character used for

character framing of the received data streams.

When MID, the framer looks for both positive and negative disparity versions of the eight-bit

comma character.

When HIGH, the framer looks for both positive and negative disparity versions of the K28.5

character.

Configuring FRAMCHAR = LOW is reserved for component test.

RFMODE

3-level select static Reframe mode select. Used to select the type of character framing used to adjust the

control input^[7]

character boundaries (based on detection of one or more framing characters in the data

stream. This signal operates in conjunction with the type of framing character selected.

When LOW, the low-latency framer is selected. This will frame on each occurrence of the

selected framing character(s) in the received data stream. This mode of framing stretches the

recovered character-rate clock for one or multiple cycles to align that clock with the recovered

data.

When MID, the Cypress-mode multi-byte parallel framer is selected. This requires a pair of

the selected framing character(s), on identical 10-bit boundaries, within a span of 50 bits (five

characters), before the character boundaries are adjusted. The recovered character clock

remains in the same phase regardless of character offset.

When HIGH, the alternate-mode multi-byte parallel framer is selected. This requires detection

of the selected framing character(s) in the received data stream, on identical 10-bit

boundaries, on four directly adjacent characters. The recovered character clock remains in

the same phase regardless of character offset.

PARCTL

3-level select static Parity check/Generate control. Used to control the parity check and generate functions.

control input^[7]

When LOW, parity checking is disabled, and the RXOP output is disabled (high Z).

When MID, and the 8B/10B encoder and decoder are enabled (TXMODE[1]  LOW,

DECMODE  LOW), TXD[7:0] inputs are checked (along with TXOP) for valid ODD parity,

and ODD parity is generated for the RXD[7:0] outputs and presented on RXOP. When the

8B/10B encoder and decoder are disabled (TXMODE[1]  LOW, DECMODE  LOW), the

TXD[7:0] and TXCT[1:0] inputs are checked (along with TXOP) for valid ODD parity, and ODD

parity is generated for the RXD[7:0] and RXST[1:0] outputs and presented on RXOP.

When HIGH, parity generation and checking are enabled. The TXD[7:0] and TXCT[1:0] inputs

are checked (along with TXOP) for valid ODD parity, and ODD parity is generated for the

RXD[7:0] and RXST[2:0] outputs and presented on RXOP.

See Table 2 and Table 15 for details.

DECMODE

RXCKSEL

3-level select static Decoder mode select. When LOW, the decoder is bypassed and raw 10-bit characters are

control input^[7]

passed to the output register. When the decoder is bypassed, RXCKSEL must be MID.

When MID, the Cypress Decoder table for special code characters is used. When HIGH, the

alternate Decoder table for special code characters is used. See Table 21 for a list of the

special codes supported in both encoded modes.

3-level select^[7]

static control input

Receive clock mode. Selects the receive clock source used to transfer data to the output

registers and configures the elasticity buffer in the receive path.

When LOW, the output register is clocked by REFCLK. RXCLKand RXCLKC+ present

buffered and delayed forms of REFCLK.

When MID, the RXCLK output follows the recovered clock as selected by RXRATE and the

elasticity buffer is bypassed. When the 10B/8B decoder and elasticity buffer are bypassed

(DECMODE=LOW), RXCKSEL must be MID.

Configuring RXCKSEL = HIGH is an invalid mode of operation.

Note

7. 3-level select inputs are used for static configuration. They are ternary (not binary) inputs that make use of non-standard logic levels of LOW, MID, and HIGH. The

LOW level is usually implemented by direct connection to V (ground). The HIGH level is usually implemented by direct connection to V (power). When not

SS

CC

connected or allowed to float, a 3-level select input will self-bias to the MID level.

Document Number: 38-02031 Rev. *N

Page 9 of 43

CYP15G0101DXB

CYV15G0101DXB

Pin Descriptions

CYP(V)15G0101DXB single-channel HOTLink II (continued)

Pin Name

I/OCharacteristics Signal Description

Device Control Signals

SPDSEL

3-level select,^[8]

static control input

Serial rate select. This input specifies the operating bit-rate range of both transmit and

receive PLLs. LOW = 195–400 MBaud, MID = 400–800 MBaud, HIGH = 800–1500 MBaud.

When SPDSEL=LOW, setting TXRATE=HIGH (half-rate reference clock) is invalid.

REFCLK

DifferentialLVPECL Reference clock. This clock input is used as the timing reference for the transmit PLL. It is

or single-ended

also used as the centering frequency of the range controller block of the receive CDR PLLs.

This input clock may also be selected to clock the transmit and receive parallel interfaces.

LVTTL input clock

When driven by a single-ended LVCMOS or LVTTL clock source, the clock source may be

connected to either the true or complement REFCLK input, with the alternate REFCLK input

left open (floating). When driven by an LVPECL clock source, the clock must be a differential

clock, using both inputs. When TXCKSEL = LOW, REFCLK is also used as the clock for the

parallel transmit data (input) interface. When RXCKSEL = LOW and decoder is enabled, the

elasticity buffer is enabled and REFCLK is used as the clock source for the parallel receive

data (output) interface.

If the elasticity buffer is used, framing characters will be inserted or deleted to/from the data

stream to compensate for frequency differences between the reference clock and recovered

clock. When addition happens, a K28.5 will be appended immediately after a framing

character is detected in the elasticity buffer. When deletion happens, a framing character will

be removed from the data stream when detected in the elasticity buffer.

TRSTZ

LVTTL input,

internal pull-up

Device reset. Active LOW. Initializes all state machines and counters in the device.

When sampled LOW by the rising edge of REFLCK, this input resets the internal state

machines and sets the elasticity buffer pointers to a nominal offset. When the reset is removed

(TRSTZ sampled HIGH by REFCLK), the status and data outputs will become deterministic

in less than 16 REFCLK cycles. The BISTLE, OELE, and RXLE latches are reset by TRSTZ.

If the elasticity buffer or the phase-align buffer are used, TRSTZ should be applied after

power-up to initialize the internal pointers into these memory arrays.

Analog I/O and Control

OUT1

OUT2

IN1

CML differential

output

Primary differential serial data outputs. These PECL-compatible CML outputs (+3.3 V

referenced) are capable of driving terminated transmission lines or standard fiber-optic trans-

mitter modules.

CML differential

output

Secondary differential serial data outputs. These PECL-compatible CML outputs (+3.3 V

referenced) are capable of driving terminated transmission lines or standard fiber-optic trans-

mitter modules.

LVPECL differential Primary differential serial data inputs. These inputs accept the serial data stream for

Input, with internal

DC restoration

deserialization and decoding. The IN1serial stream is passed to the receiver clock and data

recovery (CDR) circuit to extract the data content when INSEL = HIGH.

IN2

LVPECL differential Secondary differential serial data inputs. These inputs accept the serial data stream for

input, with internal

deserialization and decoding. The IN2serial stream is passed to the receiver CDR circuit to

extract the data content when INSEL = LOW.

DC restoration

INSEL

SDASEL

LPEN

LVTTL input,

asynchronous

3-level select,^[8]

Receive input selector. Determines which external serial bit stream is passed to the receiver

CDR. When HIGH, the IN1 input is selected. When LOW, the IN2 input is selected.

Signal detect amplitude level select. Allows selection of one of three predefined amplitude

trip points for a valid signal indication, as listed in Table 10.

static control input

LVTTL input,

asynchronous,

internal pull-down

Loop-back-enable. Active HIGH. When asserted (HIGH), the transmit serial data is internally

routed to the receiver CDR circuit.All enabled serial drivers are forced to differential logic “1.”

All serial data inputs are ignored.

8. 3-level select inputs are used for static configuration. They are ternary (not binary) inputs that make use of non-standard logic levels of LOW, MID, and HIGH. The

LOW level is usually implemented by direct connection to V (ground). The HIGH level is usually implemented by direct connection to V (power). When not

SS

CC

connected or allowed to float, a 3-level select input will self-bias to the MID level.

Document Number: 38-02031 Rev. *N

Page 10 of 43

CYP15G0101DXB

CYV15G0101DXB

Pin Descriptions

CYP(V)15G0101DXB single-channel HOTLink II (continued)

Pin Name

I/OCharacteristics Signal Description

OELE

LVTTL input,

asynchronous,

internal pull-up

Serial driver output enable latch enable. Active HIGH. When OELE = HIGH, the signals on

the BOE[1:0] inputs directly control the OUTx differential drivers. When the BOE[x] input is

HIGH, the associated OUTx differential driver is enabled. When the BOE[x] input is LOW,

the associated OUTx differential driver is powered down. When OELE returns LOW, the last

values present on BOE[1:0] are captured in the internal output enable latch. The specific

mapping of BOE[1:0] signals to transmit output enables is listed in Table 14. If the device is

reset (TRSTZ is sampled LOW), the latch is reset to disable both outputs.

BISTLE

LVTTL input,

asynchronous,

internal pull-up

Transmit and receive BIST latch enable. Active HIGH. When BISTLE = HIGH, the signals

on the BOE[1:0] inputs directly control the transmit and receive BIST enables. When the

BOE[x] input is LOW, the associated transmit or receive channel is configured to generate or

compare the BIST sequence. When the BOE[x] input is HIGH, the associated transmit or

receive channel is configured for normal data transmission or reception. When BISTLE

returns LOW, the last values present on BOE[1:0] are captured in the internal BIST enable

latch. The specific mapping of BOE[1:0] signals to transmit and receive BIST enables is listed

in Table 14. When the latch is closed, if the device is reset (TRSTZ is sampled LOW), the latch

is reset to disable BIST on both the transmit and receive channels.

RXLE

LVTTL input,

asynchronous,

internal pull-up

Receive channel power-control latch enable. Active HIGH. When RXLE = HIGH, the

signal on the BOE[0] input directly controls the power enable for the receive PLL and analog

logic. When the BOE[0] input is HIGH, the receive channel PLL and analog logic are active.

When the BOE[0] input is LOW, the receive channel PLL and analog logic are placed in a

non-functional power saving mode. When RXLE returns LOW, the last value present on

BOE[0] is captured in the internal RX PLL enable latch. The specific mapping of BOE[1:0]

signals to the receive channel enable is listed in Table 14. When the latch is closed, if the

device is reset (TRSTZ is sampled LOW), the latch is reset to disable the receive channel.

BOE[1:0]

LVTTL input,

asynchronous,

internal pull-up

BIST, serial output, and receive channel enables. These inputs are passed to and through

the output enable latch when OELE = HIGH, and captured in this latch when OELE returns

LOW. These inputs are passed to and through the BIST enable latch when BISTLE = HIGH,

and captured in this latch when BISTLE returns LOW. These inputs are passed to and through

the receive channel enable latch when RXLE = HIGH, and captured in this latch when RXLE

returns LOW.

LVTTL output,

asynchronous

Link fault indication output. Active LOW. LFI is the logical OR of four internal conditions:

1. Received serial data frequency outside expected range

2. Analog amplitude below expected levels

LFI

3. Transition density lower than expected

4. Receive channel disabled.

JTAG Interface

TMS

LVTTL input,

internal pull-up

Test mode select. Used to control access to the JTAG test modes. If maintained high for >

5 TCLK cycles, the JTAG test controller is reset. The TAP controller is also reset automatically

upon application of power to the device.

TCLK

TDO

TDI

LVTTL input,

internal pull-down

JTAG test clock.

Three-state LVTTL Test data out. JTAG data output buffer which is high Z while JTAG test mode is not selected.

output

LVTTL input,

internal pull-up

Test data in. JTAG data input port.

Power

V_CC

+3.3 V power

GND

Signal and power ground for all internal circuits.

Document Number: 38-02031 Rev. *N

Page 11 of 43

CYP15G0101DXB

CYV15G0101DXB

Phase-Align Buffer

CYP(V)15G0101DXB HOTLink II Operation

Data from the input register is passed either to the encoder or to

the phase-align buffer. When the transmit path is operated

The CYP(V)15G0101DXB is a highly configurable device

designed to support reliable transfer of large quantities of data

using high-speed serial links from a single source to one or more

destinations.

synchronous

to

REFCLK

(TXCKSEL = LOW

and

TXRATE = LOW), the phase-align buffer is bypassed and data is

passed directly to the parity check and encoder block to reduce

latency.

CYP(V)15G0101DXB Transmit Data Path

When an input register clock with an uncontrolled phase

relationship to REFCLK is selected (TXCKSEL  LOW) or if data

is captured on both edges of REFCLK (TXRATE = HIGH), the

phase-align buffer is enabled. This buffer is used to absorb clock

phase differences between the presently selected input clock

and the internal character clock.

Operating Modes

The transmit path of the CYP(V)15G0101DXB supports a single

character-wide data path. This data path is used in multiple

operating modes as controlled by the TXMODE[1:0] inputs.

Input Register

Initialization of the phase-align buffer takes place when the

TXRST input is sampled LOW by two consecutive rising edges

of REFCLK. When TXRST is returned HIGH, the present input

clock phase relative to REFCLK is set. TXRST is an

asynchronous input, but is sampled internally to synchronize it to

the internal transmit path state machine.

The bits in the input register support different assignments,

based on if the character is unencoded, encoded with two control

bits, or encoded with three control bits. These assignments are

shown in Table 1.

Table 1. Input Register Bit Assignments^[9]

Once set, the input clock is allowed to skew in time up to half a

character period in either direction relative to REFCLK; that

is 180°. This time shift allows the delay path of the character

clock (relative to REFLCK) to change due to operating voltage

and temperature, while not affecting the design operation.

Encoded

Unencoded

(Encoder

Bypassed)

(Encoder Enabled)

Signal Name

Two-bit

Control

Three-bit

Control

TXD[0] (LSB)

TXD[1]

DIN[0]

DIN[1]

DIN[2]

DIN[3]

DIN[4]

DIN[5]

DIN[6]

DIN[7]

DIN[8]

DIN[9]

N/A

TXD[0]

TXD[1]

TXD[2]

TXD[3]

TXD[4]

TXD[5]

TXD[6]

TXD[7]

TXCT[0]

TXCT[1]

N/A

TXD[0]

TXD[1]

TXD[2]

TXD[3]

TXD[4]

TXD[5]

TXD[6]

TXD[7]

TXCT[0]

TXCT[1]

SCSEL

If the phase offset, between the initialized location of the input

clock and REFCLK, exceeds the skew handling capabilities of

the phase-align buffer, an error is reported on the TXPER output.

This output indicates a continuous error until the phase-align

buffer is reset. While the error remains active, the transmitter

outputs a continuous C0.7 character to indicate to the remote

receiver that an error condition is present in the link.

TXD[2]

TXD[3]

TXD[4]

TXD5]

In specific transmit modes, it is also possible to reset the

phase-align buffer with minimal disruption of the serial data

stream. When the transmit interface is configured for generation

of atomic Word Sync Sequences (TXMODE[1] = MID) and a

phase-align buffer error is present, the transmission of a Word

Sync Sequence will recenter the phase-align buffer and clear the

error condition.^[10]

TXD[6]

TXD[7]

TXCT[0]

TXCT[1] (MSB)

SCSEL

Parity Support

The input register captures a minimum of eight data bits and two

control bits on each input clock cycle. When the encoder is

bypassed, the TXCT[1:0] control bits are part of the pre-encoded

10-bit data character.

In addition to the ten data and control bits that are captured at

the transmit input register, a TXOP input is also available. This

allows the CYP(V)15G0101DXB to support ODD parity

checking. Parity checking is available for all operating modes

(including encoder bypass). The specific mode of parity checking

is controlled by the PARCTL input, and operates per Table 2.

When the encoder is enabled (TXMODE[1]  LOW), the

TXCT[1:0] bits are interpreted along with the TXD[7:0] character

to generate the specific 10-bit transmission character. When

TXMODE[0]  HIGH, an additional special character select

(SCSEL) input is also captured and interpreted. This SCSEL

input is used to modify the encoding of the characters.

When PARCTL = MID (open) and the encoder is enabled

(TXMODE[1]  LOW), only the TXD[7:0] data bits are checked

for ODD parity along with the TXOP bit. When PARCTL = HIGH

with the encoder enabled (or MID with the encoder bypassed),

the TXD[7:0] and TXCT[1:0] inputs are checked for ODD parity

along with the TXOP bit. When PARCTL = LOW, parity checking

is disabled.

Notes

9. The TXOP input is also captured in the input register, but its interpretation is under the separate control of PARCTL.

10. One or more K28.5 characters may be added or lost from the data stream during this reset operation. When used with non-Cypress devices that require a complete

16-character Word Sync Sequence for proper receive elasticity buffer alignment, it is recommend that the sequence be followed by a second Word Sync Sequence

to ensure proper operation.

Document Number: 38-02031 Rev. *N

Page 12 of 43

CYP15G0101DXB

CYV15G0101DXB

When parity checking and the encoder are both enabled

(TXMODE[1]  LOW), the detection of a parity error causes a

C0.7 character of proper disparity to be passed to the transmit

shifter. When the encoder is bypassed (TXMODE[1] = LOW),

detection of a parity error causes a positive disparity version of

a C0.7 transmission character to be passed to the transmit

shifter.

Data Encoding

Raw data, as received directly from the transmit input register, is

seldom in a form suitable for transmission across a serial link.

The characters must usually be processed or transformed to

guarantee

■ a minimum transition density (to allow the serial receive PLL to

extract a clock from the data stream)

Table 2. Input Register Bits Checked for Parity^[12]

Transmit Parity Check Mode (PARCTL)

■ a DC-balance in the signaling (to prevent baseline wander)

■ run-length limits in the serial data (to limit the bandwidth of the

link)

Signal

Name

MID

LOW

HIGH

TXMODE[1]

= LOW

TXMODE[1]

■ the remote receiver a way of determining the correct character

boundaries (framing).

 LOW

TXD[0]

TXD[1]

TXD[2]

TXD[3]

TXD[4]

TXD[5]

TXD[6]

TXD[7]

TXCT[0]

TXCT[1]

TXOP

X^[11]

X

When the encoder is enabled (TXMODE[1]  LOW), the

characters to be transmitted are converted from data or special

character codes to 10-bit transmission characters (as selected

by the TXCT[1:0] and SCSEL inputs), using an integrated

8B/10B encoder. When directed to encode the character as a

special character code, it is encoded using the special character

encoding rules listed in Table 21. When directed to encode the

character as a data character, it is encoded using the data

character encoding rules in Table 20.

X

The 8B/10B encoder is standards compliant with ANSI/NCITS

ASC X3.230-1994 (fibre channel), IEEE 802.3z (gigabit

ethernet), the IBM^ESCON^and FICON™, and digital video

broadcast (DVB-ASI) standards for data transport.

X

Many of the special character codes listed in Table 21 may be

generated by more than one input character. The

CYP(V)15G0101DXB is designed to support two independent

(but non-overlapping) special character code tables. This allows

the CYP(V)15G0101DXB to operate in mixed environments with

other Cypress HOTLink devices using the enhanced Cypress

command code set, and the reduced command sets of other

non-Cypress devices. Even when used in an environment that

normally uses non-Cypress special character codes, the

selective use of Cypress command codes can permit operation

where running disparity and error handling must be managed.

Encoder

The character, received from the input register or phase-align

buffer and parity check logic, is then passed to the encoder logic.

This block interprets each character and any control bits, and

outputs a 10-bit transmission character.

Depending on the configured operating mode, the generated

transmission character may be

■ the 10-bit pre-encoded character accepted in the input register

■ the 10-bit equivalent of the eight-bit data character accepted in

the input register

Following conversion of each input character from eight bits to a

10-bit transmission character, it is passed to the transmit shifter

and is shifted out LSB first, as required by ANSI and IEEE

standards for 8B/10B coded serial data streams.

■ the 10-bit equivalent of the eight -bit special character code

accepted in the input register

Transmit Modes

■ the 10-bit equivalent of the C0.7 SVS character if parity

checking was enabled and a parity error was detected

The operating mode of the transmit path is set through the

TXMODE[1:0] inputs. These 3-level select inputs allow one of

nine transmit modes to be selected. The transmit modes are

listed in Table 3.

■ the 10-bit equivalent of the C0.7 SVS character if a phase-align

buffer overflow or underflow error is present

■ a character that is part of the 511-character BIST sequence

The encoded modes (TX modes 3 through 8) support multiple

encoding tables. These encoding tables vary by the specific

combinations of SCSEL, TXCT[1], and TXCT[0] that are used to

control the generation of data and control characters. These

multiple encoding forms allow maximum flexibility in interfacing

to legacy applications, while also supporting numerous

extensions in capabilities.TX Mode 0—encoder bypass

■ a K28.5 character generated as an individual character or as

part of the 16-character Word Sync Sequence.

The selection of the specific characters generated are controlled

by the TXMODE[1:0], SCSEL, TXCT[1:0], and TXD[7:0] inputs

for each character.

Notes

11. Bits marked as X are XORed together. Result must be a logic-1 for parity to be valid.

12. Transmit path parity errors are reported on the TXPER output.

Document Number: 38-02031 Rev. *N

Page 13 of 43

CYP15G0101DXB

CYV15G0101DXB

When the encoder is bypassed, the character captured from the

TXD[7:0] and TXCT[1:0] inputs is passed directly to the transmit

shifter without modification. If parity checking is enabled

(PARCTL  LOW) and a parity error is detected, the 10-bit

character is replaced with the 1001111000 pattern (+C0.7

character) regardless of the running disparity of the previous

character.

TX Modes 1 and 2—Factory Test Modes

These modes enable specific factory test configurations. They

are not considered normal operating modes of the device. Entry

or configuration into these test modes will not damage the

device.

TX Mode 3—Atomic Word Sync and SCSEL Control of Special

Codes

With the encoder bypassed, the TXCT[1:0] inputs are considered

part of the data character and do not perform a control function

that would otherwise modify the interpretation of the TXD[7:0]

bits. The bit usage and mapping of these control bits when the

encoder is bypassed is shown in Table 4.

When configured in TX Mode 3, the SCSEL input is captured

along with the TXCT[1:0] data control inputs. These bits combine

to control the interpretation of the TXD[7:0] bits and the

characters generated by them. These bits are interpreted as

listed in Table 5.

In encoder bypass mode, the SCSEL input is ignored. All

clocking modes interpret the data in the same way.

Table 5. TX Modes 3 and 6 Encoding

Table 3. Transmit Operating Modes

TX Mode

Operating Mode

Characters Generated

Word Sync

Sequence

Support

SCSEL

TXCT Function

X

0

1

X

0

1

0

1

Encoded data character

K28.5 fill character

Control

None

0

1

2

3

LL None

LM None

Encoder bypass

Reserved for test

Encoder control

Special character code

None

16-character Word Sync Sequence

LH None

When TXCKSEL = MID or HIGH, the transmit channel captures

data into its input register using the TXCLK clock.

ML Atomic

Special

Character

Word Sync Sequence

4

5

6

MM Atomic

MH Atomic

Word Sync Encoder control

When TXCT[1:0] = 11, a 16-character sequence of K28.5

characters, known as a Word Sync Sequence, is generated on

the transmit channel. This sequence of K28.5 characters may

start with either a positive or negative disparity K28.5 (as

determined by the current running disparity and the 8B/10B

coding rules). The disparity of the second and third K28.5

characters in this sequence are reversed from what normal

8B/10B coding rules would generate. The remaining K28.5

characters in the sequence follow all 8B/10B coding rules. The

disparity of the generated K28.5 characters in this sequence

follow a pattern of either + + – – + – + – + – + – + – + – or

– – + + – + – + – + – + – + – +.

None

Encoder control

HL Interruptible Special

Character

7

8

HM Interruptible Word Sync Encoder control

HH Interruptible None Encoder control

Table 4. Encoder Bypass Mode (TXMODE[1:0] = LL)

When TXMODE[1] = MID (open, TX modes 3, 4 and 5), the

generation of this character sequence is an atomic

(non-interruptible) operation. Once it has been successfully

started, it cannot be stopped until all 16 characters have been

generated. The content of the input register is ignored for the

duration of this 16-character sequence. At the end of this

sequence, if the TXCT[1:0] = 11 condition is sampled again, the

sequence restarts and remains uninterrupted for the following 15

character clocks.

Signal Name

Bus Weight

10B Name

[13]

TXD[0] (LSB)

TXD[1]

2⁰

2¹

2²

2³

2⁴

2⁵

2⁶

2⁷

2⁸

2⁹

a

b

c

d

e

i

TXD[2]

TXD[3]

TXD[4]

TXD[5]

If parity checking is enabled, the character used to start the Word

Sync Sequence must also have correct ODD parity. This is true

even though the contents of the TXD[7:0] bits do not directly

control the generation of characters during the Word Sync

Sequence. Once the sequence is started, parity is not checked

on the following 15 characters in the Word Sync Sequence.

TXD[6]

f

TXD[7]

g

h

j

TXCT[0]

TXCT[1] (MSB)

Note

13. LSB is shifted out first.

Document Number: 38-02031 Rev. *N

Page 14 of 43

CYP15G0101DXB

CYV15G0101DXB

When TXMODE[1] = HIGH (TX modes 6, 7, and 8), the

generation of the Word Sync Sequence becomes an interruptible

operation. In TX Mode 6, this sequence is started as soon as the

TXCT[1:0] = 11 condition is detected on the channel. In order for

the sequence to continue, the TXCT[1:0] inputs must be sampled

as 00 for the remaining 15 characters of the sequence. If at any

time a sample period exists where TXCT[1:0]  00, the Word

Sync Sequence is terminated, and a character representing the

data and control bits is generated by the encoder. This resets the

Word Sync Sequence state machine such that it will start at the

beginning of the sequence at the next occurrence of

TXCT[1:0] = 11.

TX Mode 5—Atomic Word Sync, No SCSEL

When configured in TX Mode 5, the SCSEL signal is not used.

The TXCT[1:0] inputs control the characters generated by the

channel. The specific characters generated by these bits are

listed in Table 7.

Table 7. TX Modes 5 and 8 Encoding

Characters Generated

When parity checking is enabled and TXMODE[1] = HIGH, all

characters (including those in the middle of a Word Sync

Sequence) must have correct parity. The detection of a character

with incorrect parity during a Word Sync Sequence (regardless

of the state of TXCT[1:0]) will interrupt that sequence and force

generation of a C0.7 SVS character. Any interruption of the Word

Sync Sequence causes the sequence to terminate.

X

0

1

0

1

0

1

Encoded data character

K28.5 fill character

Special character code

16-character Word Sync Sequence

When TXCKSEL = LOW, the input register for the transmit

channel is clocked by REFCLK.^[14]When TXCKSEL = HIGH or

MID, the input register for the transmit channel is clocked with

TXCLK.

TX Mode 5 also has the capability of generating an Atomic Word

Sync Sequence. For the sequence to be started, the TXCT[1:0]

inputs must both be sampled HIGH. The generation and

operation of this Word Sync Sequence is the same as that

documented for TX Mode 3.

TX Mode 4—Atomic Word Sync and SCSEL Control of

Word Sync Sequence Generation

Transmit BIST

When configured in TX Mode 4, the SCSEL input is captured

along with the TXCT[1:0] data control inputs. These bits combine

to control the interpretation of the TXD[7:0] bits and the

characters generated by them. These bits are interpreted as

listed in Table 6.

The transmit channel contains an internal pattern generator that

can be used to validate both device and link operation. This

generator is enabled by the BOE[1] signal, as listed in Table 8

(when the BISTLE latch enable input is HIGH). When enabled,

a register in the transmit channel becomes a signature pattern

generator by logically converting to a linear feedback shift

Table 6. TX Modes 4 and 7 Encoding

register (LFSR). This LFSR generates

a 511-character

sequence that includes all data and special character codes,

including the explicit violation symbols. This provides a

predictable yet pseudo-random sequence that can be matched

to an identical LFSR in the attached Receiver. If the receive

channel is configured for REFCLK clocking (RXCKSEL = LOW),

each pass is preceded by a 16-character Word Sync Sequence

to allow elasticity buffer alignment and management of

clock-frequency variations.

Characters Generated

X

0

1

X

0

1

X

0

1

Encoded data character

K28.5 fill character

Special character code

When the BISTLE signal is HIGH, if the BOE[1] input is LOW, the

BIST generator in the transmit channel is enabled (and if

BOE[0] = LOW the BIST checker in the receive channel is

enabled). When BISTLE returns LOW, the values of the

BOE[1:0] signals are captured in the BIST enable latch. These

values remain in the BIST enable latch until BISTLE is returned

high to open the latch again. A device reset (TRSTZ sampled

LOW), also presets the BIST enable latch to disable BIST on

both the transmit and receive channels.

16-character Word Sync Sequence

TX Mode 4 also supports an Atomic Word Sync Sequence.

Unlike TX Mode 3, this sequence is started when both SCSEL

and TXCT[0] are sampled HIGH. With the exception of the

combination of control bits used to initiate the sequence, the

generation and operation of this Word Sync Sequence is the

same as that documented for TX Mode 3.

All data and data-control information present at the TXD[7:0] and

TXCT[1:0] inputs are ignored when BIST is active on the transmit

channel.

Note

14. When REFCLK is configured for half-rate operation (TXRATE = HIGH), this input is sampled (or the outputs change) relative to both the rising and falling edges of

REFCLK.

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CYP15G0101DXB

CYV15G0101DXB

When TXRATE=HIGH, configuring TXCKSEL = HIGH or MID is

an invalid mode of operation.

SPDSEL is a 3-level select^[15](ternary) input that selects one of

three operating ranges for the serial data outputs and inputs. The

operating serial signaling-rate and allowable range of REFCLK

frequencies are listed in Table 9.

Serial Output Drivers

The serial interface output drivers use high-performance

differential current mode logic (CML) to provide source-matched

drivers for the transmission lines. These serial drivers accept

data from the transmit shifter. These outputs have signal swings

equivalent to that of standard PECL drivers, and are capable of

driving AC-coupled optical modules or AC-coupled transmission

lines.

Table 9. Operating Speed Settings

REFCLK

Frequency

(MHz)

When configured for local loop-back (LPEN = HIGH), the

enabled serial drivers are configured to drive a static differential

logic-1.

Signaling Rate

SPDSEL

TXRATE

(MBaud)

LOW

1

0

1

0

1

0

Reserved

19.5–40

20–40

195–400

Each serial driver can be enabled or disabled through the

BOE[1:0] inputs, as controlled by the OELE latch-enable signal.

When OELE = HIGH, the signals present on the BOE[1:0] inputs

are passed through the serial output enable latch to control the

serial driver. The BOE[1:0] input with OUT1 and OUT2driver

is listed in Table 8.

MID (Open)

HIGH

400–800

40–80

40–75

800–1500

80–150

Table 8. Output Enable, BIST, and Receive Channel Enable

Signal Map

The REFCLK input is a differential input with each input

internally biased to 1.4 V. If the REFCLK+ input is connected to

a TTL, LVTTL, or LVCMOS clock source, the input signal is

recognized when it passes through the internally biased

reference point.

BIST

ReceivePLL

Channel

Enable

Output

Controlled

(OELE)

Channel

Enable

BOE Input

(BISTLE)

(RXLE)

BOE[1]

BOE[0]

OUT2

OUT1

Transmit

Receive

X

When both the REFCLK+ and REFCLK inputs are connected,

the clock source must be a differential clock. This can be either

a differential LVPECL clock that is DC- or AC-coupled, or a

differential LVTTL or LVCMOS clock.

Receive

When OELE = HIGH and BOE[x] = HIGH, the associated serial

driver is enabled to drive any attached transmission line. When

OELE = HIGH and BOE[x] = LOW, the associated driver is

disabled and internally configured for minimum power

dissipation. If both serial drivers for the channel are disabled, the

internal logic for the transmit channel is also configured for

lowest power operation. When OELE returns LOW, the values

present on the BOE[1:0] inputs are latched in the output enable

latch, and remain there until OELE returns HIGH to open the

latch again. A device reset (TRSTZ sampled LOW) clears this

latch and disables both serial drivers.

By connecting the REFCLK input to an external voltage source

or resistive voltage divider, it is possible to adjust the reference

point of the REFCLK+ input for alternate logic levels. When doing

so, it is necessary to ensure that the 0 V-differential crossing

point remains within the parametric range supported by the input.

CYP(V)15G0101DXB Receive Data Path

Serial Line Receivers

Two differential line receivers, IN1and IN2, are available for

accepting serial data streams. The active serial line receiver is

selected using the INSEL input. Both serial line receivers have

differential inputs, and can accommodate wire interconnect and

filtering losses or transmission line attenuation greater than

16 dB. For normal operation, these inputs should receive a

signal of at least V_DIFFS> 100 mV, or 200-mV peak-to-peak

differential. Each line receiver can be DC- or AC-coupled to

+3.3 V powered fiber-optic interface modules (any ECL/PECL

logic family, not limited to 100 K PECL) or AC-coupled to

+5 V-powered optical modules. The common-mode tolerance of

the receivers accommodates a wide range of signal termination

voltages. Each receiver provides internal DC-restoration, to the

center of the receiver’s common mode range, for AC-coupled

signals.

Note. When both serial output drivers are disabled and a driver

is re-enabled, the data on the serial drivers may not meet all

timing specifications for up to 200 µs.

Transmit PLL Clock Multiplier

The transmit PLL clock multiplier accepts a character-rate or

half-character-rate external clock at the REFCLK input, and

multiples that clock by 10 or 20 (as selected by TXRATE) to

generate a bit-rate clock for use by the transmit shifter. It also

provides a character-rate clock used by the transmit path.

This clock multiplier PLL can accept a REFCLK input between

19.5 MHz and 150 MHz, however, this clock range is limited by

the operating mode of the CYP(V)15G0101DXB clock multiplier

(controlled by TXRATE) and by the level on the SPDSEL input.

Note

15. When REFCLK is configured for half-rate operation (TXRATE = HIGH), this input is sampled (or the outputs change) relative to both the rising and falling edges of

REFCLK.

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CYP15G0101DXB

CYV15G0101DXB

The local loop-back input (LPEN) allows the serial transmit data

to be routed internally back to the clock and data recovery circuit.

When configured for local loop-back, the transmit serial driver

outputs are forced to output a differential logic-1. This prevents

local diagnostic patterns from being broadcast to attached

remote receivers.

Range Control

The clock/data recovery (CDR) circuit includes logic to monitor

the frequency of the phase-locked loop (PLL) voltage controlled

oscillator (VCO) used to sample the incoming data stream. This

logic ensures that the VCO operates at, or near the rate of the

incoming data stream for two primary cases:

Signal Detect/Link Fault

■ when the incoming data stream resumes after a time in which

it has been “missing.”

Each selected line receiver (i.e., that routed to the clock and data

recovery PLL) is simultaneously monitored for

■ when the incoming data stream is outside the acceptable

frequency range.

■ analog amplitude above limit specified by SDASEL

■ transition density greater than specified limit

To perform this function, the frequency of the VCO is periodically

sampled and compared to the frequency of the REFCLK input. If

the VCO is running at a frequency beyond +1500 ppm^[16]as

defined by the reference clock frequency, it is periodically forced

to the correct frequency (as defined by REFCLK, SPDSEL, and

TXRATE) and then released in an attempt to lock to the input

data stream. The sampling and relock period of the range control

is calculated as follows: RANGE CONTROL SAMPLING

PERIOD = (REFCLKPERIOD) × (16000).

■ range controller reports the received data stream within normal

frequency range (±1500 ppm)^[16]

■ receive channel enabled.

All of these conditions must be valid for the signal detect block

to indicate a valid signal is present. This status is presented on

the LFI (link fault indicator) output.

During the time that the range control forces the PLL VCO to run

at REFCLK × 10 (or REFCLK × 20 when TXRATE = HIGH) rate,

the LFIx output will be asserted LOW. While the PLL is

attempting to re-lock to the incoming data stream, LFIx may be

either HIGH or LOW (depending on other factors such as

transition density and amplitude detection) and the recovered

byte clock (RXCLK) may run at an incorrect rate (depending on

the quality or existence of the input serial data stream). After a

valid serial data stream is applied, it may take up to one RANGE

CONTROL SAMPLING PERIOD before the PLL locks to the

input data stream, after which LFIx should be HIGH.

Analog Amplitude

While most signal monitors are based on fixed constants, the

analog amplitude level detection is adjustable to allow operation

with highly attenuated signals, or in high-noise environments.

This adjustment is made through the SDASEL signal, a 3-level

select^[17](ternary) input, which sets the trip point for the detection

of a valid signal at one of three levels, as listed in Table 10.

The analog signal detect monitor is active for the present line

receiver, as selected by the INSEL input. When configured for

local loop-back (LPEN = HIGH), the analog signal detect monitor

is disabled.

Receive Channel Enabled

Transition Density

The CYP(V)15G0101DXB receive channel can be enabled and

disabled through the BOE[0] input, as controlled by the RXLE

latch-enable signal. When RXLE = HIGH, the signal present on

the BOE[0] input is passed through the receive channel enable

latch to control the PLL and logic of the receive channel. The

BOE[1:0] input functions are listed in Table 8.

The transition detection logic checks for the absence of any

transitions spanning greater than six transmission characters

(60-bits). If no transitions are present in the data received (within

the referenced period), the transition detection logic asserts LFI.

The LFI output remains asserted until at least one transition is

detected in each of three adjacent received characters.

When RXLE = HIGH and BOE[0] = HIGH, the receive channel is

enabled to receive and recover a serial stream from the line

receiver. When RXLE = HIGH and BOE[0] = LOW, the receive

channel is disabled and internally configured for minimum power

dissipation. When disabled, the channel indicates a constant LFI

output. When RXLE returns LOW, the values present on the

BOE[1:0] inputs are latched in the Receive Channel Enable

Latch, and remain there until RXLE returns HIGH to open the

latch again.^[19]

Table 10. Analog Amplitude Detect Valid Signal Levels^[18]

Typical Signal with Peak Amplitudes

SDASEL

Above

LOW

MID (Open) 280-mV p-p differential

HIGH 420-mV p-p differential

140-mV p-p differential

Notes

16. REFCLK has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time. REFCLK

must be within ±1500 PPM (±0.15%) of the remote transmitter’s PLL reference (REFCLK) frequency. Although transmitting to a HOTLink II receiver necessitates the

frequency difference between the transmitter and receiver reference clocks to be within ±1500-PPM, the stability of the crystal needs to be within the limits specified

by the appropriate standard when transmitting to a remote receiver that is compliant to that standard. For example, to be IEEE 802.3z Gigabit Ethernet compliant,

the frequency stability of the crystal needs to be within ±100 PPM.

17. When REFCLK is configured for half-rate operation (TXRATE = HIGH), this input is sampled (or the outputs change) relative to both the rising and falling edges of

REFCLK.

18. The peak amplitudes listed in this table are for typical waveforms that have generally 3–4 transitions for every ten bits. In a worse case environment the signals may

have a sign-wave appearance (highest transition density with repeating 0101...). Signal peak amplitudes levels within this environment type could increase the values

in the table above by approximately 100 mV.

19. When a disabled receive channel is reenabled, the status of the LFI output and data on the parallel outputs may be indeterminate for up to 2 ms.

Document Number: 38-02031 Rev. *N

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CYP15G0101DXB

CYV15G0101DXB

Framing Character

Clock/Data Recovery

The CYP(V)15G0101DXB allows selection of two combinations

of framing characters to support requirements of different

interfaces. The selection of the framing character is made

through the FRAMCHAR input.

The extraction of a bit-rate clock and recovery of bits from a

received serial stream is performed by a CDR block within the

receive channel. The clock extraction function is performed by a

high-performance embedded PLL that tracks the frequency of

the transitions in the incoming bit stream and aligns the phase of

the internal bit-rate clock to the transitions in the serial data

stream.

The specific bit combinations of these framing characters are

listed in Table 11. When the specific bit combination of the

selected framing character is detected by the framer, the

boundaries of the characters present in the received data stream

are known.

The CDR accepts

half-character-rate (bit-rate  20) reference clock from the

a

character-rate (bit-rate  10) or

REFCLK input. This REFCLK input is used to

Table 11. Framing Character Selector

■ ensure that the VCO (within the CDR) is operating at the correct

frequency

Bits Detected in Framer

FRAMCHAR

Character Name

Bits Detected

■ reduce PLL acquisition time

LOW

Reserved for test

■ limit unlocked frequency excursions of the CDR VCO when

there is no input data present at the selected serial line receiver.

MID (Open)

Comma+

Comma–

00111110XX^[21]

or 11000001XX

Regardless of the type of signal present, the CDR will attempt to

recover a data stream from it. If the frequency of the recovered

data stream is outside the limits of the range control monitor, the

CDR will switch to track REFCLK instead of the data stream.

Once the CDR output (RXCLK) frequency returns back close to

REFCLK frequency, the CDR input will be switched back to track

the input data stream. In case no data is present at the input, this

switching behavior may result in brief RXCLK frequency

excursions from REFCLK. However, the validity of the input data

stream is indicated by the LFIx output. The frequency of

REFCLK is required to be within  1500 ppm^[20]of the frequency

of the clock that drives the REFCLK input of the remote

transmitter to ensure a lock to the incoming data stream.

HIGH

–K28.5

K28.5

0011111010 or

1100000101

Framer

The framer operates in one of three different modes, as selected

by the RFMODE input. In addition, the framer itself may be

enabled or disabled through the RFEN input. When

RFEN = LOW, the framer is disabled, and no combination of bits

in a received data stream will alter the character boundaries.

When RFEN = HIGH, the framer-mode selected by RFMODE is

enabled.

For systems using multiple or redundant connections, the LFI

output can be used to select an alternate data stream. When an

LFI indication is detected, external logic can toggle selection of

the IN1 and IN2 inputs through the INSEL input. When a port

switch takes place, it is necessary for the receive PLL to

reacquire the new serial stream and frame to the incoming

character boundaries.

When RFMODE = LOW, the low-latency framer is selected. This

framer operates by stretching the recovered character clock until

it aligns with the received character boundaries. In this mode, the

framer starts its alignment process on the first detection of the

selected framing character. To reduce the impact on external

circuits that make use of a recovered clock, the clock period is

not stretched by more than two bit-periods in any one clock cycle.

When operated with

a

character-rate output clock

Deserializer/Framer

(RXRATE = LOW), the output of properly framed characters may

be delayed by up to nine character-clock cycles from the

detection of the selected framing character. When operated with

a half-character-rate output clock (RXRATE = HIGH), the output

of properly framed characters may be delayed by up to 14

character-clock cycles from the detection of the selected framing

character.^[22]

Each CDR circuit extracts bits from the serial data stream and

clocks these bits into the shifter/framer at the bit-clock rate.

When enabled, the framer examines the data stream, looking for

one or more comma or K28.5 characters at all possible bit

positions. The location of these characters in the data stream are

used to determine the character boundaries of all following

characters.

Notes

20. REFCLK has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time. REFCLK

must be within ±1500 ppm (±0.15%) of the remote transmitter’s PLL reference (REFCLK) frequency. Although transmitting to a HOTLink II receiver necessitates the

frequency difference between the transmitter and receiver reference clocks to be within ±1500 ppm, the stability of the crystal needs to be within the limits specified

by the appropriate standard when transmitting to a remote receiver that is compliant to that standard. For example, to be IEEE 802.3z Gigabit Ethernet compliant,

the frequency stability of the crystal needs to be within ±100 ppm.

21. The standard definition of a Comma contains only seven bits. However, since all valid Comma characters within the 8B/10B character set also have the 8th bit as

an inversion of the 7th bit, the compare pattern is extended to a full eight bits to reduce the possibility of a framing error.

22. When receive BIST is enabled on a channel, the low-latency framer must not be enabled. The BIST sequence contains an aliased K28.5 framing character, which

would cause the receiver to update its character boundaries incorrectly.

Document Number: 38-02031 Rev. *N

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CYP15G0101DXB

CYV15G0101DXB

When RFMODE = MID (open), the Cypress-mode multi-byte

framer is selected. The required detection of multiple framing

characters makes the link much more robust to incorrect framing

due to aliased framing characters in the data stream. In this

mode, the framer does not adjust the character clock boundary,

but instead aligns the character to the already recovered

character clock. This ensures that the recovered clock does not

contain any significant phase changes or hops during normal

operation or framing, and allows the recovered clock to be

replicated and distributed to other external circuits or

components using PLL-based clock distribution elements. In this

framing mode, the character boundaries are only adjusted if the

selected framing character is detected at least twice within a

span of 50-bits, with both instances on identical 10-bit character

boundaries.

When DECMODE = MID (or open), the 10-bit transmission

characters are decoded using Table 20 and Table 21. Received

special code characters are decoded using the Cypress column

of Table 21.

When DECMODE = HIGH, the 10-bit transmission characters

are decoded using Table 20 and Table 21. Received special

code characters are decoded using the alternate column of

Table 21.

Receive BIST Operation

The receiver interface contains an internal pattern generator that

can be used to validate both device and link operation. This

generator is enabled by the BOE[0] signal as listed in Table 8

(when the BISTLE latch enable input is HIGH). When enabled,

a register in the receive channel becomes a pattern generator

and checker by logically converting to a linear feedback shift

When RFMODE = HIGH, the alternate-mode multi-byte framer

is enabled. Like the Cypress-mode multi-byte framer, multiple

framing characters must be detected before the character

boundary is adjusted. In this mode, the framer does not adjust

the character clock boundary, but instead aligns the character to

the already recovered character clock. In this mode, the data

stream must contain a minimum of four of the selected framing

characters, received as consecutive characters, on identical

10-bit boundaries, before character framing is adjusted.

register (LFSR). This LFSR generates

a 511-character

sequence that includes all data and special character codes,

including the explicit violation symbols. This provides a

predictable yet pseudo-random sequence that can be matched

to an identical LFSR in the attached transmitter. If the receive

channels

are

configured

for

REFCLK

clocking

(RXCKSEL  LOW), each pass is preceded by a 16-character

Word Sync Sequence.

Framing is enabled when RFEN = HIGH. If RFEN = LOW, the

framer is disabled. When the framer is disabled, no changes are

made to the recovered character boundary, regardless of the

presence of framing characters in the data stream.

When synchronized with the received data stream, the receiver

checks each character in the decoder with each character

generated by the LFSR and indicates compare errors and BIST

status at the RXST[2:0] bits of the output register.

When the BISTLE signal is HIGH, if the BOE[0] input is LOW the

BIST generator/checker in the receive channel is enabled (and

if BOE[1] = LOW the BIST generator in the transmit channel is

enabled). When BISTLE returns LOW, the values of the

BOE[1:0] signals are captured in the BIST enable latch. These

values remain in the BIST enable latch until BISTLE is returned

high to open the latch again. All captured signals in the BIST

enable latch are set HIGH (i.e., BIST is disabled) following a

device reset (TRSTZ is sampled LOW).

10B/8B Decoder Block

The decoder logic block performs three primary functions:

■ decoding the received transmission characters back into data

and special character codes

■ comparing generated BIST patterns with received characters

to permit at-speed link and device testing

■ generation of ODD parity on the decoded characters.

When BIST is first recognized as being enabled in the receiver,

the LFSR is preset to the BIST-loop start-code of D0.0. This D0.0

character is sent only once per BIST loop. The status of the BIST

progress and any character mismatches is presented on the

RXST[2:0] status outputs.

10B/8B Decoder

The framed parallel output of the deserializer shifter is passed to

the 10B/8B decoder where, if the decoder is enabled

(DECMODE  LOW), it is transformed from a 10-bit transmission

character back to the original data and special character codes.

This block uses the 10B/8B decoder patterns in Table 20 and

Table 21 of this data sheet. Valid data characters are indicated

by a 000b bit-combination on the RXST[2:0] status bits, and

special character codes are indicated by a 001b bit-combination

on these same status outputs. Framing characters, invalid

patterns, disparity errors, and synchronization status are

presented as alternate combinations of these status bits.

Code rule violations or running disparity errors that occur as part

of the BIST loop do not cause an error indication. RXST[2:0]

indicates 010b or 100b for one character period per BIST loop to

indicate loop completion. This status can be used to check test

pattern progress. These same status values are presented when

the decoder is bypassed and BIST is enabled on the receive

channel.

The status reported on RXST[2:0] by the BIST state machine are

listed in Table 16. When receive BIST is enabled, the same

status is reported on the receive status outputs regardless of the

state of DECMODE.

The 10B/8B decoder operates in two normal modes, and can

also be bypassed. The operating mode for the decoder is

controlled by the DECMODE input.

When DECMODE = LOW, the decoder is bypassed and raw

10-bit characters are passed to the output register. In this mode,

the receive elasticity buffers are bypassed, and RXCKSEL must

be MID.

The specific patterns checked by each receiver are described in

detail in the Cypress application note HOTLink Built-In Self-test.

The sequence compared by the CYP(V)15G0101DXB is

identical to that in the CY7B933 and CY7C924DX, allowing

interoperable systems to be built when used at compatible serial

signaling rates.

Document Number: 38-02031 Rev. *N

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CYP15G0101DXB

CYV15G0101DXB

If the number of invalid characters received ever exceeds the

number of valid characters by 16, the receive BIST state

machine aborts the compare operations and resets the LFSR to

the D0.0 state to look for the start of the BIST sequence again.

also be centered by a device reset operation initiated through the

TRSTZ input. However, following such an event, the

CYP(V)15G0101DXB will normally require a framing event

before it will correctly decode characters.

When the receive paths are configured for REFCLK clocking

(RXCKSEL = LOW), each pass must be preceded by a

16-character Word Sync Sequence to allow output buffer

alignment and management of clock frequency variations. This

is automatically generated by the transmitter when its local

RXCKSEL = LOW.

Receive Modes

The operating mode of the receive path is set through the

RXMODE input. The ‘Reserved for test’ setting (RXMODE = M)

is not allowed, even if the receiver is not being used, as it will

stop normal function of the device. When the decoder is

disabled, the RXMODE setting is ignored as long as it is not a

test mode. These modes determine the RXST status reporting.

The different receive modes are listed in Table 12.

The BIST state machine requires the characters to be correctly

framed for it to detect the BIST sequence. If the low-latency

framer is enabled (RFMODE = LOW), the framer will misalign to

an aliased framing character within the BIST sequence. If the

alternate-mode multi-byte framer is enabled (RFMODE = HIGH)

and the receiver outputs are clocked relative to a recovered clock

(RXCKSEL  MID), it is necessary to frame the receiver before

BIST is enabled. If the receiver outputs are clocked relative to

REFCLK (RXCKSEL = LOW), the transmitter precedes every

511 character BIST sequence with a 16-character Word Sync

Sequence.

Table 12. Receive Operating Modes

RX Mode

Mode

Number

RXMODE

RXST Status Reporting

Status A

Reserved for test

Status B

0

1

2

L

M

H

Receive Elasticity Buffer

Power Control

The receive channel contains an elasticity buffer that is designed

to support multiple clocking modes. This buffer allows data to be

read using an elasticity buffer read-clock that is asynchronous in

both frequency and phase from the elasticity buffer write clock,

or to use a read clock that is frequency coherent but with uncon-

trolled phase relative to the elasticity buffer write clock.

The CYP(V)15G0101DXB supports user control of the powered

up or down state of the transmit and receive channel. The

receive channel is controlled by the RXLE signal and the values

present on the BOE[1:0] bus. The transmit channel is controlled

by the OELE signal and the values present on the BOE[1:0] bus.

If either the transmit or the receive channel is not used, then

powering down the unused channel will save power and reduce

system heat generation. Controlling system power dissipation

will improve the system performance.

The elasticity buffer is 10 characters deep, and supports a

12-bit-wide data path. It is capable of supporting a decoded

character, three status bits, and a parity bit for each character

present in the buffer. The write clock for this buffer is always the

recovered clock for the read channel.

Receive Channel

When RXLE = HIGH, the signal on the BOE[0] input directly

controls the power enable for the receive PLL and the analog

circuit. When BOE[0] = HIGH, the receive channel and its analog

circuits are active. When BOE[0] = LOW, the receive channel

and its analog circuits are powered down. When RXLE returns

LOW, the values present on the BOE[1:0] inputs are latched in

the receive channel enable latch. When a disabled receive

channel is re-enabled, the status of the LFI output and data on

the parallel outputs for the receive channel may be indeterminate

for up to 2 ms.

The read clock for the elasticity buffer can be set to

character-rate REFCLK (RXCKSEL = LOW and DECMODE 

LOW). The write clock for the elasticity buffer is always

recovered clock.

When RXCKSEL = LOW, the receive channel is clocked by

REFCLK. The RXCLK and RXCLKC+ outputs present buffered

and delayed forms of REFCLK. In this mode, the receive

elasticity buffer is enabled. For REFCLK clocking, the elasticity

buffer must be able to insert K28.5 characters and delete framing

characters as appropriate. The elasticity buffer is bypassed

whenever the decoder is bypassed (DECMODE = LOW). When

the decoder and elasticity buffer are bypassed, RXCKSELx must

be set to MID. When RXCKSEL = MID (or open), the receive

channel output register is clocked by the recovered clock.

Transmit Channel

When OELE = HIGH, the signals on the BOE[1:0] inputs directly

control the power enables for the serial drivers. When a BOE[1:0]

input is HIGH, the associated serial driver is enabled. When a

BOE[1:0] input is LOW, the associated serial driver is disabled.

When both serial drivers are powered down, the logic in the

entire transmit channel is also powered down. When OELE

returns LOW, the values present on the BOE[1:0] inputs are

latched in the output enable latch.

The insertion of a K28.5 or deletion of a framing character can

occur at any time. However, the actual timing on these insertions

and deletions is controlled in part by the how the transmitter

sends its data. Insertion of a K28.5 character can only occur

when the receiver has a framing character in the elasticity buffer.

Likewise, to delete a framing character, one must also be present

in the elasticity buffer. To prevent an elasticity buffer overflow or

underflow in the receive channel, a minimum density of framing

characters must be present in the received data stream.

Device Reset State

When the CYP(V)15G0101DXB is reset by assertion of TRSTZ,

both the transmit enable and receive enable latches are cleared,

and the BIST enable latch is preset. In this state, the transmit and

receive channels are disabled, and BIST is disabled.

Prior to reception of valid data, at least one Word Sync Sequence

(or at least four framing characters) must be received to allow the

receive elasticity buffer to be centered. The elasticity buffer may

Document Number: 38-02031 Rev. *N

Page 20 of 43

CYP15G0101DXB

CYV15G0101DXB

Following a device reset, it is necessary to enable the transmit

and receive channels for normal operation. This can be done by

sequencing the appropriate values on the BOE[1:0] inputs while

the OELE and RXLE signals are raised and lowered. For

systems that do not require dynamic control of power, or want

the part to power-up in a fixed configuration, it is also possible to

strap the RXLE and OELE control signals HIGH to permanently

enable their associated latches. Connection of the associated

BOE[1:0] signals to a stable HIGH will then enable the transmit

and receive channels as soon as the TRSTZ signal is

deasserted.

character in the output register is one of the selected framing

characters. The bit usage and mapping of the external signals to

the raw 10B transmission character is shown in Table 14.

Table 14. Decoder Bypass Mode (DECMODE = LOW)

Signal Name

RXST[2] (LSB)

RXST[1]

RXST[0]

RXD[0]

Bus Weight

10B Name

COMDET

2⁰

2¹

2²

2³

2⁴

2⁵

2⁶

2⁷

2⁸

2⁹

a

b

c

d

e

i

Output Bus

RXD[1]

The receive channel presents a 12-signal output bus consisting

of

RXD[2]

RXD[3]

■ an eight-bit data bus

■ a three-bit status bus

■ a parity bit.

RXD[4]

f

RXD[5]

g

h

j

RXD[6]

The bit assignments of the Data and Status are dependent on the

setting of DECMODE. This mapping is shown in Table 13.

RXD[7] (MSB)

Table 13. Output Register Bit Assignments^[23]

The COMDET output is HIGH when the character in the output

register contains the selected framing character at the proper

character boundary, and LOW for all other bit combinations.

DECMODE = MID

Signal Name

DECMODE = LOW

or HIGH

RXST[2]

RXST[1]

RXST[0]

RXD[0]

RXD[1]

RXD[2]

RXD[3]

RXD[4]

RXD[5]

RXD[6]

RXD[7]

When the low-latency framer and half-rate receive port clocking

is also enabled (RFMODE = LOW, RXRATE = HIGH, and

RXCKSEL = MID), the framer will stretch the recovered clock to

the nearest 20-bit boundary such that the rising edge of RXCLK+

occurs when COMDET = HIGH in the output register.

RXST[2] (LSB)

RXST[1]

RXST[0]

RXD[0]

COMDET

DOUT[0]

DOUT[1]

DOUT[2]

DOUT[3]

DOUT[4]

DOUT[5]

DOUT[6]

DOUT[7]

DOUT[8]

DOUT[9]

RXD[1]

RXD[2]

RXD[3]

RXD[4]

RXD[5]

RXD[6]

When the Cypress or alternate-mode framer is enabled and

half-rate receive port clocking is also enabled (RFMODE  LOW

and RXRATE = HIGH), the output clock is not modified when

framing is detected, but a single pipeline stage may be added or

subtracted from the data stream by the framer logic such that the

rising edge of RXCLK+ occurs when COMDET = HIGH in the

output register. This adjustment only occurs when the framer is

enabled (RFEN = HIGH). When the framer is disabled, the clock

boundaries are not adjusted, and COMDET may be asserted

during the rising edge of RXCLK– (if an odd number of

characters were received following the initial framing).

RXD[7] (MSB)

When the 10B/8B decoder is bypassed (DECMODE = LOW),

the framed 10-bit character is presented to the receiver output

register, along with a status output (COMDET) indicating if the

Note

23. The RXOP output is also driven from the Output Register, but its interpretation is under the separate control of PARCTL.

Document Number: 38-02031 Rev. *N

Page 21 of 43

CYP15G0101DXB

CYV15G0101DXB

When PARCTL = MID (open) and the decoder is bypassed

(DECMODE = LOW), ODD parity is generated for the received

and decoded character in the RXD[7:0] and RXST[1:0] bit

positions.

Parity Generation

In addition to the eleven data and status bits that are presented,

an RXOP parity output is also available. This allows the

CYP(V)15G0101DXB to support ODD parity generation. To

When PARCTL = HIGH, ODD parity is generated for the

TXD[7:0] and the RXST[2:0] status bits.

handle

a

wide range of system environments, the

CYP(V)15G0101DXB supports different forms of parity gener-

ation (in addition to no parity). When the decoder is enabled

(DECMODE  LOW), parity can be generated on

Receive Status Bits

When the 10B/8B decoder is enabled (DECMODE  LOW),

each character presented at the output register includes three

associated status bits. These bits are used to identify

■ the RXD[7:0] character

■ the RXD[7:0] character and RXST[2:0] status.

When the decoder is bypassed (DECMODE = LOW), parity can

be generated on

■ if the contents of the data bus are valid

■ the type of character present

■ the RXD[7:0] and RXST[1:0] bits

■ the RXD[7:0] and RXST[2:0] bits.

■ the state of receive BIST operations (regardless of the state of

DECMODE)

These modes differ in the number of bits which are included in

the parity calculation. For all cases, only ODD parity is provided

which ensures that at least one bit of the data bus is always a

logic-1. Those bits covered by parity generation are listed in

Table 15.

■ character violations.

These conditions normally overlap; for example, a valid data

character received with incorrect running disparity is not reported

as a valid data character. It is instead reported as a decoder

violation of some specific type. This implies a hierarchy or priority

level to the various status bit combinations. The hierarchy and

value of each status is listed in Table 16.

Parity generation is enabled through the 3-level select PARCTL

input. When PARCTL = LOW, parity checking is disabled, and

the RXOP output is disabled (high Z).

Within these status decodes, there are three forms of status

reporting. The two normal or data status reporting modes

(Type A and Type B) are selectable through the RXMODE input.

These status types allow compatibility with legacy systems, while

allowing full reporting in new systems. The third status type is

used for reporting receive BIST status and progress.

Table 15. Output Register Parity Generation

Receive Parity Generate Mode (PARCTL)

Signal

Name

MID

LOW^[24]

HIGH

DECMODE

= LOW

 LOW

BIST Status State Machine

RXST[2]

RXST[1]

RXST[0]

RXD[0]

RXD[1]

RXD[2]

RXD[3]

RXD[4]

RXD[5]

RXD[6]

RXD[7]

X^[25]

X

When the receive path is enabled to look for and compare the

received data stream with the BIST pattern, the RXST[2:0] bits

identify the present state of the BIST compare operation.

X

The BIST state machine has multiple states, as shown in

Figure 2 on page 24 and Table 16. When the receive PLL detects

an out-of-lock condition, the BIST state is forced to the

Start-of-BIST state, regardless of the present state of the BIST

state machine. If the number of detected errors ever exceeds the

number of valid matches by greater than 16, the state machine

is forced to the WAIT_FOR_BIST state where it monitors the

interface for the first character (D0.0) of the next BIST sequence.

Also, if the elasticity buffer ever hits and overflow/underflow

condition, the status is forced to the BIST_START until the buffer

is re-centered (approximately nine character periods).

X

To ensure compatibility between the source and destination

systems when operating in BIST, the sending and receiving ends

of the BIST sequence must use the same clock setup

(RXCKSEL = MID or RXCKSEL = LOW).

When PARCTL = MID (open) and the decoder is enabled

(DECMODE  LOW), ODD parity is generated for the received

and decoded character in the RXD[7:0] signals and is presented

on the RXOP output.

Notes

24. Receive path parity output driver (RXOP) is disabled (high Z) when PARCTL = LOW.

25. When the decoder is bypassed (DECMODE = LOW) and BIST is not enabled (Receive BIST latch output is HIGH), RXST[2] is driven to a logic-0, except when the

character in the output buffer is a framing character.

Document Number: 38-02031 Rev. *N

Page 22 of 43

CYP15G0101DXB

CYV15G0101DXB

JTAG ID

JTAG Support

The JTAG device ID for the CYP(V)15G0101DXB is

“1C804069”x.

The CYP(V)15G0101DXB contains a JTAG port to allow system

level diagnosis of device interconnect. Of the available JTAG

modes, only boundary scan is supported. This capability is

present only on the LVTTL inputs, LVTTL outputs and the

REFCLK clock input. The high-speed serial inputs and outputs

are not part of the JTAG test chain.

3-Level Select Inputs

Each 3-level select input reports as two bits in the scan register.

These bits report the LOW, MID, and HIGH state of the

associated input as 00, 10, and 11, respectively.

Table 16. Receive Character Status Bits

Description

RXST[2:0] Priority

Type-A Status

Receive BIST Status

Type-B Status

(Receive BIST = Enabled)

000

001

7

Normal character received. The valid data character on the output bus BIST data compare.

meets all the formatting requirements of data characters listed in Table 20. Character compared correctly

Special code detected. The valid special character on the output bus meets BIST command compare.

all the formatting requirements of the special code characters listed in Character compared correctly

Table 21, but is not the presently selected framing character or a decoder

violation indication.

010

2

Receive

Underrun/Overrun error.

The receive buffer was not able to

elasticity

buffer RESERVED

BIST last good.

Last character

sequence detected and valid.

of

BIST

add/drop

a

K28.5 or framing

character.

011

100

101

5

4

1

Framing character detected. This indicates that a character matching the RESERVED

patterns identified as a framing character (as selected by FRAMCHAR) was

detected. The decoded value of this character is present on the output bus.

Codeword violation. The character on the output bus is a C0.7. This

indicates that the received character cannot be decoded into any valid

character.

BIST last bad.

Last character

sequence detected invalid.

of

BIST

PLL out of lock. This indicates a PLL out of lock condition.

BIST start. Receive BIST is

enabled on this channel, but

character compares have not

yet commenced. This also

indicates a PLL out of lock

condition, and elasticity buffer

overflow/underflow conditions.

110

111

6

3

Running disparity error. The character on the output bus is a C4.7, C1.7, BIST error. While comparing

or C2.7.

characters, a mismatch was

found in one or more of the

decoded character bits.

RESERVED

BIST wait. The receiver is

comparing characters. but has

not yet found the start of BIST

character to enable the LFSR.

Document Number: 38-02031 Rev. *N

Page 23 of 43

CYP15G0101DXB

CYV15G0101DXB

Figure 2. Receive BIST State Machine

Monitor Data

Received

Receive BIST

Detected LOW

RXST =

RX PLL

Out of Lock

BIST_START (101)

RXST =

BIST_START (101)

RXST =

BIST_WAIT (111)

Elasticity

Buffer Error

Yes

Start of

BIST Detected

No

Yes, RXST = BIST_DATA_COMPARE (000)

OR BIST_COMMAND_COMPARE(001)

Compare

Next Character

RXST =

Mismatch

Match

BIST_COMMAND_COMPARE (001)

Command

Data or

Command

Auto-Abort

Condition

Yes

RXST =

BIST_DATA_COMPARE (000)

No

Data

End-of-BIST

State

End-of-BIST

State

No

Yes, RXST =

BIST_LAST_BAD (100)

Yes, RXST =

BIST_LAST_GOOD (010)

No, RXST =

BIST_ERROR (110)

Document Number: 38-02031 Rev. *N

Page 24 of 43

CYP15G0101DXB

CYV15G0101DXB

Static discharge voltage........................................... >2000 V

(per MIL-STD-883, method 3015)

Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the

device. User guidelines are not tested.

Latch-up current .....................................................> 200 mA

Power-up Requirements

Storage temperature................................. –65 °C to +150 °C

The CYP(V)15G0101DXB requires one power-supply. The

voltage on any input or I/O pin cannot exceed the power pin

during power-up.

Ambient temperature with

power applied ........................................... –55 °C to +125 °C

Supply voltage to ground potential ...............–0.5 V to +3.8 V

Operating Range

DC voltage applied to LVTTL outputs

in high Z State...................................... –0.5 V to V_CC+ 0.5 V

Range

Commercial

Industrial

Ambient Temperature

0 °C to +70 °C

V_CC

Output current into LVTTL outputs (LOW)................... 60 mA

DC input voltage.................................. –0.5 V to V_CC+ 0.5 V

+3.3 V ±5%

–40 °C to +85 °C

DC Electrical Characteristics

Over the Operating Range

Parameter

Description

Test Conditions

Min

Max

Unit

LVTTL-compatible Outputs

V_OHT

V_OLT

I_OST

I_OZL

Output HIGH voltage

Output LOW voltage

I_OH=  4 mA, V_CC= Min

I_OL= 4 mA, V_CC= Min

V_OUT= 0V^[26]

2.4

0

V_CC

0.4

V

Output short circuit current

–20

–100

20

mA

µA

High Z output leakage current

LVTTL-compatible Inputs

V_IHT

V_ILT

I_IHT

Input HIGH voltage

2.0

–0.5

–

V_CC+ 0.3

0.8

V

Input LOW voltage

Input HIGH current

V

REFCLK Input, V_IN= V_CC

Other Inputs, V_IN= V_CC

REFCLK Input, V_IN= 0.0 V

Other Inputs, V_IN= 0.0 V

V_IN= V_CC

1.5

mA

µA

mA

µA

–

+40

I_ILT

Input LOW current

–

–1.5

-40

–

I_IHPDT

I_ILPUT

Input HIGH current with internal pull-down

Input LOW current with internal pull-up

–

+200

–200

V_IN= 0.0 V

–

LVDIFF Inputs: REFCLK

[27]

V_DIFF

Input differential voltage

400

1.2

0.0

1.0

V_CC

mV

V

V_IHHP

Highest input HIGH voltage

Lowest input LOW voltage

Common mode range

V_ILLP

V_CC/ 2

V_CC– 1.2

V

[28]

V_COMREF

V

3-Level Inputs

V_IHH

V_IMM

V_ILL

I_IHH

I_IMM

I_ILL

3-level input HIGH voltage

Min  V_CC Max

V_IN= V_CC

0.87 × V_CC

V_CC

V

3-level input MID voltage

3-level input LOW voltage

Input HIGH current

0.47 × V_CC0.53 × V_CC

0.0

–

0.13 × V_CC

200

V

µA

Input MID current

V_IN= V_CC/2

–50

–

50

Input LOW current

V_IN= GND

–200

Differential CML Serial Outputs: OUT1, OUT2

V_OHC

Output HIGH voltage

(V_CCreferenced)

100  differential load

150  differential load

V_CC– 0.5 V_CC0.2

V_CC0.5 V_CC0.2

V

Notes

26. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle.

27. This is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 or logic-0. A logic-1 exists when the

true (+) input is more positive than the complement () input. A logic-0 exists when the complement () input is more positive than true (+) input.

28. The common mode range defines the allowable range of REFCLK+ and REFCLKwhen REFCLK+ = REFCLK. This marks the zero-crossing between the true

and complement inputs as the signal switches between a logic-1 and a logic-0.

Document Number: 38-02031 Rev. *N

Page 25 of 43

CYP15G0101DXB

CYV15G0101DXB

DC Electrical Characteristics

Over the Operating Range (continued)

Parameter

V_OLC

Description

Output LOW voltage

(V_CCreferenced)

Test Conditions

100  differential load

150  differential load

100  differential load

150  differential load

Min

Max

Unit

V

V_CC1.4 V_CC0.7

V

V_ODIF

Output differential voltage

|(OUT+)  (OUT)|

450

560

900

mV

1000

Differential Serial Line Receiver Inputs: IN1, IN2

[29]

V_DIFFS

V_IHE

V_ILE

I_IHE

Input differential voltage |(IN+)  (IN)|

Highest input HIGH voltage

Lowest input LOW voltage

Input HIGH current

100

1200

V_CC

–

mV

V

–

V_CC– 2.0

–

V

V_IN= V_IHEMax

V_IN= V_ILEMin

1350

–

µA

V

I_ILE

Input LOW current

–700

[30, 31]

V_COM

Common mode input range

V_CC 1.95 V_CC 0.05

Power Supply

Typ ^[33]

Max ^[32]

500

Unit

mA

I_CC

Power supply current

REFCLK= Max

Commercial

Industrial

390

510

I_CC

Power supply current

REFCLK = 125 MHz

Commercial

Industrial

390

500

510

AC Test Loads and Waveforms

3.3 V

R1

R2

R_L= 100 

R

L

R1 = 590 

R2 = 435

C_L

(b) CML Output Test Load^[34]

C_L 7 pF

(Includes fixture and

probe capacitance)

V_IHE

(a) LVTTL Output Test Load ^[34]

V_IHE

80%

3.0 V

20%

V_ILE

 270 ps

2.0 V

0.8 V

2.0 V

0.8 V

V_th= 1.4 V

GND

V_th= 1.4 V

V_ILE

 270 ps

(d) CML/LVPECL Input Test Waveform

 1 ns

[35]

(c) LVTTL Input Test Waveform

Notes

29. This is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 or logic-0. A logic-1 exists when

the true (+) input is more positive than the complement () input. A logic-0 exists when the complement () input is more positive than true (+) input.

30. The common mode range defines the allowable range of INPUT+ and INPUT when INPUT+ = INPUT. This marks the zero-crossing between the true and

complement inputs as the signal switches between a logic-1 and a logic-0.

31. Not applicable for AC-coupled interfaces. For AC-coupled interfaces, V

requirement still needs to be satisfied.

DIFFS

32. Maximum I is measured with V_CC= MAX, with all Serial Drivers enabled, parallel outputs unloaded, sending a alternating 01 pattern to the Serial Input Receiver.

CC

33. Typical I is measured under similar conditions except with V = 3.3V, T = 25°C, parallel outputs unloaded, RXCKSEL = MID, and with one Serial Line

CC

A

Driver sending a continuous alternating 01 pattern to the Serial Input Receiver.

34. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only. 5pF differential load reflects tester capacitance,

and is recommended at low data rates only.

35. The LVTTL switching threshold is 1.4V. All timing references are made relative to the point where the signal edges crosses this threshold voltage.

Document Number: 38-02031 Rev. *N

Page 26 of 43

CYP15G0101DXB

CYV15G0101DXB

CYP(V)15G0101DXB AC Characteristics

Over the Operating Range

Parameter

Description

Min

Max

Unit

Transmitter LVTTL Switching Characteristics

f_TS

TXCLK clock frequency

19.5

6.66

2.2

150

51.28

–

MHz

ns

t_TXCLK

TXCLK period

[36]

t_TXCLKH

TXCLK HIGH time

ns

[36]

t_TXCLKL

TXCLK LOW time

2.2

–

ns

[36, 37, 38]

t_TXCLKR

t_TXCLKF

t_TXDS

TXCLK rise time

0.2

1.7

–

ns

[36, 37, 38]

TXCLK fall time

0.2

ns

Transmit data det-up time toTXCLK (TXCKSEL  LOW)

Transmit data hold time from TXCLK(TXCKSEL  LOW)

TXCLKO clock frequency = 1x or 2x REFCLK frequency

TXCLKO period

1.7

ns

t_TXDH

0.8

–

ns

f_TOS

19.5

6.66

–1.0

–0.5

150

51.28

+0.5

+1.0

MHz

ns

t_TXCLKO

t_TXCLKOD+

t_TXCLKOD–

TXCLKO+ duty cycle with 60% HIGH time

TXCLKO– duty cycle with 40% HIGH time

ns

Receiver LVTTL Switching Characteristics

f_RS

RXCLK clock output frequency

9.75

6.66

2.33 ^[36]

150

102.56

26.64

52.28

26.64

52.28

+1.0

1.2

MHz

ns

t_RXCLKP

t_RXCLKH

RXCLK period

RXCLK HIGH time (RXRATE = LOW)

RXCLK HIGH time (RXRATE = HIGH)

RXCLK LOW time (RXRATE = LOW)

RXCLK LOW time (RXRATE = HIGH)

RXCLK duty cycle centered at 50%

5.66

t_RXCLKL

t_RXCLKD

2.33 ^[36]

5.66

–1.0

[36]

t_RXCLKR

RXCLK rise time

0.3

[36]

t_RXCLKF

RXCLK fall time

0.3

1.2

[39]

t_RXDV–

Status and data valid time to RXCLK (RXCKSEL = MID)

Status and data valid time to RXCLK(HALF RATE RECOVERED CLOCK)

Status and data valid time from RXCLK(RXCKSEL = MID)

Status and data valid time from RXCLK(HALF RATE RECOVERED CLOCK)

5UI – 1.5

5UI – 1.0

5UI – 1.8

5UI – 2.3

–

[39]

t_RXDV+

–

REFCLK Switching Characteristics Over the Operating Range

f_REF

REFCLK clock frequency

19.5

6.6

5.9

2.9^[36]

5.9

2.9^[36]

30

150

MHz

ns

%

t_REFCLK

t_REFH

REFCLK period

51.28

REFCLK HIGH time (TXRATE = HIGH)

REFCLK HIGH time (TXRATE = LOW)

REFCLK LOW time (TXRATE = HIGH)

REFCLK LOW time (TXRATE = LOW)

REFCLK duty cycle

–

t_REFL

–

[40]

t_REFD

70

2

[36, 37, 38]

t_REFR

REFCLK rise time (20% – 80%)

–

ns

[36, 37, 38]

t_REFF

t_TREFDS

t_TREFDH

REFCLK fall time (20% – 80%)

–

2

Transmit data setup time toREFCLK (TXCKSEL LOW)

Transmit data hold time from REFCLK(TXCKSEL LOW)

1.7

0.8

–

Notes

36. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.

37. The ratio of rise time to falling time must not vary by greater than 2:1.

38. For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time.

39. Parallel data output specifications are only valid if all inputs or outputs are loaded with similar DC and AC loads.

40. The duty cycle specification is a simultaneous condition with the t

and t

parameters. This means that at faster character rates the REFCLK duty cycle

REFH

REFL

cannot be as large as 30%–70%.

Document Number: 38-02031 Rev. *N

Page 27 of 43

CYP15G0101DXB

CYV15G0101DXB

CYP(V)15G0101DXB AC Characteristics

Over the Operating Range (continued)

Parameter

Description

Min

–

Max

Unit

ns

[43]

t_RREFDA

Receive data access time from REFCLK (RXCKSEL LOW)

Receive data valid time from REFCLK(RXCKSEL LOW)

Received data valid time to RXCLK (RXCKSEL = LOW)

Received data valid time from RXCLK (RXCKSEL = LOW)

Received data valid time to RXCLKC (RXCKSEL = LOW)

Received data valid time from RXCLKC (RXCKSEL = LOW)

REFCLK frequency referenced to extracted received clock frequency

9.5

t_RREFDV

t_REFDV–

t_REFDV+

t_REFCDV–

t_REFCDV+

2.5

–

ns

10UI – 4.7

0.5

–

ns

–

ns

10UI – 4.3

–0.2

–

ns

[41, 42]

t_REFRX

–1500

+1500

ppm

Transmit Serial Outputs and TX PLL Characteristics

t_B

Bit time

5100

60

666

270

500

1000

270

500

1000

25

ps

us

[42]

t_RISE

CML output rise time 20%–80% (CML test load)

SPDSEL = HIGH

SPDSEL = MID

SPDSEL = LOW

SPDSEL = HIGH

SPDSEL = MID

SPDSEL = LOW

IEEE 802.3z^[47]

100

180

60

[42]

t_FALL

CML output fall time 80%–20% (CML test load)

100

180

–

[42, 44, 46]

[42, 45, 46]

t_DJ

t_RJ

Deterministic Jitter (peak-peak)

Random Jitter ()

–

11

t_TXLOCK

Transmit PLL lock to REFCLK

–

200

Receive Serial Inputs and CDR PLL Characteristics

t_RXLOCK

Receive PLL lock to input data stream (cold start)

Receive PLL lock to input data stream

Receive PLL unlock rate

–

376K

46

UI^[48]

UI

t_RXUNLOCK

–

UI

[46]

t_JTOL

Total jitter tolerance

IEEE 802.3z^[47]

600

370

–

ps

[46]

t_DJTOL

Deterministic jitter tolerance

–

ps

Capacitance^[42]

Parameter

C_INTTL

Description

TTL input capacitance

Test Conditions

Max

7

Unit

pF

T_A= 25 °C, f₀= 1 MHz, V_CC= 3.3 V

C_INPECL

PECL input capacitance

4

pF

Notes

41. REFCLK has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time. REFCLK

must be within ±1500 ppm (±0.15%) of the remote transmitter’s PLL reference (REFCLK) frequency. Although transmitting to a HOTLink II receiver necessitates

the frequency difference between the transmitter and receiver reference clocks to be within ±1500 ppm, the stability of the crystal needs to be within the limits

specified by the appropriate standard when transmitting to a remote receiver that is compliant to that standard. For example, to be IEEE 802.3z Gigabit Ethernet

compliant, the frequency stability of the crystal needs to be within ±100 ppm.

42. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.

43. Since this timing parameter is greater than the minimum time period of REFCLK it sets an upper limit to the frequency in which REFCLKx can be used to clock

the receive data out of the output register. For predictable timing, users can use this parameter only if REFCLK period is greater than sum of t

and set-up

RREFDA

time of the upstream device. When this condition is not true, RXCLKC± or RXCLKA± (a buffered or delayed version of REFCLK when RXCKSELx = LOW) could

be used to clock the receive data out of the device.

44. While sending continuous K28.5s, outputs loaded to a balanced 100 load, measured at the cross point of the differential outputs over the operating range.

45. While sending continuous K28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to REFCLK input, over the operating

range.

^{46. Total jitter is calculated at an assumed BER of 1E}12. Hence: Total Jitter (t ) = (t * 14) + t

.

DJ

J

RJ

47. Also meets all Jitter Generation and Jitter Tolerance requirements as specified by SMPTE 259M, SMPTE 292M, CPRI, ESCON, FICON, Fibre Channel and

DVB-ASI.

48. Receiver UI (Unit Interval) iscalculatedas1/(f

* 20)(whenRXRATE = HIGH)or1/(f

* 10) (whenRXRATE = LOW)if no data is being received, or 1/(f

* 20)(when

REF

RXRATE = HIGH) or 1/(f

* 10) (when RXRATE = LOW) of the remote transmitter if data is being received. In an operating link this is equivalent to t

REF

B

Document Number: 38-02031 Rev. *N

Page 28 of 43

CYP15G0101DXB

CYV15G0101DXB

Switching Waveforms for the HOTLink II Transmitter

Transmit Interface

Write Timing

t_TXCLK

TXCKSEL  LOW

t_TXCLKH

t

TXCLKL

TXCLK

t

TXDS

TXD[7:0],

TXCT[1:0],

TXOP,

SCSEL

t

TXDH

Transmit Interface

Write Timing

TXCKSEL = LOW

TXRATE = LOW

t_REFCLK

t_REFH

t

REFL

REFCLK

t

TREFDS

TXD[7:0],

TXCT[1:0],

TXOP,

SCSEL

t

TREFDH

Transmit Interface

Write Timing

TXCKSEL = LOW

TXRATE = HIGH

t_REFCLK

t_REFH

t

REFL

Note ⁴⁹

Note 49

REFCLK

t

TREFDS

TXD[7:0],

TXCT[1:0],

TXOP,

SCSEL

t

TREFDH

t

Transmit Interface

TXCLKO Timing

TXCKSEL = LOW

TXRATE = HIGH

REFCLK

t

t_REFL

REFH

REFCLK

t

TXCLKO

Note ⁵¹

t_TXCLKOD+

t

TXCLKOD

–

Note ⁵⁰

TXCLKO

Notes

49. When REFCLK is configured for half-rate operation (TXRATE = HIGH) and data is captured using REFCLK instead of TXCLK clock (TXCKSEL = LOW), data

is captured using both the rising and falling edges of REFCLK.

50. The TXCLKO output is at twice the rate of REFCLK when TXRATE = HIGH and same rate as REFCLK when TXRATE = LOW. TXCLKO does not follow the duty

cycle of REFCLK.

51. The rising edge of TXCLKO output has no direct phase relationship to the REFCLK input.

Document Number: 38-02031 Rev. *N

Page 29 of 43

CYP15G0101DXB

CYV15G0101DXB

Transmit Interface

TXCLKO Timing

TXCKSEL = LOW

TXRATE = LOW

t_REFCLK

t_REFH

t

REFL

Note ⁵⁰

REFCLK

t_TXCLKO

t_TXCLKOD+

Note ⁵²

t

TXCLKOD

–

TXCLKO

Receive Interface

Read Timing

RXCKSEL = LOW

TXRATE = LOW

t_REFCLK

t_REFH

t

REFL

REFCLK

t

RREFDV

RREFDA

RXD[7:0],

RXST[2:0],

RXOP

t

REFDV+

t

REFDV–

REFCDV+

t

REFCDV

–

Note ⁵³

RXCLK

RXCLKC+

Receive Interface

Read Timing

RXCKSEL = LOW

TXRATE = HIGH

t_REFCLK

t_REFH

t

REFL

REFCLK

t

RREFDA

t

RREFDV

RXD[7:0],

RXST[2:0],

RXOP

t

REFDV+

t

REFDV

–

t

REFCDV+

t

REFCDV

–

Note ⁵³

RXCLK

RXCLKC+

Note 54

Notes

52. The rising edge of TXCLKO output has no direct phase relationship to the REFCLK input.

53. RXCLK and RXCLK+ are delayed versions of REFCLK when RXCKSEL = LOW, and are different in phase from each other.

54. When operated with a half-rate REFCLK, the setup and hold specifications for data relative to RXCLK are relative to both rising and falling edges of the clock output

Document Number: 38-02031 Rev. *N

Page 30 of 43

CYP15G0101DXB

CYV15G0101DXB

Receive Interface

Read Timing

RXCKSEL = MID

RXRATE = LOW

t_RXCLKP

t_RXCLKH

t

RXCLKL

RXCLK+

RXCLK–

t

RXDV

–

RXD[7:0],

RXST[2:0],

RXOP

t

RXDV+

Receive Interface

Read Timing

RXCKSEL = MID

RXRATE = HIGH

t_RXCLKP

t_RXCLKH

t

RXCLKL

RXCLK+

RXCLK–

t

RXDV

–

RXD[7:0],

RXST[2:0],

RXOP

t

RXDV+

Document Number: 38-02031 Rev. *N

Page 31 of 43

CYP15G0101DXB

CYV15G0101DXB

Table 17. Package Coordinate Signal Allocation

Ball

ID

Ball

ID

Ball

ID

Signal Name

Signal Type

Signal Name

Signal Type

Signal Name

Signal Type

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

D1

D2

D3

D4

VCC

IN2+

POWER

CML IN

D5

D6

D7

D8

D9

D10

E1

E2

E3

E4

E5

E6

E7

E8

E9

E10

F1

GND

GROUND

G9

G10

H1

H2

H3

H4

H5

H6

H7

H8

H9

H10

J1

TXCLKO+

TXCLKO–

RXD[0]

RXD[2]

RXD[6]

LFI

LVTTL OUT

LVTTL IN

VCC

POWER

GND

GROUND

OUT2–

RXMODE

TXMODE[1]

IN1+

CML OUT

TMS

LVTTL IN PU

3-LEVEL SEL

LVTTL IN PU

GROUND

3-LEVEL SEL

CML IN

TRSTZ

TDI

BISTLE

DECMODE

OELE

TXCT[1]

TXD[6]

TXD[3]

TXCLK

TXRST

#NC

VCC

POWER

LVTTL IN

OUT1–

VCC

CML OUT

LVTTL IN

POWER

GND

LVTTL IN PD

LVTTL IN PU

NO CONNECT

POWER

VCC

POWER

GND

GROUND

IN2–

CML IN

GND

GROUND

TDO

LVTTL 3-S OUT

CML OUT

GND

GROUND

VCC

OUT2+

TXRATE

TXMODE[0]

IN1–

TCLK

LVTTL IN PD

3-LEVEL SEL

LVTTL OUT

GROUND

J2

RXD[3]

RXD[7]

RXCLK–

TXCT[0]

TXD[5]

TXD[2]

TXD[0]

#NC

LVTTL OUT

LVTTL IN

LVTTL IN PD

3-LEVEL SEL

CML IN

RXCKSEL

TXCKSEL

RXST[2]

RXST[1]

RXST[0]

GND

J3

J4

J5

#NC

NO CONNECT

CML OUT

F2

J6

LVTTL IN

OUT1+

VCC

F3

J7

LVTTL IN

POWER

F4

J8

LVTTL IN

RFEN

LVTTL IN PD

LVTTL IN PU

LVTTL 3-S OUT

LVTTL IN PD

3-LEVEL SEL

LVTTL IN

F5

GND

GROUND

J9

NO CONNECT

POWER

LPEN

F6

GND

GROUND

J10

K1

K2

K3

K4

K5

K6

K7

K8

K9

K10

VCC

RXLE

F7

GND

GROUND

VCC

POWER

RXCLKC+

RXRATE

SDASEL

SPDSEL

PARCTL

RFMODE

INSEL

F8

TXPER

REFCLK–

REFCLK+

RXOP

RXD[1]

RXD[5]

GND

LVTTL OUT

PECL IN

RXD[4]

VCC

LVTTL OUT

POWER

F9

F10

G1

G2

G3

G4

G5

G6

G7

G8

PECL IN

RXCLK+

TXD[7]

TXD[4]

TXD[1]

VCC

LVTTL OUT

LVTTL IN

LVTTL 3-S OUT

LVTTL OUT

GROUND

LVTTL IN

POWER

BOE[0]

BOE[1]

FRAMCHAR

GND

LVTTL IN PU

3-LEVEL SEL

GROUND

GND

GROUND

SCSEL

VCC

LVTTL IN PD

POWER

GND

GROUND

GND

GROUND

TXOP

LVTTL IN PU

Document Number: 38-02031 Rev. *N

Page 32 of 43

CYP15G0101DXB

CYV15G0101DXB

c is set to D, xx is the decimal value of the binary number

composed of the bits E, D, C, B, and A in that order, and the y is

the decimal value of the binary number composed of the bits H,

G, and F in that order. When c is set to K, xx and y are derived

by comparing the encoded bit patterns of the Special Character

to those patterns derived from encoded Valid Data bytes and

selecting the names of the patterns most similar to the encoded

bit patterns of the Special Character.

X3.230 Codes and Notation Conventions

Information to be transmitted over a serial link is encoded eight

bits at a time into a 10-bit Transmission Character and then sent

serially, bit by bit. Information received over a serial link is

collected ten bits at a time, and those Transmission Characters

that are used for data characters are decoded into the correct

eight-bit codes. The 10-bit Transmission Code supports all 256

eight-bit combinations. Some of the remaining Transmission

Characters (Special Characters) are used for functions other

than data transmission.

Under the above conventions, the Transmission Character used

for the examples above, is referred to by the name D5.2. The

Special Character K29.7 is so named because the first six bits

(abcdei) of this character make up a bit pattern similar to that

resulting from the encoding of the unencoded 11101 pattern (29),

and because the second four bits (fghj) make up a bit pattern

similar to that resulting from the encoding of the unencoded 111

pattern (7). This definition of the 10-bit Transmission Code is

based on the following references.

The primary use of a Transmission Code is to improve the trans-

mission characteristics of a serial link. The encoding defined by

the Transmission Code ensures that sufficient transitions are

present in the serial bit stream to make clock recovery possible

at the Receiver. Such encoding also greatly increases the

likelihood of detecting any single or multiple bit errors that may

occur during transmission and reception of information. In

addition, some Special Characters of the Transmission Code

selected by Fibre Channel Standard contain a distinct and easily

recognizable bit pattern that assists the receiver in achieving

character alignment on the incoming bit stream.

A.X. Widmer and P.A. Franaszek. “A DC-Balanced, Parti-

tioned-Block, 8B/10B Transmission Code” IBM Journal of

Research and Development, 27, No. 5: 440-451 (September, 1983).

U.S. Patent 4,486,739. Peter A. Franaszek and Albert X.

Widmer. “Byte-Oriented DC Balanced (0.4) 8B/10B Partitioned

Block Transmission Code” (December 4, 1984).

Notation Conventions

Fibre Channel Physical and Signaling Interface (ANS

X3.230-1994 ANSI FC-PH Standard).

The documentation for the 8B/10B Transmission Code uses

letter notation for the bits in an eight-bit byte. Fibre Channel

Standard notation uses a bit notation of A, B, C, D, E, F, G, H for

the eight-bit byte for the raw eight-bit data, and the letters a, b,

c, d, e, i, f, g, h, j for encoded 10-bit data. There is a correspon-

dence between bit A and bit a, B and b, C and c, D and d, E and

e, F and f, G and g, and H and h. Bits i and j are derived, respec-

tively, from (A,B,C,D,E) and (F,G,H).

IBM Enterprise Systems Architecture/390 ESCON I/O Interface

(document number SA22-7202).

8B/10B Transmission Code

The following information describes how the tables are used for

both generating valid Transmission Characters (encoding) and

checking the validity of received Transmission Characters

(decoding). It also specifies the ordering rules to be followed

when transmitting the bits within a character and the characters

within any higher-level constructs specified by a standard.

The bit labeled A in the description of the 8B/10B Transmission

Code corresponds to bit 0 in the numbering scheme of the FC-2

specification, B corresponds to bit 1, as shown below.

FC-2 bit designation—76543210

HOTLink D/Q designation—76543210

Transmission Order

8B/10B bit designation—HGFEDCBA

To clarify this correspondence, the following example shows the

conversion from an FC-2 Valid Data Byte to a Transmission

Character.

Within the definition of the 8B/10B Transmission Code, the bit

positions of the Transmission Characters are labeled a, b, c, d,

e, i, f, g, h, j. Bit “a” is transmitted first followed by bits b, c, d, e,

i, f, g, h, and j in that order.

FC-2 45H

Bits: 7654 3210

0100 0101

Note that bit i is transmitted between bit e and bit f, rather than

in alphabetical order.

Converted to 8B/10B notation, note that the order of bits has

been reversed):

Valid and Invalid Transmission Characters

The following tables define the valid Data Characters and valid

Special Characters (K characters), respectively. The tables are

used for both generating valid Transmission Characters and

checking the validity of received Transmission Characters. In the

tables, each Valid-Data-byte or Special-Character-code entry

has two columns that represent two Transmission Characters.

The two columns correspond to the current value of the running

disparity. Running disparity is a binary parameter with either a

negative (–) or positive (+) value.

Data Byte Name D5.2

Bits: ABCDE FGH

10100 010

Translated to a transmission Character in the 8B/10B Trans-

mission Code:

Bits: abcdei fghj

101001 0101

Each valid Transmission Character of the 8B/10B Transmission

Code has been given a name using the following convention:

cxx.y, where c is used to show whether the Transmission

Character is a Data Character (c is set to D, and SC/D = LOW)

or a Special Character (c is set to K, and SC/D = HIGH). When

After powering on, the Transmitter may assume either a positive

or negative value for its initial running disparity. Upon

transmission of any Transmission Character, the transmitter will

select the proper version of the Transmission Character based

on the current running disparity value, and the Transmitter

Document Number: 38-02031 Rev. *N

Page 33 of 43

CYP15G0101DXB

CYV15G0101DXB

calculates a new value for its running disparity based on the

contents of the transmitted character. Special Character codes

C1.7 and C2.7 can be used to force the transmission of a specific

Special Character with a specific running disparity as required for

some special sequences in X3.230.

disparity is calculated. This new value is used as the Trans-

mitter’s current running disparity for the next Valid Data byte or

Special Character byte to be encoded and transmitted. Table 18

shows naming notations and examples of valid transmission

characters.

After powering on, the Receiver may assume either a positive or

negative value for its initial running disparity. Upon reception of

any Transmission Character, the Receiver decides whether the

Transmission Character is valid or invalid according to the

following rules and tables and calculates a new value for its

Running Disparity based on the contents of the received

character.

Use of the Tables for Checkingthe Validity ofReceived

Transmission Characters

The column corresponding to the current value of the Receiver’s

running disparity is searched for the received Transmission

Character. If the received Transmission Character is found in the

proper column, then the Transmission Character is valid and the

Data byte or Special Character code is determined (decoded). If

the received Transmission Character is not found in that column,

then the Transmission Character is invalid. This is called a code

violation. Independent of the Transmission Character’s validity,

the received Transmission Character is used to calculate a new

value of running disparity. The new value is used as the

Receiver’s current running disparity for the next received Trans-

mission Character.

The following rules for running disparity are used to calculate the

new running-disparity value for Transmission Characters that

have been transmitted (Transmitter’s running disparity) and that

have been received (Receiver’s running disparity).

Running disparity for a Transmission Character is calculated

from sub-blocks, where the first six bits (abcdei) form one

sub-block and the second four bits (fghj) form the other

sub-block. Running disparity at the beginning of the six-bit

sub-block is the running disparity at the end of the previous

Transmission Character. Running disparity at the beginning of

the four-bit sub-block is the running disparity at the end of the

six-bit sub-block. Running disparity at the end of the Trans-

mission Character is the running disparity at the end of the

four-bit sub-block.

Table 18. Valid Transmission Characters

Data

D_INor Q_OUT

Byte Name

Hex Value

765

43210

D0.0

D1.0

D2.0

000

00000

00

01

02

Running disparity for the sub-blocks is calculated as follows:

1. Running disparity at the end of any sub-block is positive if the

sub-block contains more ones than zeros. It is also positive at

the end of the six-bit sub-block if the six-bit sub-block is

000111, and it is positive at the end of the four-bit sub-block if

the four-bit sub-block is 0011.

000

00001

00010

.

2. Running disparity at the end of any sub-block is negative if the

sub-block contains more zeros than ones. It is also negative

at the end of the six-bit sub-block if the six-bit sub-block is

111000, and it is negative at the end of the four-bit sub-block

if the four-bit sub-block is 1100.

D5.2

010

00101

45

.

3. Otherwise, running disparity at the end of the sub-block is the

same as at the beginning of the sub-block.

D30.7

D31.7

111

11110

11111

FE

FF

Use of the Tables for Generating Transmission

Characters

Detection of a code violation does not necessarily show that the

Transmission Character in which the code violation was detected

is in error. Code violations may result from a prior error that

altered the running disparity of the bit stream which did not result

in a detectable error at the Transmission Character in which the

error occurred. Table 19 shows an example of this behavior.

The appropriate entry in the table is found for the Valid Data byte

or the Special Character byte for which a Transmission

Character is to be generated (encoded). The current value of the

Transmitter’s running disparity is used to select the Transmission

Character from its corresponding column. For each Trans-

mission Character transmitted, a new value of the running

Table 19. Code Violations Resulting from Prior Errors

RD

–

Character

D21.1

RD

–

Character

D10.2

RD

–

Character

D23.5

RD

+

Transmitted data character

Transmitted bit stream

Bit stream after error

–

101010 1001

101010 1011

D21.0

–

010101 0101

D10.2

–

111010 1010

Code Violation

+

–

+

Decoded data character

–

+

Document Number: 38-02031 Rev. *N

Page 34 of 43

CYP15G0101DXB

CYV15G0101DXB

Table 20. Valid Data Characters (TXCTx[0] = 0, RXSTx[2:0] = 000)

Data

Byte

Data

Byte

Bits

Current RD

Current RD+

abcdei fghj

Bits

Current RD

abcdei fghj

Current RD+

abcdei fghj

HGF EDCBA

000 00000

000 00001

000 00010

000 00011

000 00100

000 00101

000 00110

000 00111

000 01000

000 01001

000 01010

000 01011

000 01100

000 01101

000 01110

000 01111

000 10000

000 10001

000 10010

000 10011

000 10100

000 10101

000 10110

000 10111

000 11000

000 11001

000 11010

000 11011

000 11100

000 11101

000 11110

000 11111

abcdei fghj

HGF EDCBA

001 00000

001 00001

001 00010

001 00011

001 00100

001 00101

001 00110

001 00111

001 01000

001 01001

001 01010

001 01011

001 01100

001 01101

001 01110

001 01111

001 10000

001 10001

001 10010

001 10011

001 10100

001 10101

001 10110

001 10111

001 11000

001 11001

001 11010

001 11011

001 11100

001 11101

001 11110

001 11111

Name

D0.0

D1.0

100111 0100 011000 1011

011101 0100 100010 1011

101101 0100 010010 1011

110001 1011 110001 0100

110101 0100 001010 1011

101001 1011 101001 0100

011001 1011 011001 0100

111000 1011 000111 0100

111001 0100 000110 1011

100101 1011 100101 0100

010101 1011 010101 0100

110100 1011 110100 0100

001101 1011 001101 0100

101100 1011 101100 0100

011100 1011 011100 0100

010111 0100 101000 1011

011011 0100 100100 1011

100011 1011 100011 0100

010011 1011 010011 0100

110010 1011 110010 0100

001011 1011 001011 0100

101010 1011 101010 0100

011010 1011 011010 0100

111010 0100 000101 1011

110011 0100 001100 1011

100110 1011 100110 0100

010110 1011 010110 0100

110110 0100 001001 1011

001110 1011 001110 0100

101110 0100 010001 1011

011110 0100 100001 1011

101011 0100 010100 1011

100111 0101 011000 0101

011101 0101 100010 0101

101101 0101 010010 0101

D0.1

D1.1

100111 1001 011000 1001

011101 1001 100010 1001

101101 1001 010010 1001

110001 1001 110001 1001

110101 1001 001010 1001

101001 1001 101001 1001

011001 1001 011001 1001

111000 1001 000111 1001

111001 1001 000110 1001

100101 1001 100101 1001

010101 1001 010101 1001

110100 1001 110100 1001

001101 1001 001101 1001

101100 1001 101100 1001

011100 1001 011100 1001

010111 1001 101000 1001

011011 1001 100100 1001

100011 1001 100011 1001

010011 1001 010011 1001

110010 1001 110010 1001

001011 1001 001011 1001

101010 1001 101010 1001

011010 1001 011010 1001

111010 1001 000101 1001

110011 1001 001100 1001

100110 1001 100110 1001

010110 1001 010110 1001

110110 1001 001001 1001

001110 1001 001110 1001

101110 1001 010001 1001

011110 1001 100001 1001

101011 1001 010100 1001

100111 0011 011000 1100

011101 0011 100010 1100

101101 0011 010010 1100

D2.0

D2.1

D3.0

D3.1

D4.0

D4.1

D5.0

D5.1

D6.0

D6.1

D7.0

D7.1

D8.0

D8.1

D9.0

D9.1

D10.0

D11.0

D12.0

D13.0

D14.0

D15.0

D16.0

D17.0

D18.0

D19.0

D20.0

D21.0

D22.0

D23.0

D24.0

D25.0

D26.0

D27.0

D28.0

D29.0

D30.0

D31.0

D0.2

D10.1

D11.1

D12.1

D13.1

D14.1

D15.1

D16.1

D17.1

D18.1

D19.1

D20.1

D21.1

D22.1

D23.1

D24.1

D25.1

D26.1

D27.1

D28.1

D29.1

D30.1

D31.1

D0.3

010 00000

010 00001

010 00010

011 00000

011 00001

011 00010

D1.2

D1.3

D2.2

D2.3

Document Number: 38-02031 Rev. *N

Page 35 of 43

CYP15G0101DXB

CYV15G0101DXB

Table 20. Valid Data Characters (TXCTx[0] = 0, RXSTx[2:0] = 000) (continued)

Data

Byte

Data

Byte

Bits

Current RD

Current RD+

abcdei fghj

Bits

Current RD

abcdei fghj

Current RD+

abcdei fghj

HGF EDCBA

010 00011

010 00100

010 00101

010 00110

010 00111

010 01000

010 01001

010 01010

010 01011

010 01100

010 01101

010 01110

010 01111

010 10000

010 10001

010 10010

010 10011

010 10100

010 10101

010 10110

010 10111

010 11000

010 11001

010 11010

010 11011

010 11100

010 11101

010 11110

010 11111

100 00000

100 00001

100 00010

100 00011

100 00100

100 00101

100 00110

abcdei fghj

HGF EDCBA

011 00011

011 00100

011 00101

011 00110

011 00111

011 01000

011 01001

011 01010

011 01011

011 01100

011 01101

011 01110

011 01111

011 10000

011 10001

011 10010

011 10011

011 10100

011 10101

011 10110

011 10111

011 11000

011 11001

011 11010

011 11011

011 11100

011 11101

011 11110

011 11111

101 00000

101 00001

101 00010

101 00011

101 00100

101 00101

101 00110

Name

D3.2

D4.2

110001 0101 110001 0101

110101 0101 001010 0101

101001 0101 101001 0101

011001 0101 011001 0101

111000 0101 000111 0101

111001 0101 000110 0101

100101 0101 100101 0101

010101 0101 010101 0101

110100 0101 110100 0101

001101 0101 001101 0101

101100 0101 101100 0101

011100 0101 011100 0101

010111 0101 101000 0101

011011 0101 100100 0101

100011 0101 100011 0101

010011 0101 010011 0101

110010 0101 110010 0101

001011 0101 001011 0101

101010 0101 101010 0101

011010 0101 011010 0101

111010 0101 000101 0101

110011 0101 001100 0101

100110 0101 100110 0101

010110 0101 010110 0101

110110 0101 001001 0101

001110 0101 001110 0101

101110 0101 010001 0101

011110 0101 100001 0101

101011 0101 010100 0101

100111 0010 011000 1101

011101 0010 100010 1101

101101 0010 010010 1101

110001 1101 110001 0010

110101 0010 001010 1101

101001 1101 101001 0010

011001 1101 011001 0010

D3.3

D4.3

110001 1100 110001 0011

110101 0011 001010 1100

101001 1100 101001 0011

011001 1100 011001 0011

111000 1100 000111 0011

111001 0011 000110 1100

100101 1100 100101 0011

010101 1100 010101 0011

110100 1100 110100 0011

001101 1100 001101 0011

101100 1100 101100 0011

011100 1100 011100 0011

010111 0011 101000 1100

011011 0011 100100 1100

100011 1100 100011 0011

010011 1100 010011 0011

110010 1100 110010 0011

001011 1100 001011 0011

101010 1100 101010 0011

011010 1100 011010 0011

111010 0011 000101 1100

110011 0011 001100 1100

100110 1100 100110 0011

010110 1100 010110 0011

110110 0011 001001 1100

001110 1100 001110 0011

101110 0011 010001 1100

011110 0011 100001 1100

101011 0011 010100 1100

100111 1010 011000 1010

011101 1010 100010 1010

101101 1010 010010 1010

110001 1010 110001 1010

110101 1010 001010 1010

101001 1010 101001 1010

011001 1010 011001 1010

D5.2

D5.3

D6.2

D6.3

D7.2

D7.3

D8.2

D8.3

D9.2

D9.3

D10.2

D11.2

D12.2

D13.2

D14.2

D15.2

D16.2

D17.2

D18.2

D19.2

D20.2

D21.2

D22.2

D23.2

D24.2

D25.2

D26.2

D27.2

D28.2

D29.2

D30.2

D31.2

D0.4

D10.3

D11.3

D12.3

D13.3

D14.3

D15.3

D16.3

D17.3

D18.3

D19.3

D20.3

D21.3

D22.3

D23.3

D24.3

D25.3

D26.3

D27.3

D28.3

D29.3

D30.3

D31.3

D0.5

D1.4

D1.5

D2.4

D2.5

D3.4

D3.5

D4.4

D4.5

D5.4

D5.5

D6.4

D6.5

Document Number: 38-02031 Rev. *N

Page 36 of 43

CYP15G0101DXB

CYV15G0101DXB

Table 20. Valid Data Characters (TXCTx[0] = 0, RXSTx[2:0] = 000) (continued)

Data

Byte

Data

Byte

Bits

Current RD

Current RD+

abcdei fghj

Bits

Current RD

abcdei fghj

Current RD+

abcdei fghj

HGF EDCBA

100 00111

100 01000

100 01001

100 01010

100 01011

100 01100

100 01101

100 01110

100 01111

100 10000

100 10001

100 10010

100 10011

100 10100

100 10101

100 10110

100 10111

100 11000

100 11001

100 11010

100 11011

100 11100

100 11101

100 11110

100 11111

110 00000

110 00001

110 00010

110 00011

110 00100

110 00101

110 00110

110 00111

110 01000

110 01001

110 01010

abcdei fghj

HGF EDCBA

101 00111

101 01000

101 01001

101 01010

101 01011

101 01100

101 01101

101 01110

101 01111

101 10000

101 10001

101 10010

101 10011

101 10100

101 10101

101 10110

101 10111

101 11000

101 11001

101 11010

101 11011

101 11100

101 11101

101 11110

101 11111

111 00000

111 00001

111 00010

111 00011

111 00100

111 00101

111 00110

111 00111

111 01000

111 01001

111 01010

Name

D7.4

D8.4

111000 1101 000111 0010

111001 0010 000110 1101

100101 1101 100101 0010

010101 1101 010101 0010

110100 1101 110100 0010

001101 1101 001101 0010

101100 1101 101100 0010

011100 1101 011100 0010

010111 0010 101000 1101

011011 0010 100100 1101

100011 1101 100011 0010

010011 1101 010011 0010

110010 1101 110010 0010

001011 1101 001011 0010

101010 1101 101010 0010

011010 1101 011010 0010

111010 0010 000101 1101

110011 0010 001100 1101

100110 1101 100110 0010

010110 1101 010110 0010

110110 0010 001001 1101

001110 1101 001110 0010

101110 0010 010001 1101

011110 0010 100001 1101

101011 0010 010100 1101

100111 0110 011000 0110

011101 0110 100010 0110

101101 0110 010010 0110

110001 0110 110001 0110

110101 0110 001010 0110

101001 0110 101001 0110

011001 0110 011001 0110

111000 0110 000111 0110

111001 0110 000110 0110

100101 0110 100101 0110

010101 0110 010101 0110

D7.5

D8.5

111000 1010 000111 1010

111001 1010 000110 1010

100101 1010 100101 1010

010101 1010 010101 1010

110100 1010 110100 1010

001101 1010 001101 1010

101100 1010 101100 1010

011100 1010 011100 1010

010111 1010 101000 1010

011011 1010 100100 1010

100011 1010 100011 1010

010011 1010 010011 1010

110010 1010 110010 1010

001011 1010 001011 1010

101010 1010 101010 1010

011010 1010 011010 1010

111010 1010 000101 1010

110011 1010 001100 1010

100110 1010 100110 1010

010110 1010 010110 1010

110110 1010 001001 1010

001110 1010 001110 1010

101110 1010 010001 1010

011110 1010 100001 1010

101011 1010 010100 1010

100111 0001 011000 1110

011101 0001 100010 1110

101101 0001 010010 1110

110001 1110 110001 0001

110101 0001 001010 1110

101001 1110 101001 0001

011001 1110 011001 0001

111000 1110 000111 0001

111001 0001 000110 1110

100101 1110 100101 0001

010101 1110 010101 0001

D9.4

D9.5

D10.4

D11.4

D12.4

D13.4

D14.4

D15.4

D16.4

D17.4

D18.4

D19.4

D20.4

D21.4

D22.4

D23.4

D24.4

D25.4

D26.4

D27.4

D28.4

D29.4

D30.4

D31.4

D0.6

D10.5

D11.5

D12.5

D13.5

D14.5

D15.5

D16.5

D17.5

D18.5

D19.5

D20.5

D21.5

D22.5

D23.5

D24.5

D25.5

D26.5

D27.5

D28.5

D29.5

D30.5

D31.5

D0.7

D1.6

D1.7

D2.6

D2.7

D3.6

D3.7

D4.6

D4.7

D5.6

D5.7

D6.6

D6.7

D7.6

D7.7

D8.6

D8.7

D9.6

D9.7

D10.6

D10.7

Document Number: 38-02031 Rev. *N

Page 37 of 43

CYP15G0101DXB

CYV15G0101DXB

Table 20. Valid Data Characters (TXCTx[0] = 0, RXSTx[2:0] = 000) (continued)

Data

Byte

Data

Byte

Bits

Current RD

Current RD+

abcdei fghj

Bits

Current RD

abcdei fghj

Current RD+

abcdei fghj

HGF EDCBA

110 01011

110 01100

110 01101

110 01110

110 01111

110 10000

110 10001

110 10010

110 10011

110 10100

110 10101

110 10110

110 10111

110 11000

110 11001

110 11010

110 11011

110 11100

110 11101

110 11110

110 11111

abcdei fghj

HGF EDCBA

111 01011

111 01100

111 01101

111 01110

111 01111

111 10000

111 10001

111 10010

111 10011

111 10100

111 10101

111 10110

111 10111

111 11000

111 11001

111 11010

111 11011

111 11100

111 11101

111 11110

111 11111

Name

D11.6

D12.6

D13.6

D14.6

D15.6

D16.6

D17.6

D18.6

D19.6

D20.6

D21.6

D22.6

D23.6

D24.6

D25.6

D26.6

D27.6

D28.6

D29.6

D30.6

D31.6

110100 0110 110100 0110

001101 0110 001101 0110

101100 0110 101100 0110

011100 0110 011100 0110

010111 0110 101000 0110

011011 0110 100100 0110

100011 0110 100011 0110

010011 0110 010011 0110

110010 0110 110010 0110

001011 0110 001011 0110

101010 0110 101010 0110

011010 0110 011010 0110

111010 0110 000101 0110

110011 0110 001100 0110

100110 0110 100110 0110

010110 0110 010110 0110

110110 0110 001001 0110

001110 0110 001110 0110

101110 0110 010001 0110

011110 0110 100001 0110

101011 0110 010100 0110

D11.7

D12.7

D13.7

D14.7

D15.7

D16.7

D17.7

D18.7

D19.7

D20.7

D21.7

D22.7

D23.7

D24.7

D25.7

D26.7

D27.7

D28.7

D29.7

D30.7

D31.7

110100 1110 110100 1000

001101 1110 001101 0001

101100 1110 101100 1000

011100 1110 011100 1000

010111 0001 101000 1110

011011 0001 100100 1110

100011 0111 100011 0001

010011 0111 010011 0001

110010 1110 110010 0001

001011 0111 001011 0001

101010 1110 101010 0001

011010 1110 011010 0001

111010 0001 000101 1110

110011 0001 001100 1110

100110 1110 100110 0001

010110 1110 010110 0001

110110 0001 001001 1110

001110 1110 001110 0001

101110 0001 010001 1110

011110 0001 100001 1110

101011 0001 010100 1110

Document Number: 38-02031 Rev. *N

Page 38 of 43

CYP15G0101DXB

CYV15G0101DXB

Table 21. Valid Special Character Codes and Sequences (TXCTx = Special Character Code or RXSTx[2:0] = 001)^[55,56]

S.C. Byte Name

Cypress

S.C. Byte

Alternate

Current RD

abcdei fghj

Current RD+

abcdei fghj

S.C. Code Name

Bits

HGF EDCBA

S.C. Byte

Bits

Name^[57]

HGF EDCBA

K28.0

C0.0

(C00)

(C01)

(C02)

(C03)

(C04)

(C05)

(C06)

(C07)

(C08)

(C09)

000 00000 C28.0 (C1C)

000 00001 C28.1 (C3C)

000 00010 C28.2 (C5C)

000 00011 C28.3 (C7C)

000 00100 C28.4 (C9C)

000 00101 C28.5 (CBC)

000 00110 C28.6 (CDC)

000 00111 C28.7 (CFC)

000 01000 C23.7 (CF7)

000 01001 C27.7 (CFB)

000 01010 C29.7 (CFD)

000 01011 C30.7 (CFE)

000 11100

001 11100

010 11100

011 11100

100 11100

101 11100

110 11100

111 11100

111 10111

111 11011

111 11101

111 11110

001111 0100

001111 1001

001111 0101

001111 0011

001111 0010

001111 1010

001111 0110

001111 1000

111010 1000

110110 1000

101110 1000

011110 1000

110000 1011

110000 0110

110000 1010

110000 1100

110000 1101

110000 0101

110000 1001

110000 0111

000101 0111

001001 0111

010001 0111

100001 0111

K28.1^[58]

K28.2^[58]

K28.3

K28.4^[58]

K28.5^{[58, 59]}

K28.6^[58]

K28.7^{[58, 60]}

K23.7

C1.0

C2.0

C3.0

C4.0

C5.0

C6.0

C7.0

C8.0

C9.0

K27.7

K29.7

C10.0 (C0A)

C11.0 (C0B)

K30.7

End of Frame Sequence

EOFxx^[61]

C2.1 (C22)

Code Rule Violation and SVS Tx Pattern

001 00010 C2.1

(C22)

001 00010 K28.5,Dn.xxx0

+K28.5,Dn.xxx1

Exception^{[60, 62]}C0.7

(CE0)

(CE1)

(CE2)

111 00000 C0.7

111 00001 C1.7

111 00010 C2.7

(CE0)

(CE1)

(CE2)

111 00000^[66]

111 00001^[66]

111 00010^[66]

100111 1000

001111 1010

110000 0101

011000 0111

001111 1010

110000 0101

K28.5^[63]

C1.7

C2.7

+K28.5^[64]

Running Disparity Violation Pattern

Exception^[65]

C4.7

(CE4)

111 00100 C4.7

(CE4)

111 00100^[66]

110111 0101

001000 1010

Notes

55. All codes not shown are reserved.

56. Notation for Special Character Code Name is consistent with Fibre Channel and ESCON naming conventions. Special Character Code Name is intended to

describe binary information present on I/O pins. Common usage for the name can either be in the form used for describing Data patterns (i.e., C0.0 through

C31.7), or in hex notation (i.e., Cnn where nn = the specified value between 00 and FF).

57. Both the Cypress and alternate encodings may be used for data transmission to generate specific Special Character Codes. The decoding process for received

characters generates Cypress codes or Alternate codes as selected by the DECMODE configuration input.

58. These characters are used for control of ESCON interfaces. They can be sent as embedded commands or other markers when not operating using ESCON protocols.

59. The K28.5 character is used for framing operations by the receiver. It is also the pad or fill character transmitted to maintain the serial link when no user data is available.

60. Care must be taken when using this Special Character code. When a K28.7(C7.0) or SVS(C0.7) is followed by a D11.x or D20.x,an alias K28.5 sync character

is created. These sequences can cause erroneous framing and should be avoided while RFEN = HIGH.

61. C2.1 = Transmit either K28.5+ or +K28.5 as determined by Current RD and modify the Transmission Character that follows, by setting its least significant bit

to 1 or 0. If Current RD at the start of the following character is plus (+) the LSB is set to 0, and if Current RD is minus () the LSB becomes 1. This modification

allows construction of X3.230 “EOF” frame delimiters wherein the second data byte is determined by the Current RD.

For example, to send “EOFdt” the controller could issue the sequence C2.1D21.4 D21.4D21.4, and the HOTLink Transmitter will send either

K28.5D21.4D21.4D21.4 or K28.5D21.5 D21.4D21.4 based on Current RD. Likewise to send “EOFdti” the controller could issue the sequence

C2.1D10.4D21.4D21.4, and the HOTLink Transmitter will send either K28.5D10.4D21.4 D21.4 or K28.5D10.5D21.4 D21.4 based on Current RD.

The receiver will never output this Special Character, since K28.5 is decoded as C5.0, C1.7, or C2.7, and the subsequent bytes are decoded as data.

62. C0.7 = Transmit a deliberate code rule violation. The code chosen for this function follows the normal Running Disparity rules. The receiver will only output this

Special Character if the Transmission Character being decoded is not found in the tables.

63. C1.7 = Transmit Negative K28.5 (K28.5+) disregarding Current RD. The receiver will only output this Special Character if K28.5 is received with the wrong

running disparity. The receiver will output C1.7 if K28.5 is received with RD+, otherwise K28.5 is decoded as C5.0 or C2.7.

64. C2.7 = Transmit Positive K28.5 (+K28.5) disregarding Current RD. The receiver will only output this Special Character if K28.5 is received with the wrong

running disparity. The receiver will output C2.7 if +K28.5 is received with RD, otherwise K28.5 is decoded as C5.0 or C1.7.

65. C4.7 = Transmit a deliberate code rule violation to indicate a Running Disparity violation. The receiver will only output this Special Character if the Transmission

Character being decoded is found in the tables, but Running Disparity does not match. This might indicate that an error occurred in a prior byte.

66. Supported only for data transmission. The receive status for these conditions will be reported by specific combinations of receive status bits.

Document Number: 38-02031 Rev. *N

Page 39 of 43

CYP15G0101DXB

CYV15G0101DXB

Ordering Information

Speed

Ordering Code

Package Name

BB100

Package Type

Operating Range

Commercial

Industrial

Standard CYP15G0101DXB-BBXC

Standard CYP15G0101DXB-BBXI

Standard CYV15G0101DXB-BBXC

Pb-free 100-ball Grid Array

BB100

Commercial

Ordering Code Definitions

CY

X

X15G0101

-

BB

DXB

X

X = Temperature Grade = C or I (C = Commercial; I = Industrial)

X = Pb-free

BB = 100-ball BGA

Fixed Value

Part Identifier

Company ID: CY = Cypress

Document Number: 38-02031 Rev. *N

Page 40 of 43

CYP15G0101DXB

CYV15G0101DXB

Package Diagram

Figure 3. 100-ball Thin Ball Grid Array (11 × 11 × 1.4 mm) BB100

51-85107 *D

Acronyms

Document Conventions

Table 23. Units of Measure

The following table lists the acronyms that are used in this

document.

Acronym

Description

Table 22. Acronyms Used in this Datasheet

°C

k

µA

µs

mA

ms

mV

nA



degree Celsius

kilohm

Acronym

Description

ball grid array

BGA

BIST

I/O

microampere

microsecond

milliampere

millisecond

millivolt

built-in self test

input/output

JTAG

PLL

joint test action group

phase-locked loop

test mode select

test data out

TMS

TDO

TDI

nanoampere

ohm

test data in

pF

V

picofarad

volt

W

watt

Document Number: 38-02031 Rev. *N

Page 41 of 43

CYP15G0101DXB

CYV15G0101DXB

Document History Page

Document Title: CYP15G0101DXB/CYV15G0101DXB Single-channel HOTLink II™ Transceiver

Document Number: 38-02031

Submission Orig. of

Revision

ECN

Description of Change

Date

Change

**

113123

119704

05/20/02

10/30/02

TPS

New Data Sheet

*A

LNM

Changed TXPER description

Changed TXCLKO description

Changed RXCKSEL to include RXCLKC+

Removed disparity reference from RFMODE

Removed the LOW setting for FRAMCHAR and related references

Removed references to ATM transport

Changed the I_OSTboundary values

Changed V_ODIFand V_OLCfor CML output

Changed the t_TXCLKRand t_TXCLKFmin. values

Changed t_TXDS, t_TXDH, t_TREFDS, and t_TREFDH

Changed t_REFDV–, t_REFCDV–, and t_REFCDV+

Changed the JTAG ID from 0C804069 to 1C804069

Added a section for characterization and standards compliance

Changed I/O type of RXCLKC in I/O coordinates table

*B

*C

122209

122546

12/28/02

02/13/03

RBI

Minor Change Document Control corrected Document History Page

CGX

Changed Minimum tRISE/tFALL for CML

Changed tRXLOCK

Changed tDJ, tRJ

Changed tJTOL

Changed tTXLOCK

Changed tRXCLKH, tRXCLKL

Changed tTXCLKOD+, tTXCLKOD-

Changed Power Specs

Changed verbiage...Paragraph: Clock/Data Recovery

Changed verbiage...Paragraph: Range Control

Added Power-up Requirements

*D

124994

04/15/03

POT

Changed CYP15G0101DXB to CYP(V)15G0101DXB type corresponding to

the Video-compliant parts

Reduced the lower limit of the serial signaling rate from 200 Mbaud to

195 Mbaud and changed the associated specifications accordingly

*E

*F

128366

128835

7/3/03

PDS

KKV

Revised the value of t_RREFDV,t_{REFADV+ and}t_REFCDV+

7/31/03

Minor change: corrections due to editorial error - old file used for *E revision

(reestablishing *D changes)

*G

131898

12/10/03

PDS

When TXCKSEL = MID or HIGH, TXRATE = HIGH is an invalid mode. Made

appropriate changes to reflect this invalid condition

Removed requirement of AC coupling for Serial I/Os for interfacing with

LVPECL I/Os

Changed LFI to Asynchronous output

Expanded the CDR Range Controller’s permissible frequency offset between

incoming serial signaling rate and Reference clock from ±200-PPM to

±1500-PPM (changed parameter t_REFRX

)

*H

*I

211461

230621

338721

See ECN

KKV

LAR

SUA

Minor change: Package diagram isn’t legible in pdf

Updated package information in features list to reflect correct package

*J

Added CYW15G0101DXB part number for OBSAI RP3 compliance to support

operating data rate upto 1540 MBaud. Made changes to reflect OBSAI RP3

and CPR compliance. Added Pb-Free Package option for all parts listed in the

datasheet.

Changed MBd to MBaud in SPDSEL pin description

*K

2898355

03/24/2010

CGX

Removed inactive parts from Ordering Information.

Updated Packaging Information.

Document Number: 38-02031 Rev. *N

Page 42 of 43

CYP15G0101DXB

CYV15G0101DXB

Document Title: CYP15G0101DXB/CYV15G0101DXB Single-channel HOTLink II™ Transceiver

Document Number: 38-02031

Submission Orig. of

Revision

ECN

Description of Change

Date

Change

*L

3053045

10/08/2010

CGX

Updated Ordering Information and added Ordering Code Definitions.

Added Acronyms and Document Conventions.

Minor edits and updated in new template.

*M

*N

3243269

3589088

04/28/2011

04/17/2012

SAAC

Removed the following part numbers from the Ordering Information on page 40

since the parts are no longer active. (CDT 98703)

a) CYP15G0101DXB-BBI

b) CYV15G0101DXB-BBI

c) CYW15G0101DXB-BBXI

Removed all references to the part CYW15G0101DXB from the datasheet

(CDT 98703).

Removed the part number CYP15G0101DXB-BBC from the Ordering Infor-

mation on page 40 as the part is no longer active.

Updated Package Diagram 51-85107 (from Rev *C to *D).

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

Products

Automotive

cypress.com/go/automotive

cypress.com/go/clocks

cypress.com/go/interface

cypress.com/go/powerpsoc

cypress.com/go/plc

PSoC Solutions

Clocks & Buffers

Interface

psoc.cypress.com/solutions

PSoC 1 | PSoC 3 | PSoC 5

Lighting & Power Control

Memory

cypress.com/go/memory

cypress.com/go/image

cypress.com/go/psoc

Optical & Image Sensing

PSoC

Touch Sensing

USB Controllers

Wireless/RF

cypress.com/go/touch

cypress.com/go/USB

cypress.com/go/wireless

any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for

medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress

integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 38-02031 Rev. *N

Revised April 17, 2012

Page 43 of 43

HOTLink is a registered trademark, and HOTLink II and MultiFrame are trademarks, of Cypress Semiconductor Corporation. CPRI is a trademark of Siemens AG. IBM and ESCON are registered

trademarks, and FICON is a trademark, of International Business Machines.

All products and company names mentioned in this document may be the trademarks of their respective holders.

厂商	型号	描述	页数
NIDEC	CYP	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0200MB	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0200MC	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0200TB	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0200TC	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0201MB	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0201MC	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0201TB	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0201TC	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0202MB	[ PIANO SWITCHES (FULL PITCH) ]	5 页