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AZV99_12

型号：

AZV99_12

描述：

PECL / LVDS振荡器增益级和缓冲区，可选择启用[ PECL/LVDS Oscillator Gain Stage & Buffer with Selectable Enable ]

品牌：

AZM[ ARIZONA MICROTEK, INC ]

页数：

14 页

PDF大小：

745 K

下载PDF手册
AZV99  
www.azmicrotek.com  
PECL/LVDS Oscillator Gain Stage &  
Buffer with Selectable Enable  
FEATURES  
DESCRIPTION  
• Minimizes External  
Components  
The AZV99 is a specialized oscillator gain stage with an LVDS output  
buffer including an enable. The selectable enable input allows continuous  
oscillator operation by only controlling the QHG /Q¯ HG outputs.  
• Selectable Enable Polarity and  
Threshold (CMOS or PECL)  
• 3V to 5.5V Power Supply  
• Similar Operation as  
AZ100LVEL16VT except  
with LVDS Outputs  
The AZV99 provides adjustable internal pull-down current sources for the  
Q/Q¯ outputs. Internal input biasing further reduces the number of needed  
external components  
BLOCK DIAGRAM  
APPLICATIONS  
•
Crystal or saw oscillators that  
require minimal external  
components  
PACKAGE AVAILABILITY  
•
•
•
•
MLP8  
MLP16  
MSOP8  
Green/RoHS Compliant/Pb-Free  
Order Number  
AZV99NG 1  
AZV99NBG 1  
AZV99NDG 1  
AZV99LG 1  
Package  
MLP8  
Marking  
V1G <Date Code> 2  
V8G <Date Code> 2  
V2G <Date Code> 2  
AZMG <Date Code> 2  
AZ+V99 2  
MLP8  
MLP8  
MLP16  
MSOP8  
AZV99T+ 1  
1
2
Tape & Reel - Add 'R1' at end of PN for 7in (1k parts), 'R2' (2.5k) for 13in  
See www.azmicrotek.com for date code format  
www.azmicrotek.com  
+1-480-962-5881  
1630 S Stapley Dr, Suite 127  
Mesa, AZ 85204 USA  
Request a Sample  
May 2012, Rev 2.0  
Arizona Microtek, Inc.  
AZV99  
PECL/LVDS Oscillator Gain Stage &  
Buffer with Selectable Enable  
PIN DESCRIPTION AND CONFIGURATION  
Table 1 - Pin Description for AZV99N  
Pin  
1
Name  
Q¯  
Type  
Output  
Input  
Function  
Inverting PECL Output  
Data Input  
VCC  
QHG  
1
2
3
Q
D
8
7
2
D
Leave Pad  
open or  
connect to  
VEE  
3
VBB  
EN  
Output  
Input  
Reference Voltage  
Output Enable  
4
VBB  
EN  
6
5
5
VEE  
Q¯HG  
QHG  
VCC  
Power  
Output  
Output  
Power  
Negative Supply  
Inverting LVDS Output  
LVDS Output  
QHG  
VEE  
6
4
7
8
Positive Supply  
Table 2 - Pin Description for AZV99NB  
Pin  
1
Name  
D
Type  
Input  
Function  
Data Input  
D
1
2
3
Q
8
7
2
VBB  
E¯N¯  
Output  
Input  
Reference Voltage  
Output Enable  
Leave Pad  
open or  
connect to  
VEE  
VBB  
3
VCC  
QHG  
QHG  
4
VEE  
Q¯HG  
QHG  
VCC  
Q¯  
Power  
Output  
Output  
Power  
Output  
Negative Supply  
Inverting LVDS Output  
LVDS Output  
6
5
EN  
5
6
VEE  
4
7
Positive Supply  
Inverting PECL Output  
8
Table 3 - Pin Description for AZV99ND  
Pin  
1
Name  
Q¯  
Type  
Output  
Input  
Function  
Inverting PECL Output  
Data Input  
VCC  
QHG  
1
2
3
Q
D
8
7
2
D
Leave Pad  
open or  
connect to  
VEE  
3
VBB  
E¯N¯  
Output  
Input  
Reference Voltage  
Output Enable  
4
VBB  
EN  
6
5
5
VEE  
Q¯HG  
QHG  
VCC  
Power  
Output  
Output  
Power  
Negative Supply  
Inverting LVDS Output  
LVDS Output  
QHG  
VEE  
6
4
7
8
Positive Supply  
www.azmicrotek.com  
+1-480-962-5881  
2
Request a Sample  
May 2012, Rev 2.0  
Arizona Microtek, Inc.  
AZV99  
PECL/LVDS Oscillator Gain Stage &  
Buffer with Selectable Enable  
Table 4 - Pin Description for AZV99L  
Pin  
1
Name  
NC  
D
Type  
-
Function  
N/A  
2
Input  
Input  
Output  
Input  
-
Data Input  
3
D¯  
Inverting Data Input  
Reference Voltage  
Output Enable  
N/A  
4
VBB  
EN  
NC  
VEE  
NC  
5
6
7
Power  
-
Negative Supply  
N/A  
8
9
EN-SEL  
Q¯HG  
QHG  
CS-SEL  
VCC  
Input  
Output  
Output  
Input  
Enable Polarity Select  
Inverting LVDS Output  
LVDS Output  
10  
11  
12  
13  
14  
15  
16  
Current Source Select  
Positive Supply  
Power  
-
NC  
N/A  
Q
Output  
Output  
PECL Output  
Q¯  
Inverting PECL Output  
Table 5 - Pin Description for AZV99T  
Pin  
1
Name  
Q¯  
Type  
Output  
Input  
Function  
Inverting PECL Output  
Data Input  
1
Q
D
8
7
6
5
VCC  
QHG  
QHG  
VEE  
2
D
3
VBB  
EN  
Output  
Input  
Reference Voltage  
Output Enable  
2
3
4
4
5
VEE  
Q¯HG  
QHG  
VCC  
Power  
Output  
Output  
Power  
Negative Supply  
Inverting LVDS Output  
LVDS Output  
VBB  
EN  
6
7
8
Positive Supply  
www.azmicrotek.com  
+1-480-962-5881  
3
Request a Sample  
May 2012, Rev 2.0  
Arizona Microtek, Inc.  
AZV99  
PECL/LVDS Oscillator Gain Stage &  
Buffer with Selectable Enable  
ENGINEERING NOTES  
FUNCTIONALITY MLP16 PACKAGE (AZV99L)  
The AZV99L provides a selectable enable (EN). Enable polarity and threshold can be selected to accommodate either  
CMOS/TTL or PECL input levels. If enable pull-up is desired in the CMOS/TTL mode, an external ≤ 20kΩ resistor  
connecting EN to VCC will override the on-chip pull-down resistor.  
Outputs Q/Q¯ each have a selectable on-chip pull-down current source. External resistors may also be used to increase  
pull-down current to a maximum of 25mA (includes internal on-chip current source).  
The AZV99 also provides input biasing which is accomplished with a VBB and 470Ω internal resistors from D to VBB and D¯ to  
VBB. The VBB pin supports 1.5mA sink/source current. VBB should be bypassed to ground with a 0.01µF capacitor.  
FUNCTIONALITY MLP8 PACKAGE (AZV99NB & AZV99ND)  
The AZV99NB and AZV99NB provide a PECL/ECL level enable input (¯E¯N¯). When the ¯E¯N¯ input is LOW, the Q¯ and  
QHG/Q¯HG outputs pass data from the inputs. When ¯E¯N¯ is HIGH, the Q¯ output continues to pass data while the QHG output  
is forced high and the Q¯HG output is forced low.  
Only the Q¯ output operates with a current source (4 mA) to VEE. This is accomplished by internal bonding of CS-SEL. An  
external resistor may also be used to increase pull-down current to a maximum of 25mA (includes 4mA on-chip current  
source).  
The AZV99NB and AZV99ND versions operate with a single ended data input (D). The D¯ input is internally bonded  
directly to the VBB pin bypassing the 470Ω bias resistor.  
FUNCTIONALITY MLP8 PACKAGE (AZV99N) & MSOP8 PACKAGE (AZV99T)  
The AZV99N and AZV99T provide a CMOS/TTL level enable input (EN). When the EN input is HIGH, the Q¯ and  
QHG/Q¯HG outputs pass data from the inputs. When EN is LOW, the Q¯ output continues to pass data while the QHG output is  
forced high and the Q¯HG output is forced low.  
Only the Q¯ output operates with a current source (4 mA) to VEE. This is accomplished by internal bonding of CS-SEL. An  
external resistor may also be used to increase pull-down current to a maximum of 25mA (includes 4mA on-chip current  
source).  
The MSOP8 (T) and MLP8 (N) AZV99 operate with a single ended data input (D). The D¯ input is internally bonded  
directly to the VBB pin bypassing the 470Ω bias resistor.  
www.azmicrotek.com  
+1-480-962-5881  
4
Request a Sample  
May 2012, Rev 2.0  
Arizona Microtek, Inc.  
AZV99  
PECL/LVDS Oscillator Gain Stage &  
Buffer with Selectable Enable  
Table 6 – Enable Truth Table  
Q/ Q  
EN-SEL  
QHG  
EN/ EN  
Q
HG  
PECL Low, VEE or NC  
PECL High or VCC  
Data  
Data  
Data  
Data  
Data  
High  
High  
Data  
Data  
Low  
Low  
Data  
NC  
CMOS/TTL Low, VEE or NC  
1
VEE  
2
CMOS/TTL High or VCC  
1
2
EN-SEL connections must be less than 1Ω.  
An external ≤20kΩ pull-up resistor between EN and VCC ensures a High when the  
EN pin is not driven.  
D
EN-SEL OPEN  
(PECL)  
EN  
{
(CMOS)  
EN-SEL SHORTED TO VEE  
Q
Q
QHG  
QHG  
Figure 1 – Timing Diagram  
Table 7 - Current Source Truth Table  
CS-SEL  
Q
Q
NC  
4mA typ  
8mA typ  
0
4mA typ  
8mA typ  
4mA typ  
1
VEE  
1
VCC  
1
Connection must be less than 1Ω  
www.azmicrotek.com  
+1-480-962-5881  
5
Request a Sample  
May 2012, Rev 2.0  
Arizona Microtek, Inc.  
AZV99  
PECL/LVDS Oscillator Gain Stage &  
Buffer with Selectable Enable  
AC Coupling Capacitor  
C2  
R1  
See table  
EL16VO  
Front End  
3.3 or 5 V  
CMOS  
D
R2  
470 Ω  
D
VBB  
C1  
0.01 μF  
Figure 2 - Application circuit for CMOS inputs  
Table 8 – Recommended Component Values for CMOS Single Ended Inputs  
R11 Value  
Input Type  
AC Coupled (C2 in circuit)  
DC Coupled (C2 shorted)  
3.3 V CMOS  
5.0 V CMOS  
1.1 kΩ  
1.6 kΩ  
2.0 kΩ  
3.3 kΩ  
1. R1 should be chosen so that the input swing on the D input with respect to D¯  
is in the range of ±80 to ±1000 mV, per the AC Characteristics table and the  
D input is < ±750 mV with respect to VBB.  
www.azmicrotek.com  
+1-480-962-5881  
6
Request a Sample  
May 2012, Rev 2.0  
Arizona Microtek, Inc.  
AZV99  
PECL/LVDS Oscillator Gain Stage &  
Buffer with Selectable Enable  
Figure 3 - S11, 50Ω AC load  
Figure 4 - S12, 50Ω AC load  
www.azmicrotek.com  
+1-480-962-5881  
7
Request a Sample  
May 2012, Rev 2.0  
Arizona Microtek, Inc.  
AZV99  
PECL/LVDS Oscillator Gain Stage &  
Buffer with Selectable Enable  
Figure 5 – S21, 50Ω AC load  
Figure 6 – S22, 50Ω AC load  
www.azmicrotek.com  
+1-480-962-5881  
8
Request a Sample  
May 2012, Rev 2.0  
Arizona Microtek, Inc.  
AZV99  
PECL/LVDS Oscillator Gain Stage &  
Buffer with Selectable Enable  
PERFORMANCE DATA  
Table 9 – Absolute Maximum Ratings  
Absolute Maximum Ratings are those values beyond which device life may be impaired.  
Symbol  
VCC  
Characteristic  
PECL Power Supply  
PECL Input Voltage  
D/D¯ Input Voltage  
Condition  
Rating  
0 to + 6.0  
0 to + 6.0  
±0.75  
50  
Unit  
V
VEE = 0V  
VI  
VEE = 0V  
V
VD/D¯  
Referenced to VBB  
V
Continuous Q/Q¯  
Surge Q/Q¯  
100  
IOUT  
Output Current  
mA  
Continuous QHG/Q¯HG  
5
Surge QHG/Q¯HG  
10  
TA  
Operating Temperature Range  
Storage Temperature Range  
-
-
-
-
-
-40 to +85  
-65 to +150  
2500  
°C  
°C  
V
TSTG  
ESDHBM  
ESDMM  
ESDCDM  
Human Body Model Electro Static Discharge  
Machine Model Electro Static Discharge  
Charged Device Model Electro Static Discharge  
200  
V
2000  
V
Table 10 - 100K LVPECL DC Characteristics  
100K LVPECL DC Characteristics (VEE = GND, VCC = +3.3V)  
-40°C  
0°C  
25°C  
85°C  
Symbol  
Characteristic  
Unit  
Min  
2255  
1375  
1910  
Max  
2465  
1745  
2050  
2560  
Min  
2275  
1400  
1910  
Max  
2465  
1680  
2050  
Min  
2275  
1400  
1910  
Max  
2465  
1680  
2050  
Min  
2275  
1400  
1910  
Max  
2465  
1680  
2050  
VOH  
VOL  
VBB  
Output HIGH Voltage1,2  
Output LOW Voltage1,2  
Reference Voltage1  
mV  
mV  
mV  
mV  
mV  
Input HIGH Voltage D/D¯, EN (ECL)3 2135  
2135  
2000  
1400  
GND  
2560  
VCC  
2135  
2000  
1400  
2560  
VCC  
2135  
2000  
1400  
GND  
2560  
VCC  
VIH  
Input HIGH Voltage EN (CMOS)4  
2000  
1400  
GND  
VCC  
Input LOW Voltage D/D¯, EN (ECL)3  
Input LOW Voltage EN (CMOS)4  
Input HIGH Current EN  
1825  
800  
1825  
800  
1825  
800  
1825  
800  
mV  
mV  
µA  
µA  
µA  
mA  
VIL  
IIH  
IIL  
GND  
150  
150  
150  
150  
Input LOW Current EN (ECL)  
Input LOW Current EN (CMOS)  
Power Supply Current2  
0.5  
0.5  
0.5  
0.5  
-150  
-150  
-150  
-150  
IEE  
48  
48  
48  
54  
1. For supply voltages other that 3.3V, use the ECL table values and ADD supply voltage value.  
2. Specified with VEEP and CS-SEL NC, QHG/Q¯HG terminated through 50Ω resistors to VCC - 2V.  
3. EN-SEL = NC.  
4. EN-SEL = VCC or VEE.  
www.azmicrotek.com  
+1-480-962-5881  
9
Request a Sample  
May 2012, Rev 2.0  
Arizona Microtek, Inc.  
AZV99  
PECL/LVDS Oscillator Gain Stage &  
Buffer with Selectable Enable  
Table 11 - 100K PECL DC Characteristics  
100K PECL DC Characteristics (VEE = GND, VCC = +5.0V)  
-40°C  
0°C  
25°C  
85°C  
Min  
Symbol  
Characteristic  
Unit  
Min  
3955  
3075  
3610  
Max  
4165  
3445  
3750  
4260  
Min  
3975  
3100  
3610  
Max  
4165  
3380  
3750  
4260  
Min  
3975  
3100  
3610  
Max  
4165  
3380  
3750  
4260  
Max  
4165  
3380  
3750  
4260  
VOH  
VOL  
VBB  
Output HIGH Voltage1,2  
Output LOW Voltage1,2  
Reference Voltage1  
mV  
mV  
mV  
mV  
mV  
3975  
3100  
3610  
Input HIGH Voltage D/D¯, EN (ECL)3 3835  
3835  
2000  
3100  
GND  
3835  
2000  
3100  
3835  
2000  
3100  
GND  
VIH  
Input HIGH Voltage EN (CMOS)4  
2000  
3100  
GND  
VCC  
VCC  
VCC  
VCC  
Input LOW Voltage D/D¯, EN (ECL)3  
Input LOW Voltage EN (CMOS)4  
Input HIGH Current EN  
mV  
mV  
µA  
µA  
µA  
mA  
3525  
3525  
3525  
3525  
VIL  
IIH  
IIL  
800  
150  
800  
150  
GND  
800  
150  
800  
150  
Input LOW Current EN (ECL)  
Input LOW Current EN (CMOS)  
Power Supply Current2  
0.5  
0.5  
0.5  
0.5  
-150  
-150  
-150  
-150  
IEE  
48  
48  
48  
54  
1. For supply voltages other that 5.0V, use the ECL table values and ADD supply voltage value.  
2. Specified with VEEP and CS-SEL NC, QHG/Q¯HG terminated through 50Ω resistors to VCC - 2V.  
3. EN-SEL = NC.  
4. EN-SEL = VCC or VEE.  
Table 12 – LVDS DC Characteristics  
LVDS DC Characteristics for QHG/Q¯HG Outputs1 (VEE = GND, VCC = +3.0V to +5.5V)  
-40°C  
0°C  
25°C  
85°C  
Symbol  
Characteristic  
Unit  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
VOH  
VOL  
Output HIGH Voltage  
Output LOW Voltage  
Output Common Mode Voltage2  
Change in Common Mode Voltage3  
Single-Ended Output Swing  
Differential Output Swing  
1600  
1600  
1600  
1600  
mV  
mV  
mV  
mV  
mV  
mV  
900  
1125  
-50  
900  
1125  
-50  
900  
1125  
-50  
900  
1125  
-50  
VOC  
1375  
50  
1375  
50  
1375  
50  
1375  
50  
∆VOC  
VOUT  
250  
500  
450  
900  
250  
500  
450  
900  
250  
500  
450  
900  
250  
500  
450  
900  
VDIFF_OUT  
1. Specified with 100Ω resistor connecting QHG and Q¯HG together.  
2. Common mode voltage is the center voltage between QHG and Q¯HG during a steady state.  
3. Change in common mode voltage is the difference between common mode voltages at opposite binary states.  
www.azmicrotek.com  
+1-480-962-5881  
10  
Request a Sample  
May 2012, Rev 2.0  
Arizona Microtek, Inc.  
AZV99  
PECL/LVDS Oscillator Gain Stage &  
Buffer with Selectable Enable  
Table 13 – AC Characteristics  
AC Characteristics (VEE = -3.0V to -5.5V; VCC=GND or VEE=GND; VCC = +3.0V to +5.5V)  
-40°C  
0°C  
25°C  
85°C  
Symbol  
Characteristic  
Unit  
Min Typ Max Min Typ Max Min Typ Max Min Typ Max  
Propagation Delay  
tPLH/tPHL  
D to Q/Q¯1  
400  
450  
20  
400  
450  
20  
400  
450  
20  
400  
450  
20  
ps  
ps  
ps  
2
D to QHG/Q¯HG  
tSKEW  
Duty Cycle Skew3  
Input Swing4  
Differential  
5
5
5
5
Vpp (AC)  
80  
1000  
80  
1000  
80  
1000  
80  
1000 mV  
2000 mV  
Single Ended  
150  
2000 150  
2000 150  
2000 150  
Output Rise/Fall1,2  
(20%-80%)  
Q/Q¯1  
100  
180  
260  
280  
100  
180  
260  
280  
100  
180  
260  
280  
100  
180  
260  
280  
ps  
ps  
tr/tf  
2
QHG/Q¯HG  
1. Specified with CS-SEL connected to VEE and Q/Q¯ with AC coupled 50Ω loads.  
2. Specified with 100Ω resistor connecting QHG and Q¯HG together.  
3. Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device.  
4. The peak-to-peak differential input swing is the range for which AC parameters guaranteed. VD and VD¯ must remain within the  
range of ±750 mV with respect to VBB.  
www.azmicrotek.com  
+1-480-962-5881  
11  
Request a Sample  
May 2012, Rev 2.0  
Arizona Microtek, Inc.  
AZV99  
PECL/LVDS Oscillator Gain Stage &  
Buffer with Selectable Enable  
PACKAGE DIAGRAM  
MLP8  
Green/RoHS compliant/Pb-Free  
MSL=1  
www.azmicrotek.com  
+1-480-962-5881  
12  
Request a Sample  
May 2012, Rev 2.0  
Arizona Microtek, Inc.  
AZV99  
PECL/LVDS Oscillator Gain Stage &  
Buffer with Selectable Enable  
PACKAGE DIAGRAM  
MLP16  
Green/RoHS compliant/Pb-Free  
MSL=1  
www.azmicrotek.com  
+1-480-962-5881  
13  
Request a Sample  
May 2012, Rev 2.0  
Arizona Microtek, Inc.  
AZV99  
PECL/LVDS Oscillator Gain Stage &  
Buffer with Selectable Enable  
PACKAGE DIAGRAM  
MSOP8  
Green/RoHS compliant/Pb-Free  
MSL=1  
Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice.  
Arizona Microtek, Inc. makes no warranty, representation or guarantee regarding the suitability of its products for  
any particular purpose, nor does Arizona Microtek, Inc. assume any liability arising out of the application or use of  
any product or circuit and specifically disclaims any and all liability, including without limitation special,  
consequential or incidental damages. Arizona Microtek, Inc. does not convey any license rights nor the rights of  
others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems  
intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc.  
product could create a situation where personal injury or death may occur. Should Buyer purchase or use Arizona  
Microtek, Inc. products for any such unintended or unauthorized application, Buyer shall indemnify and hold  
Arizona Microtek, Inc. and its officers, employees, subsidiaries, affiliates, and distributors harmless against all  
claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of  
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that  
Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part.  
www.azmicrotek.com  
+1-480-962-5881  
14  
Request a Sample  
May 2012, Rev 2.0  
厂商 型号 描述 页数 下载

DIODES

 		AZV3001 [ Single/Dual Channel Low Voltage Push-Pull Output Comparators ] 11 页

DIODES

 		AZV3001FZ4-7 [ Single/Dual Channel Low Voltage Push-Pull Output Comparators ] 11 页

DIODES

 		AZV3002 [ Single/Dual Channel Low Voltage Push-Pull Output Comparators ] 11 页

DIODES

 		AZV3002RL-7 [ Single/Dual Channel Low Voltage Push-Pull Output Comparators ] 11 页

DIODES

 		AZV3002S-13 [ Single/Dual Channel Low Voltage Push-Pull Output Comparators ] 11 页

BCDSEMI

 		AZV321 单一的低电压轨到轨输出运算放大器[ SINGLE LOW VOLTAGE RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIER ] 13 页

BCDSEMI

 		AZV321KSTR-E1 单一的低电压轨到轨输出运算放大器[ SINGLE LOW VOLTAGE RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIER ] 13 页

BCDSEMI

 		AZV321KSTR-G1 单一的低电压轨到轨输出运算放大器[ SINGLE LOW VOLTAGE RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIER ] 13 页

BCDSEMI

 		AZV321KTR-E1 单一的低电压轨到轨输出运算放大器[ SINGLE LOW VOLTAGE RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIER ] 13 页

BCDSEMI

 		AZV321KTR-G1 单一的低电压轨到轨输出运算放大器[ SINGLE LOW VOLTAGE RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIER ] 13 页

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