CYRF89235-40LTXC,PDF,CYRF89235-40LTXC PDF资料,Datasheet,下载CYRF89235-40LTXC技术资料

CYRF89235

PRoC™ USB

❐ Crystal-less oscillator with support for an external crystal or

PRoC-USB Features

■ Single Device, Two Functions

❐ 8-bit, flash based USB peripheral MCU function and 2.4-GHz

radio transceiver function in a single device

resonator

❐ Internal ±5.0% 6, 12, or 24 MHz main oscillator (IMO):

• 0.25% accuracy with oscillator lock to USB data, no

external components required

■ RF Attributes

❐ Fully integrated 2.4-GHz radio on a chip

❐ 1-Mbps over-the-air data rate

• Internal low-speed oscillator (ILO) at 32 kHz for watchdog

and sleep. The frequency range is 19 to 50 kHz with a

32-kHz typical value

■ Programmable pin configurations.

❐ Transmit power typical: 0 dBm

❐ Receive sensitivity typical: –87 dBm

❐ 1 µA typical current consumption in sleep state

❐ Closed-loop frequency synthesis

❐ Supports frequency-hopping spread spectrum

❐ Up to 13 general-purpose I/Os (GPIOs)

❐ 25 mA sink current on all GPIO

• 60 mA total sink current on Even port pins and 60 mA total

sink current on Odd port pins

❐ On-chip packet framer with 64-byte first in first out (FIFO)

• 120 mA total sink current on all GPIOs

❐ Pull-up, High Z, open drain, CMOS drive modes on all GPIO

❐ CMOS drive mode A –5 mA source current on ports 0 and 1

and 1 mA on port 2

data buffer

❐ Built-in auto-retry-acknowledge protocol simplifies usage

❐ Built-in cyclic redundancy check (CRC), forward error

correction (FEC), data whitening

❐ Supports DC ~ 12-MHz SPI bus interface

❐ Additional outputs for interrupt request (IRQ) generation

❐ Digital readout of received signal strength indication (RSSI)

• 20 mA total source current on all GPIOs

❐ Low dropout voltage regulator for Port 1 pins:

• Programmable to output 3.0, 2.5, or 1.8 V

❐ Selectable, regulated digital I/O on Port 1

❐ Configurable input threshold for Port 1

❐ Hot-swappable Capability on Port 1

■ Full-Speed USB (12 Mbps)

❐ Eight unidirectional endpoints

❐ One bidirectional control endpoint

❐ USB 2.0-compliant

■ MCU Attributes

❐ Powerful Harvard-architecture processor

❐ M8C processor speeds running up to 24 MHz

❐ Low power at high processing speeds

❐ Interrupt controller

❐ 1.9 V to 3.6V operating voltage without USB

❐ Operating voltage with USB enabled:

• 3.15 V to 3.45 V when supply voltage is around 3.3 V

❐ Commercial temperature range: 0 °C to +70 °C

■ Flexible on-chip memory

❐ Dedicated 512 bytes buffer

❐ No external crystal required

■ Additional system resources

❐ Configurable communication speeds

❐ I²C slave:

❐ 32 KB flash program storage:

• Selectable to 50 kHz, 100 kHz, or 400 kHz

• 50,000 erase and write cycles

• Flexible protection modes

• Implementation requires no clock stretching

• Implementation during sleep modes with less than 100 A

• Hardware address detection

❐ Up to 2048 bytes SRAM data storage

❐ In-system serial programming (ISSP)

■ Complete development tools

❐ SPI master and SPI slave:

• Configurable between 46.9 kHz and 12 MHz

❐ Three 16-bit timers

❐ 10-bit ADC used to monitor battery voltage or other signals

with external components

❐ Watchdog and sleep timers

❐ Integrated supervisory circuit

❐ Free development tool PSoC Designer™

❐ Full-featured, in-circuit emulator and programmer

❐ Full-speed emulation

❐ Complex breakpoint structure

❐ 128-KB trace memory

■ Precision, programmable clocking

Cypress Semiconductor Corporation

Document Number: 001-77748 Rev. *F

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised May 15, 2013

CYRF89235

PRoC-USB Logical Block Diagram

Port 2 Port 1 Port 0

Prog. LDO

enCoRe V

CORE

System Bus

SRAM

2048 Bytes

32K Flash

(M8C)

SROM

CPU Core

Sleep and

Watchdog

Interrupt

Controller

6/12/24 MHz Internal Main Oscillator

V

IN

V_OUT

V_{DD_IO}

WIRELESSUSB NL

SYSTEM

GFSK

LDO Linear

Regulator

Modulator

PKT

PA

FIFO

ANT

VCO

Synthesizer

ANTb

RST_n

Pwr/ Reset

BRCLK

Receive

GFSK

Demodulator

X

Image

Xtal Osc

LNA+BPF

Rej. Mxr.

XTALi

XTALo

POR and LVD

System Resets

Full

Speed

USB

I2C Slave/SPI

Master-Slave

3 16-Bit

Timers

ADC

SYSTEM RESOURCES

Document Number: 001-77748 Rev. *F

Page 2 of 45

CYRF89235

Contents

Functional Overview ........................................................4

The enCoRe V Core ....................................................4

Full-Speed USB ...........................................................4

10-bit ADC ...................................................................5

SPI ...............................................................................5

I2C Slave .....................................................................6

WirelessUSB-NL Subsystem .......................................7

Transmit Power Control ...............................................7

Power-on and Register Initialization Sequence ...........7

Additional System Resources .....................................8

Getting Started ..................................................................8

Application Notes ........................................................8

Development Kits ........................................................8

Training .......................................................................8

CYPros Consultants ....................................................8

Solutions Library ..........................................................8

Technical Support .......................................................8

Development Tools ..........................................................9

PSoC Designer Software Subsystems ........................9

Designing with PSoC Designer .....................................10

Select User Modules .................................................10

Configure User Modules ............................................10

Organize and Connect ..............................................10

Generate, Verify, and Debug .....................................10

Pin Configuration ...........................................................11

Pin Definitions ................................................................12

Register Reference .........................................................13

Register Conventions ................................................13

Register Mapping Tables ..........................................13

Electrical Specifications ................................................16

Absolute Maximum Ratings .......................................16

Operating Temperature .............................................16

DC Chip-Level Specifications ....................................17

DC USB Interface Specifications ...............................18

ADC Electrical Specifications ....................................19

DC Analog Mux Bus Specifications ...........................20

DC Low Power Comparator Specifications ...............20

Comparator User Module Electrical Specifications ...20

DC GPIO Specifications ............................................21

DC POR and LVD Specifications ..............................23

DC Programming Specifications ...............................24

DC I2C Specifications ...............................................25

DC Reference Buffer Specifications ..........................25

DC IDAC Specifications ............................................25

AC Chip Level Specifications ....................................26

AC USB Data Timings Specifications ........................27

AC USB Driver Specifications ...................................27

AC General Purpose I/O Specifications ....................28

AC Comparator Specifications ..................................29

AC External Clock Specifications ..............................29

AC Programming Specifications ................................30

AC I2C Specifications ................................................31

SPI Master AC Specifications ...................................32

SPI Slave AC Specifications .....................................33

Electrical Specifications - RF Section ..........................35

Initialization Timing Requirements ............................38

SPI Timing Requirements .........................................39

Packaging Information ...................................................40

Packaging Dimensions ..............................................40

Thermal Impedances .................................................41

Capacitance on Crystal Pins .....................................41

Solder Reflow Peak Temperature .............................41

Ordering Information ......................................................42

Ordering Code Definitions .........................................42

Acronyms ........................................................................43

Document Conventions .................................................43

Units of Measure .......................................................43

Numeric Naming ........................................................43

Document History Page .................................................44

Sales, Solutions, and Legal Information ......................45

Worldwide Sales and Design Support .......................45

Products ....................................................................45

PSoC Solutions .........................................................45

Document Number: 001-77748 Rev. *F

Page 3 of 45

CYRF89235

Figure 1. USB Transceiver Regulator

Functional Overview

The enCoRe V family of devices are designed to replace multiple

traditional full-speed USB microcontroller system components

with one, low cost single-chip programmable component.

Communication peripherals (I²C/SPI), a fast CPU, flash program

memory, SRAM data memory, and configurable I/O are included

in a range of convenient pinouts.

PS2 Pull Up

VOLTAGE

REGULATOR

5V 3.3V

1.5K

5K

The architecture for this device family, as illustrated in the

PRoC-USB Logical Block Diagram on page 2, consists of three

main areas: the CPU core, the WirelessUSB™ NL subsystem

and the system resources.

TEN

TD

DP

DM

TRANSMITTER

RECEIVERS

PDN

This product is an enhanced version of Cypress’s successful full

speed-USB peripheral controllers. Enhancements include faster

CPU at lower voltage operation, lower current consumption,

twice the RAM and flash, hot-swappable I/Os, I²C hardware

address recognition, new very low current sleep mode, and new

package options.

RD

DPO

RSE0

The enCoRe V Core

DMO

The enCoRe V Core is a powerful engine that supports a rich

instruction set. It encompasses SRAM for data storage, an

interrupt controller, sleep and watchdog timers, and IMO and

ILO. The CPU core, called the M8C, is a powerful processor with

speeds up to 24 MHz. The M8C is a four-MIPS, 8-bit Harvard

architecture microprocessor.

At the enCoRe V system level, the full-speed USB system

resource interfaces to the rest of the enCoRe V by way of the

M8C's register access instructions and to the outside world by

way of the two USB pins. The SIE supports nine endpoints

including a bidirectional control endpoint (endpoint 0) and eight

System resources provide additional capability, such as a

configurable I²C slave and SPI master-slave communication

interface and various system resets supported by the M8C.

unidirectional data endpoints (endpoints

1 to 8). The

unidirectional data endpoints are individually configurable as

either IN or OUT.

Full-Speed USB

The USB serial interface engine (SIE) allows the enCoRe V

device to communicate with the USB host at full-speed data rates

(12 Mb/s). The SIE simplifies the interface to USB traffic by

automatically handling the following USB processing tasks

without firmware intervention:

The enCoRe V USB system resource adheres to the USB 2.0

Specification for full-speed devices operating at 12 Mb/second

with one upstream port and one USB address. enCoRe V USB

consists of these components:

■ Serial interface engine (SIE) block.

■ PSoC memory arbiter (PMA) block.

■ 512 bytes of dedicated SRAM.

■ Translates the encoded received data and formats the data to

be transmitted on the bus.

■ Generates and checks cyclical redundancy checks (CRCs).

Incoming packets failing checksum verification are ignored.

■ A full-speed USB Transceiver with internal regulator and two

dedicated USB pins.

■ Checks addresses. Ignores all transactions not addressed to

the device.

■ Sends appropriate ACK/NAK/Stall handshakes.

■ Identifies token type (SETUP, IN, OUT) and sets the

appropriate token bit once a valid token in received.

■ Identifies Start-of-Frame (SOF) and saves the frame count.

■ Sends data to or retrieves data from the USB SRAM, by way

of the PSoC Memory Arbiter (PMA).

Document Number: 001-77748 Rev. *F

Page 4 of 45

CYRF89235

Firmware is required to handle various parts of the USB

interface. The SIE issues interrupts after key USB events to

direct firmware to appropriate tasks:

input mux or the temperature sensor with an input voltage range

of 0 V to V_REFADC

.

In the ADC only configuration (the ADC MUX selects the Analog

mux bus, not the default temperature sensor connection), an

external voltage can be connected to the input of the modulator

for voltage conversion. The ADC is run for a number of cycles

set by the timer, depending upon the desired resolution of the

ADC. A counter counts the number of trips by the comparator,

which is proportional to the input voltage. The Temp Sensor block

clock speed is 36 MHz and is divided down to 1 to 12 MHz for

ADC operation.

■ Fill and empty the USB data buffers in USB SRAM.

■ Enable PMA channels appropriately.

■ Coordinate enumeration by decoding USB device requests.

■ Suspend and resume coordination.

■ Verify and select data toggle values.

10-bit ADC

SPI

The ADC on enCoRe V device is an independent block with a

state machine interface to control accesses to the block. The

ADC is housed together with the temperature sensor core and

can be connected to this or the Analog mux bus. As a default

operation, the ADC is connected to the temperature sensor

diodes to give digital values of the temperature.

The serial peripheral interconnect (SPI) 3-wire protocol uses

both edges of the clock to enable synchronous communication

without the need for stringent setup and hold requirements.

Figure 3. Basic SPI Configuration

SPI Master

Data is output by

both the Master

and Slave on

one edge of the

clock.

SPI Slave

Figure 2. ADC System Performance Block Diagram

V_IN

Data is registered at the

input of both devices on the

opposite edge of the clock.

SCLK

MOSI

MISO

TEMP SENSOR/ ADC

A device can be a master or slave. A master outputs clock and

data to the slave device and inputs slave data. A slave device

inputs clock and data from the master device and outputs data

for input to the master. Together, the master and slave are

essentially a circular Shift register, where the master generates

the clocking and initiates data transfers.

TEMP

DIODES

ADC

A basic data transfer occurs when the master sends eight bits of

data, along with eight clocks. In any transfer, both master and

slave transmit and receive simultaneously. If the master only

sends data, the received data from the slave is ignored. If the

master wishes to receive data from the slave, the master must

send dummy bytes to generate the clocking for the slave to send

data back.

SYSTEM BUS

INTERFACE BLOCK

COMMAND/ STATUS

Figure 4. SPI Block Diagram

SPI Block

MOSI,

MISO

MOSI,

MISO

DATA_IN DATA_OUT

SCLK

CLK_IN

SYSCLK

SS_

CLK_OUT

INT

Interface to the M8 C

( Processor) Core

Registers

The ADC User Module contains an integrator block and one

comparator with positive and negative input set by the MUXes.

The input to the integrator stage comes from the analog global

CONFIGURATION[7:0] CONTROL[7:0]

TRANSMIT[7:0] RECEIVE[7:0]

Document Number: 001-77748 Rev. *F

Page 5 of 45

CYRF89235

SPI configuration register (SPI_CFG) sets master/slave

functionality, clock speed, and interrupt select. SPI control

register (SPI_CR) provides four control bits and four status bits

for device interfacing and synchronization.

■ Interrupt or polling CPU interface.

■ Support for clock rates of up to 400 kHz.

■ 7- or 10-bit addressing (through firmware support).

The SPIM hardware has no support for driving the Slave Select

(SS_) signal. The behavior and use of this signal is dependent

on the application and enCoRe V device and, if required, must

be implemented in firmware.

■ SMBus operation (through firmware support).

Enhanced features of the I²C Slave Enhanced Module include:

■ Support for 7-bit hardware address compare.

■ Flexible data buffering schemes.

There is an additional data input in the SPIS, Slave Select (SS_),

which is an active low signal. SS_ must be asserted to enable

the SPIS to receive and transmit. SS_ has two high level

functions:

■ A "no bus stalling" operating mode.

■ A low power bus monitoring mode.

■ To allow for the selection of a given slave in a multi-slave

environment.

The I²C block controls the data (SDA) and the clock (SCL) to the

external I²C interface through direct connections to two

dedicated GPIO pins. When I²C is enabled, these GPIO pins are

not available for general purpose use. The enCoRe V CPU

firmware interacts with the block through I/O register reads and

writes, and firmware synchronization is implemented through

polling and/or interrupts.

■ ToprovideadditionalclockingforTXdataqueuinginSPImodes

0 and 1.

2

I C Slave

The I²C slave enhanced communications block is

a

serial-to-parallel processor, designed to interface the enCoRe V

device to a two-wire I²C serial communications bus. To eliminate

the need for excessive CPU intervention and overhead, the block

provides I²C-specific support for status detection and generation

of framing bits. By default, the I²C slave enhanced module is

firmware compatible with the previous generation of I²C slave

functionality. However, this module provides new features that

are configurable to implement significant flexibility for both

internal and external interfacing. The basic I²C features include:

In the default operating mode, which is firmware compatible with

previous versions of I²C slave modules, the I²C bus is stalled

upon every received address or byte, and the CPU is required to

read the data or supply data as required before the I²C bus

continues. However, this I²C Slave Enhanced module provides

new data buffering capability as an enhanced feature. In the

EZI²C buffering mode, the I²C slave interface appears as a

32-byte RAM buffer to the external I²C master. Using a simple

predefined protocol, the master controls the read and write

pointers into the RAM. When this method is enabled, the slave

never stalls the bus. In this protocol, the data available in the

RAM (this is managed by the CPU) is valid.

■ Slave, transmitter, and receiver operation.

■ Byte processing for low CPU overhead.

Figure 5. I²C Block Diagram

I2C Plus

Slave

I2C Core

Buffer Module

CPU Port

SDA_IN

SCL_IN

I2C Basic

Configuration

I2C_BUF

To/From

I2C_CFG

I2C_SCR

I2C_DR

GPIO

Pins

SDA_OUT

SCL_OUT

I2C_EN

32 Byte RAM

HW Addr Cmp

Buffer Ctl

I2C_ADDR

I2C_BP

SYSCLK

I2C_CP

MCU_BP

MCU_CP

Plus Features

I2C_XCFG

STANDBY

I2C_XSTAT

Document Number: 001-77748 Rev. *F

Page 6 of 45

CYRF89235

Figure 6. WirelessUSB-NL logic Block Diagram

WirelessUSB-NL Subsystem

V_DD1...V_DD7

WirelessUSB-NL, optimized to operate in the 2.4-GHz ISM band,

is Cypress's third generation of 2.4-GHz low-power RF

V

IN

V_OUT

V_{DD_IO}

technology. WirelessUSB-NL implements

a

Gaussian

LDO Linear

Regulator

GFSK

Modulator

frequency-shift keying (GFSK) radio using a differentiated

single-mixer, closed-loop modulation design that optimizes

power efficiency and interference immunity. Closed-loop

modulation effectively eliminates the problem of frequency drift,

enabling WirelessUSB-NL to transmit up to 255-byte payloads

without repeatedly having to pay power penalties for re-locking

the phase-locked loop (PLL) as in open-loop designs

PKT

PA

SPI_SS

CLK

ANT

VCO

Synthesizer

ANTb

MISO

MOSI

Among the advantages of WirelessUSB-NL are its fast lock times

and channel switching, along with the ability to transmit larger

payloads. Use of longer payload packets, compared to multiple

short payload packets, can reduce overhead, improve overall

power efficiency, and help alleviate spectrum crowding.

RST_n

Pwr/ Reset

BRCLK

GFSK

X

Image

Xtal Osc

Demodulator

LNA + BPF

Rej. Mxr.

XTALi

XTALo

GND GND

Combined with Cypress's enCoRe V based full-speed USB

controllers, WirelessUSB-NL also provides the lowest bill of

materials (BOM) cost solution for sophisticated PC peripheral

applications such as wireless keyboards and mice, as well as

best-in-class wireless performance in other demanding

applications, such as toys, remote controls, fitness, automation,

presenter tools, and gaming.

Transmit Power Control

The following table lists recommended settings for register 9 for

short-range applications, where reduced transmit RF power is a

desirable trade off for lower current.

With PRoC-USB, the WirelessUSB-NL transceiver can add

wireless capability to a wide variety of full speed USB

applications.

Table 1. Transmit Power Control

Typical

Transmit

Power

Value of Register 9

Power Setting

Description

The WirelessUSB-NL is a fully-integrated CMOS RF transceiver,

GFSK data modem, and packet framer, optimized for use in the

2.4-GHz ISM band. It contains transmit, receive, RF synthesizer,

and digital modem functions, with few external components. The

transmitter supports digital power control. The receiver uses

extensive digital processing for excellent overall performance,

even in the presence of interference and transmitter

impairments.

Silicon ID

0x1002

Silicon ID

0x2002

(dBm)

PA0 - Highest power

PA2 - High power

PA4 - High power

PA8 - Low power

PA12 - Lower power

+1

0

0x1820

0x1920

0x1A20

0x1C20

0x1E20

0x7820

0x7920

0x7A20

0x7C20

0x7E20

–3

–7.5

–11.2

The product transmits GFSK data at approximately 0-dBm

output power. Sigma-Delta PLL delivers high-quality DC-coupled

transmit data path.

Note: Silicon ID can be read from Register 31.

The low-IF receiver architecture produces good selectivity and

image rejection, with typical sensitivity of –87 dBm or better on

most channels. Sensitivity on channels that are integer multiples

of the crystal reference oscillator frequency (12 MHz) may show

approximately 5 dB degradation. Digital RSSI values are

available to monitor channel quality.

Power-on and Register Initialization Sequence

For proper initialization at power up, V_INmust ramp up at the

minimum overall ramp rate no slower than shown by T_VIN

specification in the following figure. During this time, the RST_n

line must track the V_INvoltage ramp-up profile to within

approximately 0.2 V. Since most MCU GPIO pins automatically

default to a high-Z condition at power up, it only requires a pull-up

resistor. When power is stable and the MCU POR releases, and

MCU begins to execute instructions, RST_n must then be pulsed

low as shown in Figure 18 on page 39, followed by writing

Reg 27 = 0x4200. During or after this SPI transaction, the State

Machine status can be read to confirm FRAMER_ST = 1,

indicating a proper initialization.

On-chip transmit and receive FIFO registers are available to

buffer the data transfer with MCU. Over-the-air data rate is

always 1 Mbps even when connected to a slow, low-cost MCU.

Built-in CRC, FEC, data whitening, and automatic

retry/acknowledge are all available to simplify and optimize

performance for individual applications.

For more details on the radio’s implementation details and timing

requriements, please go through the WirelessUSB-NL datasheet

in www.cypress.com.

Document Number: 001-77748 Rev. *F

Page 7 of 45

CYRF89235

Additional System Resources

Development Kits

System resources, some of which have been previously listed,

provide additional capability useful to complete systems.

Additional resources include low-voltage detection and power-on

reset. The following statements describe the merits of each

system resource.

PSoC development kits are available online from Cypress at

http://www.cypress.com and through a growing number of

regional and global distributors, including Arrow, Avnet, Digi-Key,

Farnell, Future Electronics, and Newark.

Training

■ Low-voltage detection (LVD) interrupts can signal the appli-

cation of falling voltage levels, while the advanced power-on

reset (POR) circuit eliminates the need for a system supervisor.

Free PSoC technical training (on demand, webinars, and

workshops) is available online at http://www.cypress.com. The

training covers a wide variety of topics and skill levels to assist

you in your designs.

■ The 5 V maximum input, 1.8, 2.5, or 3 V selectable output, LDO

regulator provides regulation for I/Os. A register controlled

bypass mode enables the user to disable the LDO.

CYPros Consultants

Certified PSoC Consultants offer everything from technical

assistance to completed PSoC designs. To contact or become a

PSoC Consultant, go to http://www.cypress.com and look for

CYPros Consultants.

■ Standard Cypress PSoC IDE tools are available for debugging

the enCoRe V family of parts.

Getting Started

Solutions Library

The quickest path to understanding the PRoC-USB silicon is by

reading this data sheet and using the PSoC^®Designer™

integrated development environment (IDE). This datasheet is an

overview of the PSoC integrated circuit and presents specific pin,

register, and electrical specifications. For in-depth information,

along with detailed programming information, see the enCoRe™

Visit our growing library of solution-focused designs at

http://www.cypress.com. Here you can find various application

designs that include firmware and hardware design files that

enable you to complete your designs quickly.

V

CY7C643xx, enCoRe™ V LV CY7C604xx Technical

Technical Support

Reference Manual (TRM) for this PSoC device.

For assistance with technical issues, search KnowledgeBase

articles and forums at http://www.cypress.com. If you cannot find

an answer to your question, call technical support at

1-800-541-4736.

For up-to-date ordering, packaging, and electrical specification

information, see the latest PSoC device data sheets on the web

at http://www.cypress.com.

Application Notes

Application notes are an excellent introduction to the wide variety

of possible PSoC designs and are available at

http://www.cypress.com.

Document Number: 001-77748 Rev. *F

Page 8 of 45

CYRF89235

of debugging tools. You can develop your design in C, assembly,

or a combination of the two.

Development Tools

PSoC Designer™ is the revolutionary integrated design

environment (IDE) that you can use to customize PSoC to meet

your specific application requirements. PSoC Designer software

accelerates system design and time to market. Develop your

applications using a library of precharacterized analog and digital

peripherals (called user modules) in a drag-and-drop design

environment. Then, customize your design by leveraging the

dynamically generated application programming interface (API)

libraries of code. Finally, debug and test your designs with the

integrated debug environment, including in-circuit emulation and

standard software debug features. PSoC Designer includes:

Assemblers. The assemblers allow you to merge assembly

code seamlessly with C code. Link libraries automatically use

absolute addressing or are compiled in relative mode, and linked

with other software modules to get absolute addressing.

C Language Compilers. C language compilers are available

that support the PSoC family of devices. The products allow you

to create complete C programs for the PSoC family devices. The

optimizing C compilers provide all of the features of C, tailored

to the PSoC architecture. They come complete with embedded

libraries providing port and bus operations, standard keypad and

display support, and extended math functionality.

■ Application editor graphical user interface (GUI) for device and

user module configuration and dynamic reconfiguration

Debugger

PSoC Designer has a debug environment that provides

hardware in-circuit emulation, allowing you to test the program in

a physical system while providing an internal view of the PSoC

device. Debugger commands allow you to read and program and

read and write data memory, and read and write I/O registers.

You can read and write CPU registers, set and clear breakpoints,

and provide program run, halt, and step control. The debugger

also allows you to create a trace buffer of registers and memory

locations of interest.

■ Extensive user module catalog

■ Integrated source-code editor (C and assembly)

■ Free C compiler with no size restrictions or time limits

■ Built-in debugger

■ In-circuit emulation

■ Built-in support for communication interfaces:

❐ Hardware and software I²C slaves and masters

❐ Full-speed USB 2.0

Online Help System

The online help system displays online, context-sensitive help.

Designed for procedural and quick reference, each functional

subsystem has its own context-sensitive help. This system also

provides tutorials and links to FAQs and an Online Support

Forum to aid the designer.

❐ SPI master and slave, and wireless

PSoC Designer supports the entire library of PSoC 1 devices and

runs on Windows XP, Windows Vista, and Windows 7.

PSoC Designer Software Subsystems

In-Circuit Emulator

Design Entry

A

low-cost, high-functionality in-circuit emulator (ICE) is

In the chip-level view, choose a base device to work with. Then

select different onboard analog and digital components that use

the PSoC blocks, which are called user modules. Examples of

user modules are analog-to-digital converters (ADCs),

digital-to-analog converters (DACs), amplifiers, and filters.

Configure the user modules for your chosen application and

connect them to each other and to the proper pins. Then

generate your project. This prepopulates your project with APIs

and libraries that you can use to program your application.

available for development support. This hardware can program

single devices.

The emulator consists of a base unit that connects to the PC

using a USB port. The base unit is universal and operates with

all PSoC devices. Emulation pods for each device family are

available separately. The emulation pod takes the place of the

PSoC device in the target board and performs full-speed

(24-MHz) operation.

The tool also supports easy development of multiple

configurations and dynamic reconfiguration. Dynamic

reconfiguration makes it possible to change configurations at run

time. In essence, this allows you to use more than 100 percent

of PSoC's resources for a given application.

Device Programmers

Firmware needs to be downloaded to PRoC USB device only at

3.3 V using Miniprog3 Programmer. This Programmer kit can be

purchased from Cypress Store using part# ‘CY8CKIT-002 -

MiniProg3’. It is a small, compact programmer which connects

PC via a USB 2.0 cable (provided along with CY8cKIT-002)

Code Generation Tools

Note: MiniProg1 Programmer should not be used as it does not

support programming at 3.3 V.

The code generation tools work seamlessly within the

PSoC Designer interface and have been tested with a full range

Document Number: 001-77748 Rev. *F

Page 9 of 45

CYRF89235

module and provide performance specifications. Each datasheet

describes the use of each user module parameter, and other

information that you may need to successfully implement your

design.

Designing with PSoC Designer

The development process for the PSoC device differs from that

of a traditional fixed-function microprocessor. The configurable

analog and digital hardware blocks give the PSoC architecture a

unique flexibility that pays dividends in managing specification

change during development and lowering inventory costs. These

configurable resources, called PSoC blocks, have the ability to

implement a wide variety of user-selectable functions. The PSoC

development process is:

Organize and Connect

Build signal chains at the chip level by interconnecting user

modules to each other and the I/O pins. Perform the selection,

configuration, and routing so that you have complete control over

all on-chip resources.

1. Select user modules.

Generate, Verify, and Debug

2. Configure user modules.

3. Organize and connect.

4. Generate, verify, and debug.

When you are ready to test the hardware configuration or move

on to developing code for the project, perform the “Generate

Configuration Files” step. This causes PSoC Designer to

generate source code that automatically configures the device to

your specification and provides the software for the system. The

generated code provides APIs with high-level functions to control

and respond to hardware events at run time, and interrupt

service routines that you can adapt as needed.

Select User Modules

PSoC Designer provides a library of prebuilt, pretested hardware

peripheral components called user modules. User modules

make selecting and implementing peripheral devices, both

analog and digital, simple.

A complete code development environment allows you to

develop and customize your applications in C, assembly

language, or both.

Configure User Modules

Each user module that you select establishes the basic register

settings that implement the selected function. They also provide

parameters and properties that allow you to tailor their precise

configuration to your particular application. For example, a

pulse-width modulator (PWM) user module configures one or

more digital PSoC blocks, one for each eight bits of resolution.

Using these parameters, you can establish the pulse width and

duty cycle. Configure the parameters and properties to

correspond to your chosen application. Enter values directly or

by selecting values from drop-down menus. All of the user

modules are documented in datasheets that may be viewed

directly in PSoC Designer or on the Cypress website. These user

module datasheets explain the internal operation of the user

The last step in the development process takes place inside

PSoC Designer's Debugger (accessed by clicking the Connect

icon). PSoC Designer downloads the HEX image to the ICE

where it runs at full speed. PSoC Designer debugging

capabilities rival those of systems costing many times more. In

addition to traditional single-step, run-to-breakpoint, and

watch-variable features, the debug interface provides a large

trace buffer. It allows you to define complex breakpoint events

that include monitoring address and data bus values, memory

locations, and external signals.

Document Number: 001-77748 Rev. *F

Page 10 of 45

CYRF89235

Pin Configuration

The PRoC-USB device is available in a 40-pin QFN package, which is illustrated in the subsequent tables.

Figure 7. 40-pin QFN pinout

Document Number: 001-77748 Rev. *F

Page 11 of 45

CYRF89235

Pin Definitions

Pin No

Pin name

P1[3]/SCLK

P1[1]/MOSI ^{[1, 2]}Digital I/O, Analog I/O, TC CLK, I2C SCL, SPI MOSI

Pin Description

1

2

3

Digital I/O, Analog I/O, SPI CLK

GND

V_DD

Ground connection

4, 20, 25, 33,

34, 37

Core power supply voltage. Connect all V_DDpins to VOUT pin.

5

6

D+

D-

USB PHY, Digital I/O

7

FIFO

FIFO status indicator bit

8, 21, 24

9

VIN

Unregulated input voltage to the on-chip low drop out (LDO) voltage regulator

Analog I/O, Digital I/O, TC DATA, I²C SDA

VDD for the digital interface

P1[0] ^{[1, 2]}

VDD_IO

P1[2]

10

11

Analog I/O, Digital I/O

12

P1[4]

Analog I/O, Digital I/O, EXT CLK

13

XRES

Active high external reset with internal pull-down

Enable input for SPI, active low. Also used to bring device out of sleep state.

Transmit/receive packet status indicator bit

Clock input for SPI interface

14

SPI_SS

PKT

15

16

SPI_CLK

SPI_MOSI

SPI_MISO

RST_n

17

Data input for the SPI bus

18

Data output (tristate when not active)

19

RST_n Low: Chip shutdown to conserve power. Register values lost

RST_n High: Turn on chip, registers restored to default value

22

23

26

27

28

29

30

31

32

35

36

38

39

40

VOUT

P0[4]

1.8 V output from on-chip LDO. Connect to all V_DDpins, do not connect to external loads.

Analog I/O, Digital I/O, VREF

XTALO

XTALI

P0[7]

Output of the crystal oscillator gain block

Input to the crystal oscillator gain block

Analog I/O, Digital I/O,SPI CLK

P0[3]

Analog I/O, Digital I/O, Integrating input

P0[1]

Analog I/O, Digital I/O, Integrating input

P2[5]

Analog I/O, Digital I/O, XTAL Out

P2[3]

Analog I/O, Digital I/O, XTAL In

ANTb

Differential RF input/output. Each of these pins must be DC grounded, 20 kΩ or less

Digital I/O, Analog I/O, I²C SCL, SPI SS

ANT

P1[7]/SS_N

P1[5]/MISO

VDD

Digital I/O, Analog I/O, I²C SDA, SPI MISO

Core power supply voltage. Connect all V_DDpins to VOUT pin.

Notes

2

1. During power up or reset event, device P1[0] and P1[1] may disturb the I C bus. Use alternate pins if issues are encountered.

2. These are the in-system serial programming (ISSP) pins that are not High Z at power-on reset (POR).

Document Number: 001-77748 Rev. *F

Page 12 of 45

CYRF89235

Register Reference

The section discusses the registers of the enCoRe V device. It lists all the registers in mapping tables, in address order.

Register Conventions

Register Mapping Tables

The register conventions specific to this section are listed in the

following table.

The enCoRe V device has a total register address space of 512

bytes. The register space is also referred to as I/O space and is

broken into two parts: Bank 0 (user space) and Bank 1

(configuration space). The XIO bit in the Flag register (CPU_F)

determines which bank the user is currently in. When the XIO bit

is set, the user is said to be in the “extended” address space or

the “configuration” registers.

Table 2. Register Conventions

Convention

Description

Read register or bits

R

W

L

Write register or bits

Logical register or bits

Clearable register or bits

Access is bit specific

C

#

Document Number: 001-77748 Rev. *F

Page 13 of 45

CYRF89235

Table 3. Register Map Bank 0 Table: User Space

Name

PRT0DR

PRT0IE

Addr (0,Hex) Access

Name

Addr (0,Hex) Access

Name

Addr (0,Hex) Access

Name

Addr (0,Hex) Access

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

RW

EP1_CNT0

EP1_CNT1

EP2_CNT0

EP2_CNT1

EP3_CNT0

EP3_CNT1

EP4_CNT0

EP4_CNT1

EP5_CNT0

EP5_CNT1

EP6_CNT0

EP6_CNT1

EP7_CNT0

EP7_CNT1

EP8_CNT0

EP8_CNT1

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

#

RW

#

RW

#

RW

#

RW

#

RW

#

RW

#

RW

#

RW

80

81

82

83

84

85

86

87

88

89

8A

8B

8C

8D

8E

8F

90

91

92

93

94

95

96

97

98

99

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

AA

AB

AC

AD

AE

AF

C0

C1

C2

C3

C4

C5

C6

C7

PRT1DR

PRT1IE

RW

PRT2DR

PRT2IE

RW

I2C_XCFG

I2C_XSTAT

I2C_ADDR

I2C_BP

C8

C9

CA

CB

CC

CD

CE

CF

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

DD

DE

DF

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

F0

F1

F2

F3

F4

F5

F6

F7

F8

F9

FA

FB

FC

FD

FE

FF

RW

R

RW

R

RW

R

RW

PRT3DR

PRT3IE

RW

I2C_CP

CPU_BP

CPU_CP

I2C_BUF

CUR_PP

STK_PP

PRT4DR

PRT4IE

RW

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

IDX_PP

RW

#

MVR_PP

MVW_PP

I2C_CFG

I2C_SCR

I2C_DR

PMA0_DR

PMA1_DR

PMA2_DR

PMA3_DR

PMA4_DR

PMA5_DR

PMA6_DR

PMA7_DR

RW

INT_CLR0

INT_CLR1

INT_CLR2

RW

INT_MSK2

INT_MSK1

INT_MSK0

INT_SW_EN

INT_VC

RW

RC

W

RES_WDT

PMA8_DR

PMA9_DR

PMA10_DR

PMA11_DR

PMA12_DR

PMA13_DR

PMA14_DR

PMA15_DR

TMP_DR0

TMP_DR1

TMP_DR2

TMP_DR3

RW

SPI_TXR

SPI_RXR

SPI_CR

W

R

#

PT0_CFG

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

RW

USB_SOF0

USB_SOF1

USB_CR0

USBIO_CR0

USBIO_CR1

EP0_CR

EP0_CNT0

EP0_DR0

EP0_DR1

EP0_DR2

EP0_DR3

EP0_DR4

EP0_DR5

EP0_DR6

EP0_DR7

R

RW

#

PT0_DATA1

PT0_DATA0

PT1_CFG

PT1_DATA1

PT1_DATA0

PT2_CFG

#

PT2_DATA1

PT2_DATA0

CPU_F

RL

RW

CPU_SCR1

CPU_SCR0

#

Gray fields are reserved; do not access these fields.

# Access is bit specific.

Document Number: 001-77748 Rev. *F

Page 14 of 45

CYRF89235

Table 4. Register Map Bank 1 Table: Configuration Space

Name

PRT0DM0

PRT0DM1

Addr (1,Hex) Access

Name

Addr (1,Hex) Access

Name

Addr (1,Hex) Access

Name

Addr (1,Hex) Access

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

RW

PMA4_RA

PMA5_RA

PMA6_RA

PMA7_RA

PMA8_WA

PMA9_WA

PMA10_WA

PMA11_WA

PMA12_WA

PMA13_WA

PMA14_WA

PMA15_WA

PMA8_RA

PMA9_RA

PMA10_RA

PMA11_RA

PMA12_RA

PMA13_RA

PMA14_RA

PMA15_RA

EP1_CR0

EP2_CR0

EP3_CR0

EP4_CR0

EP5_CR0

EP6_CRO

EP7_CR0

EP8_CR0

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

RW

#

80

81

82

83

84

85

86

87

88

89

8A

8B

8C

8D

8E

8F

90

91

92

93

94

95

96

97

98

99

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

AA

AB

AC

AD

AE

AF

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

D0

D1

PRT1DM0

PRT1DM1

RW

PRT2DM0

PRT2DM1

RW

PRT3DM0

PRT3DM1

RW

PRT4DM0

PRT4DM1

RW

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

EC0_ENBUS

EC0_TRIM

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

DD

DE

DF

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

F0

F1

F2

F3

F4

F5

F6

F7

F8

F9

FA

FB

FC

FD

FE

FF

RW

#

MUX_CR0

MUX_CR1

MUX_CR2

MUX_CR3

IO_CFG1

OUT_P1

IO_CFG2

MUX_CR4

OSC_CR0

ECO_CFG

OSC_CR2

VLT_CR

RW

#

RW

R

VLT_CMP

IMO_TR

ILO_TR

W

SPI_CFG

USB_CR1

RW

SLP_CFG

SLP_CFG2

SLP_CFG3

RW

TMP_DR0

TMP_DR1

TMP_DR2

TMP_DR3

RW

#

PMA0_WA

PMA1_WA

PMA2_WA

PMA3_WA

PMA4_WA

PMA5_WA

PMA6_WA

PMA7_WA

PMA0_RA

PMA1_RA

PMA2_RA

PMA3_RA

RW

CPU_F

RL

IMO_TR1

RW

USB_MISC_CR

BD

BE

BF

RW

Gray fields are reserved; do not access these fields.

# Access is bit specific.

Document Number: 001-77748 Rev. *F

Page 15 of 45

CYRF89235

Electrical Specifications

This section presents the DC and AC electrical specifications of the enCoRe V USB devices. For the most up-to-date electrical

specifications, verify that you have the most recent data sheet available by visiting the company web site at http://www.cypress.com

Figure 8. Voltage versus CPU Frequency

Figure 9. IMO Frequency Trim Options

3.6V

3.6 V

SLIMO

Mode

SLIMO SLIMO

Mode

= 00

Mode

= 01

= 10

1.9V

1.9 V

750 kHz

3 MHz

6 MHz 12 MHz 24 MHz

750kHz

3 MHz

24 MHz

IMO Frequency

CPU Frequency

Absolute Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.

Table 5. Absolute Maximum Ratings

Symbol

T_STG

Description

Conditions

Min

Typ

Max

Units

Storage temperature

Higher storage temperatures

reduce data retention time.

Recommended Storage

–55

25

125

°C

Temperature is +25 °C ± 25 °C.

Extended duration storage

temperatures above 85 °C

degrades reliability.

[3]

V_IN

–

1.9

–0.5

–25

–

3.63

V_IN+ 0.5

+50

V

V_IO

DC input voltage

[4]

V_IOZ

I_MIO

DC voltage applied to tristate

V

Maximum current into any port

mA

ESD

Electrostatic discharge voltage Human body model ESD

i) RF pins (ANT, ANTb)

–

V

500

2000

ii) Analog pins (XTALi, XTALo)

iii) Remaining pins

LU

Latch-up current

In accordance with JESD78

standard

–

140

mA

Operating Temperature

Table 6. Operating Temperature

Symbol

Description

Ambient temperature

Conditions

Min

Typ

Max

Units

T_A

–

0

–

70

°C

Notes

3. Program the device at 3.3 V only. Hence use Miniprog3 only since Miniprog1 does not support programming at 3.3 V.

4. Port1 pins are hot-swap capable with I/O configured in High-Z mode, and pin input voltage above V_IN

.

Document Number: 001-77748 Rev. *F

Page 16 of 45

CYRF89235

DC Chip-Level Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 7. DC Chip-Level Specifications

Symbol

[5, 6, 7, 8]

Description

Supply voltage

Conditions

Min

Typ

Max

Units

V_IN

No USB activity. Refer the table

DC POR and LVD

1.9

–

3.6

V

Specifications on page 23

[5, 6, 7, 8]

V_INUSB

I_DD24

Operating voltage

USB activity,

USB regulator bypassed

3.15

–

3.3

3.45

4.00

V

Supply current, IMO = 24 MHz

Conditions are VIN  3.0 V,

T_A= 25 °C, CPU = 24 MHz.

no I/O sourcing current

2.88

mA

I_DD12

Supply current, IMO = 12 MHz

Supply current, IMO = 6 MHz

Deep sleep current

Conditions are VIN  3.0 V,

T_A= 25 °C, CPU = 12 MHz.

no I/O sourcing current

–

1.71

1.16

2.60

1.80

mA

I_DD6

Conditions are VIN  3.0 V,

T_A= 25 °C, CPU = 6 MHz.

no I/O sourcing current

I_SB0

VIN  3.0 V, T_A= 25 °C, I/O

regulator turned off

–

0.10

1.07

1.64

1.05

1.50

–

A

I_SB1

Standby current with POR, LVD VIN  3.0 V, T_A= 25 °C, I/O

and sleep timer regulator turned off

Standby current with I²C enabled Conditions are VIN = 3.3 V,

T_A= 25 °C and CPU = 24 MHz

I_SBI2C

Notes

5. If powering down in standby sleep mode, to properly detect and recover from a VIN brown out condition any of the following actions must be taken:

Bring the device out of sleep before powering down.

Assure that VIN falls below 100 mV before powering back up.

Set the No Buzz bit in the OSC_CR0 register to keep the voltage monitoring circuit powered during sleep.

Increase the buzz rate to assure that the falling edge of VIN is captured. The rate is configured through the PSSDC bits in the SLP_CFG register.

For the referenced registers, refer to the enCoRe V Technical Reference Manual. In deep sleep mode, additional low power voltage monitoring circuitry allows VIN

brown out conditions to be detected for edge rates slower than 1 V/ms.

6. Always greater than 50 mV above V_PPOR1voltage for falling supply.

7. Always greater than 50 mV above V_PPOR2voltage for falling supply.

8. Always greater than 50 mV above V_PPOR3voltage for falling supply.

Document Number: 001-77748 Rev. *F

Page 17 of 45

CYRF89235

DC USB Interface Specifications

Table 8. DC USB Interface Specifications

Symbol

R_USBI

Description

USB D+ pull-up resistance

Static output high

Conditions

With idle bus

Min

900

1425

2.8

–

Typ

–

Max

1575

3090

3.6

Units



V

R_USBA

V_OHUSB

V_OLUSB

V_DI

While receiving traffic

–

Static output low

–

0.3

Differential input sensitivity

0.2

0.8

–

V_CM

Differential input common mode

range

–

2.5

V_SE

C_IN

Single ended receiver threshold

Transceiver capacitance

–

0.8

–

2.0

50

V

pF

A



–

I_IO

High Z state data line leakage

PS/2 pull-up resistance

On D+ or D– line

–10

3000

21.78

–

+10

R_PS2

R_EXT

–

5000

22.0

7000

22.22

External USB series resistor

In series with each USB pin



Document Number: 001-77748 Rev. *F

Page 18 of 45

CYRF89235

ADC Electrical Specifications

Table 9. ADC User Module Electrical Specifications

Symbol

Input

Description

Conditions

Min

Typ

Max

Units

V_IN

C_IIN

R_IN

Input voltage range

–

0

–

VREFADC

5

V

pF



Input capacitance

Input resistance

Equivalent switched cap input

resistance for 8-, 9-, or 10-bit

resolution

1/(500fF × 1/(400fF × 1/(300fF ×

dataclock) dataclock) dataclock)

Reference

V_REFADC

ADC reference voltage

–

1.14

2.25

–

1.26

6

V

Conversion Rate

F_CLKData clock

Source is chip’s internal main

oscillator. See AC Chip-Level

Specifications for accuracy

MHz

S8

8-bit sample rate

10-bit sample rate

Data clock set to 6 MHz. sample

rate = 0.001/ (2^Resolution/Data

Clock)

–

23.43

5.85

–

ksps

S10

Data clock set to 6 MHz. sample

rate = 0.001/ (2^resolution/data

clock)

DC Accuracy

RES

Resolution

Can be set to 8-, 9-, or 10-bit

8

–1

–2

0

–

10

+2

bits

LSB

DNL

Differential nonlinearity

Integral nonlinearity

Offset error

–

INL

–

+2

LSB

E_OFFSET

8-bit resolution

10-bit resolution

For any resolution

3.20

12.80

–

19.20

76.80

+5

LSB

0

LSB

E_GAIN

Power

I_ADC

Gain error

–5

%FSR

Operating current

–

2.10

24

2.60

–

mA

dB

PSRR

Power supply rejection ratio

PSRR (VIN > 3.0 V)

PSRR (VIN < 3.0 V)

30

–

Document Number: 001-77748 Rev. *F

Page 19 of 45

CYRF89235

DC Analog Mux Bus Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 10. DC Analog Mux Bus Specifications

Symbol

R_SW

Description

Conditions

Min

Typ

Max

Units

Switch resistance to common

analog bus

–

800



R_GND

Resistanceofinitializationswitch –

to GND

–

800



The maximum pin voltage for measuring R_Wand R_GNDis 1.8 V

DC Low Power Comparator Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 11. DC Comparator Specifications

Symbol

V_LPC

Description

Conditions

Min

Typ

Max

Units

Low power comparator (LPC)

common mode

Maximum voltage limited to V_IN

0.0

–

1.8

V

I_LPC

LPC supply current

LPC voltage offset

–

10

3

40

30

A

V_OSLPC

mV

Comparator User Module Electrical Specifications

The following table lists the guaranteed maximum and minimum specifications. Unless stated otherwise, the specifications are for the

entire device voltage and temperature operating range: 0 °C  T_A 70 °C, 1.9 V  V_IN 3.6 V.

Table 12. Comparator User Module Electrical Specifications

Symbol

t_COMP

Description

Conditions

50 mV overdrive

Min

–

Typ

70

Max

100

30

Units

ns

Comparator response time

Offset

Valid from 0.2 V to V_IN– 0.2 V

–

2.5

20

mV

µA

Current

Average DC current, 50 mV

overdrive

–

80

Supply voltage > 2 V

Supply voltage < 2 V

Power supply rejection ratio

–

0

80

40

–

dB

V

PSRR

Power supply rejection ratio

–

Input range

1.5

Document Number: 001-77748 Rev. *F

Page 20 of 45

CYRF89235

DC GPIO Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4 V to 3.0 V and

0 °C  T_A 70 °C, or 1.9 V to 2.4 V and 0 °C  T_A°C, respectively. Typical parameters apply to 3.3 V at 25 °C and are for design

guidance only.

Table 13. 2.4 V to 3.0 V DC GPIO Specifications

Symbol

R_PU

Description

Pull-up resistor

Conditions

Min

Typ

5.60

–

Max

8

Units

k

–

4

V_OH1

V_OH2

V_OH3

High output voltage Port 2 or 3 or I_OH< 10 A, maximum of 10 mA VIN – 0.20

4 pins source current in all I/Os

–

V

High output voltage Port 2 or 3 or I_OH= 0.2 mA, maximum of 10 mA VIN – 0.40

4 pins source current in all I/Os

–

V

High output voltage Port 0 or 1 I_OH< 10 A, maximum of 10 mA VIN – 0.20

pins with LDO regulator Disabled source current in all I/Os

for port 1

V_OH4

High output voltage Port 0 or 1 I_OH= 2 mA, maximum of 10 mA

pins with LDO regulator Disabled source current in all I/Os

for Port 1

VIN – 0.50

–

V

V_OH5A

High output voltage Port 1 pins I_OH< 10 A, VIN > 2.4 V,

with LDO enabled for 1.8 V out maximumof20 mAsourcecurrent

in all I/Os

1.50

1.80

2.10

V_OH6A

V_OL

High output voltage Port 1 pins I_OH= 1 mA, VIN > 2.4 V, maximum

with LDO enabled for 1.8 V out of 20 mA source current in all I/Os

1.20

–

V

Low output voltage

IOL = 10 mA, maximum of 30 mA

sink current on even port pins (for

example, P0[2] and P1[4]) and 30

mA sink current on odd port pins

(for example, P0[3] and P1[5])

0.75

V_IL

V_IH

V_H

Input low voltage

–

1.40

–

0.72

V

Input high voltage

Input hysteresis voltage

Input leakage (absolute value)

Capacitive load on pins

80

1

–

1000

7

mV

nA

pF

I_IL

–

C_PIN

Package and

0.50

1.70

pin dependent Temp = 25 C

V_ILLVT2.5

Input Low Voltage with low

threshold enable set, Enable for threshold voltage of Port1 input

Port1

Bit3 of IO_CFG1 set to enable low

0.7

1.2

V

–

V_IHLVT2.5

Input High Voltage with low

Bit3 of IO_CFG1 set to enable low

V

threshold enable set, Enable for threshold voltage of Port1 input

Port1

Document Number: 001-77748 Rev. *F

Page 21 of 45

CYRF89235

Table 14. 1.9 V to 2.4 V DC GPIO Specifications

Symbol Description

R_PUPull-up resistor

Conditions

Min

Typ

5.60

–

Max

8

Units

k

–

4

V_OH1

V_OH2

V_OH3

High output voltage Port 2 or 3 or I_OH= 10 A, maximum of 10 mA VIN – 0.20

4 pins source current in all I/Os

–

V

High output voltage Port 2 or 3 or I_OH= 0.5 mA, maximum of 10 mA VIN – 0.50

4 pins

–

V

source current in all I/Os

High output voltage Port 0 or 1

pins with LDO regulator Disabled source current in all I/Os

for Port 1

I_OH= 100 A, maximum of 10 mA VIN – 0.20

V_OH4

High output voltage Port 0 or 1 I_OH= 2 mA, maximum of 10 mA VIN – 0.50

–

V

Pins with LDO Regulator

Disabled for Port 1

source current in all I/Os

V_OL

Low output voltage

I_OL= 5 mA, maximum of 20 mA

sink current on even port pins (for

example, P0[2] and P1[4]) and 30

mA sink current on odd port pins

(for example, P0[3] and P1[5])

–

0.40

V_IL

V_IH

V_H

Input low voltage

–

0.30 × VIN

V

Input high voltage

0.65 × VIN

–

Input hysteresis voltage

Input leakage (absolute value)

Capacitive load on pins

–

80

1

mV

nA

pF

I_IL

1000

7

C_PIN

Package and

0.50

1.70

pin dependent temp = 25 °C

Document Number: 001-77748 Rev. *F

Page 22 of 45

CYRF89235

DC POR and LVD Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 15. DC POR and LVD Specifications

Symbol

V_POR1

Description

2.36 V selected in

PSoC Designer

Conditions

Min

Typ

Max

Units

VIN must be greater than or equal

to 1.9 V during startup, reset from

the XRES pin, or reset from

watchdog.

–

2.36

2.41

V

V_POR2

V_POR3

V_LVD0

V_LVD1

V_LVD2

V_LVD3

V_LVD4

V_LVD5

2.60 V selected in

PSoC Designer

–

2.60

2.82

2.45

2.71

2.92

3.02

3.13

1.90

2.66

2.95

2.51

2.78

2.99

3.09

3.20

2.32

2.82 V selected in

PSoC Designer

–

2.45 V selected in

PSoC Designer

–

2.40

V

2.71 V selected in

PSoC Designer

2.64^[9]

2.85^[10]

2.95^[11]

3.06

2.92 V selected in

PSoC Designer

3.02 V selected in

PSoC Designer

3.13 V selected in

PSoC Designer

1.90 V selected in

PSoC Designer

1.84

Notes

9. Always greater than 50 mV above V_PPOR1voltage for falling supply.

10. Always greater than 50 mV above V_PPOR2voltage for falling supply.

11. Always greater than 50 mV above V_PPOR3voltage for falling supply.

Document Number: 001-77748 Rev. *F

Page 23 of 45

CYRF89235

DC Programming Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 16. DC Programming Specifications

Symbol

Description

Conditions

Min

Typ

Max

Units

V_IN

I_DDP

V_ILP

Supply voltage for flash write

operations

–

1.91

–

3.6

V

Supply current during

programming or verify

–

5

–

25

mA

V

Input low voltage during

programming or verify

See the appropriate DC Analog

Mux Bus Specifications on page

20

V_IL

V_IHP

Input high voltage during

programming or verify

See the appropriate DC Analog

Mux Bus Specifications on page

20

V_IH

–

V

I_ILP

Input current when Applying V_ILPDriving internal pull-down resistor

to P1[0] or P1[1] during

programming or verify

–

0.2

1.5

mA

I_IHP

Input current when applying V_IHPDriving internal pull-down resistor

to P1[0] or P1[1] during

–

programming or verify

V_OLP

V_OHP

Output low voltage during

programming or verify

–

0.75

VIN

V

Output high voltage during

programming or verify

See appropriate DC Analog Mux

Bus Specifications on page 20.

For VIN > 3 V use V_OH4in Table 6

on page 16.

V_OH

Flash_ENPB

Flash_DR

Flash write endurance

Flash data retention

Erase/write cycles per block

50,000

20

–

Following maximum Flash write

cycles; ambient temperature of

55 °C

Years

Document Number: 001-77748 Rev. *F

Page 24 of 45

CYRF89235

2

DC I C Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3, 2.4 V to 3.0 V

and 0 °C  T_A 70 °C, or 1.9 V to 2.4 V and 0 °C  T_A 70 °C, respectively. Typical parameters apply to 3.3 V at 25 °C and are for

design guidance only.

Table 17. DC I²C Specifications

Symbol

V_ILI2C

Description

Input low level

Conditions

3.1 V ≤ VIN ≤ 3.6 V

Min

Typ

–

Max

0.25 × VIN

0.3 × VIN

–

Units

–

V

2.5 V ≤ VIN ≤ 3.0 V

1.9 V ≤ VIN ≤ 2.4 V

1.9 V ≤ VIN ≤ 3.6 V

–

V_IHI2C

Input high level

0.65 × VIN

–

DC Reference Buffer Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4 V to 3.0 V and

0 °C  T_A 70 °C, or 1.9 V to 2.4 V and 0 °C  T_A 70 °C, respectively. Typical parameters apply to 3.3 V at 25 °C and are for design

guidance only.

Table 18. DC Reference Buffer Specifications

Symbol

V_Ref

V_RefHi

Description

Reference buffer output

Conditions

1.9 V to 3.6 V

Min

1

Typ

–

Max

1.05

1.25

Units

V

1.2

–

DC IDAC Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 19. DC IDAC Specifications

Symbol

IDAC_DNL

IDAC_INL

Description

Differential nonlinearity

Integral nonlinearity

Range = 0.5x

Min

–4.5

–5

Typ

–

Max

+4.5

+5

Units

LSB

µA

Notes

–

IDAC_Gain

(Source)

6.64

14.5

42.7

91.1

184.5

–

22.46

47.8

92.3

170

DAC setting = 128 dec.

Range = 1x

–

µA

Range = 2x

–

µA

Range = 4x

–

µA

DAC setting = 128 dec.

Range = 8x

–

426.9

µA

Document Number: 001-77748 Rev. *F

Page 25 of 45

CYRF89235

AC Chip Level Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 20. AC Chip-Level Specifications

Symbol

F_IMO24

Description

Conditions

Min

Typ

Max

Units

IMO frequency at 24 MHz

Setting

–

22.8

24

25.2

MHz

F_IMO12

F_IMO6

F_CPU

IMO frequency at 12 MHz setting

IMO frequency at 6 MHz setting

CPU frequency

–

11.4

5.7

0.75

19

13

40

–

12

6.0

–

12.6

6.3

25.20

50

MHz

kHz

%

F_32K1

F_{32K_U}

DC_IMO

DC_ILO

ILO frequency

32

50

–

ILO untrimmed frequency

Duty cycle of IMO

82

60

ILO duty cycle

60

%

SR_{POWER_UP}Power supply slew rate

VIN slew rate during power-up

After supply voltage is valid

250

–

V/ms

ms

t_XRST

External reset pulse width at

power-up

1

–

t_XRST2

External reset pulse width after Applies after part has booted

power-up

10

–

s

t_OS

Startup time of ECO

N=32

–

1

–

s

t_{JIT_IMO}

6 MHz IMO cycle-to-cycle jitter

(RMS)

0.7

6.7

ns

6 MHz IMO long term N (N = 32)

cycle-to-cycle jitter (RMS)

–

4.3

29.3

ns

6 MHz IMO period jitter (RMS)

–

0.7

0.5

3.3

5.2

ns

12 MHz IMO cycle-to-cycle jitter

(RMS)

12 MHz IMO long term N (N = 32)

cycle-to-cycle jitter (RMS)

–

2.3

5.6

ns

12 MHz IMO period jitter (RMS)

–

0.4

1.0

2.6

8.7

ns

24 MHz IMO cycle-to-cycle jitter

(RMS)

24 MHz IMO long term N (N = 32)

cycle-to-cycle jitter (RMS)

–

1.4

0.6

6.0

4.0

ns

24 MHz IMO period jitter (RMS)

Document Number: 001-77748 Rev. *F

Page 26 of 45

CYRF89235

AC USB Data Timings Specifications

Table 21. AC Characteristics – USB Data Timings

Symbol

t_DRATE

Description

Conditions

Average bit rate

Min

Typ

Max

Units

Full speed data rate

12 –

0.25%

12

12 +

0.25%

MHz

t_JR1

Receiver jitter tolerance

FS Driver jitter

To next transition

To pair transition

To next transition

To pair transition

To SE0 transition

–18.5

–9.0

–3.5

–4.0

–2.0

–

18.5

9

ns

t_JR2

t_DJ1

3.5

4.0

5

t_DJ2

FS Driver jitter

t_FDEOP

Source jitter for differential

transition

t_FEOPT

t_FEOPR

t_FST

Source SE0 interval of EOP

Receiver SE0 interval of EOP

–

160.0

82.0

–

175

–

ns

Width of SE0 interval during

differential transition

14

AC USB Driver Specifications

Table 22. AC Characteristics – USB Driver

Symbol

Description

Transition rise time

Conditions

Min

4

Typ

–

Max

20

Units

ns

t_FR

t_FF

t_FRFM

V_CRS

50 pF

–

Transition fall time

4

–

20

ns

Rise/fall time matching

Output signal crossover voltage

90

1.30

–

111

2.00

%

–

V

Document Number: 001-77748 Rev. *F

Page 27 of 45

CYRF89235

AC General Purpose I/O Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 23. AC GPIO Specifications

Symbol

F_GPIO

Description

Conditions

Min

Typ

Max

6 MHz for

1.9 V <VIN < 2.40 V

12 MHz for

Units

GPIO operating frequency

Normal strong mode

Port 0, 1

0

–

MHz

0

–

MHz

ns

2.40 V < VIN< 3.6 V

t_RISE23

t_RISE23L

t_RISE01

Rise time, strong mode,

Cload = 50 pF

Port 2 or 3 or 4 pins

VIN = 3.0 to 3.6 V,

10% to 90%

15

80

50

Rise time, strong mode low

supply, Cload = 50 pF,

Port 2 or 3 or 4 pins

VIN = 1.9 to 3.0 V,

10% to 90%

15

10

–

ns

Rise time, strong mode,

Cload = 50 pF,

VIN = 3.0 to 3.6 V,

10% to 90%

Ports 0 or 1

LDO enabled or

disabled

t_RISE01L

Rise time, strong mode low

supply, Cload = 50 pF,

Ports 0 or 1

VIN = 1.9 to 3.0 V,

10% to 90%

LDO enabled or

10

–

80

ns

disabled

t_FALL

Fall time, strong mode,

Cload = 50 pF,

all ports

VIN = 3.0 to 3.6 V,

10% to 90%

10

–

50

70

ns

t_FALLL

Fall time,

strong mode low supply,

Cload = 50 pF, all ports

VIN = 1.9 to 3.0 V,

10% to 90%

Figure 10. GPIO Timing Diagram

90%

GPIO Pin

Output

Voltage

10%

t_RISE23

t_RISE01

t_RISE23L

t_RISE01L

t_FALL

t_FALLL

Document Number: 001-77748 Rev. *F

Page 28 of 45

CYRF89235

AC Comparator Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 24. AC Low Power Comparator Specifications

Symbol

t_LPC

Description

Conditions

Min

Typ

Max

Units

Comparator response time,

50 mV overdrive

50 mV overdrive does not include

offset voltage.

–

100

ns

AC External Clock Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 25. AC External Clock Specifications

Symbol

F_OSCEXT

Description

Conditions

Min

Typ

Max

Units

Frequency (external oscillator

frequency)

–

0.75

–

25.20

MHz

High period

–

20.60

150

–

5300

ns

s

Low period

–

Power-up IMO to switch

Document Number: 001-77748 Rev. *F

Page 29 of 45

CYRF89235

AC Programming Specifications

The following table lists the guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 26. AC Programming Specifications

Symbol

t_RSCLK

t_FSCLK

t_SSCLK

Description

Rise time of SCLK

Conditions

Min

1

Typ

–

Max

20

–

Units

ns

–

Fall time of SCLK

1

–

ns

Data setup time to falling edge of

SCLK

40

–

ns

t_HSCLK

Data hold time from falling edge

of SCLK

–

40

–

ns

F_SCLK

Frequency of SCLK

–

0

–

8

MHz

ms

ns

t_ERASEB

t_WRITE

t_DSCLK3

Flash erase time (block)

Flash block write time

18

25

85

Data out delay from falling edge 3.0  V_DD 3.6

of SCLK

t_DSCLK2

t_XRST3

Data out delay from falling edge 1.9  V_DD 3.0

–

130

–

ns

of SCLK

External reset pulse width after Required to enter programming

300

s

power-up

mode when coming out of sleep

t_XRES

XRES pulse length

–

300

0.1

–

1

s

t_VDDWAIT

V_DDstable to wait-and-poll hold

off

ms

t_VDDXRES

V_DDstable to XRES assertion

delay

–

14.27

–

ms

t_POLL

t_ACQ

SDATA high pulse time

–

0.01

3.20

–

200

ms

“Key window” time after a V_DD

ramp acquire event, based on

256 ILO clocks.

19.60

t_XRESINI

“Key window” time after an

XRES event, based on 8 ILO

clocks

–

98

–

615

s

Figure 11. AC Waveform

SCLK (P1[1])

T_RSCLK

T_FSCLK

SDATA (P1[0])

T_SSCLK

T_HSCLK

T_DSCLK

Document Number: 001-77748 Rev. *F

Page 30 of 45

CYRF89235

2

AC I C Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 27. AC Characteristics of the I²C SDA and SCL Pins

Standard Mode

Fast Mode

Symbol

f_SCL

Description

Units

Min

0

Max

100

–

Min

Max

400

–

SCL clock frequency

0

kHz

µs

t_HD;STA

Hold time (repeated) START condition. After this period, the

first clock pulse is generated

4.0

0.6

t_LOW

LOW period of the SCL clock

4.7

4.0

4.7

0

–

1.3

0.6

0

100^[12]

0.6

1.3

0

–

µs

ns

µs

ns

t_HIGH

HIGH Period of the SCL clock

t_SU;STA

t_HD;DAT

t_SU;DAT

t_SU;STO

t_BUF

Setup time for a repeated START condition

Data hold time

–

3.45

–

0.90

–

Data setup time

250

4.0

4.7

–

Setup time for STOP condition

–

Bus free time between a STOP and START condition

Pulse width of spikes are suppressed by the input filter

–

t_SP

–

50

Figure 12. Definition for Timing for Fast/Standard Mode on the I²C Bus

Note

12. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 °C with Sn-Pb or 245 ± 5 °C with Sn-Ag-Cu

paste. Refer to the solder manufacturer specifications.

Document Number: 001-77748 Rev. *F

Page 31 of 45

CYRF89235

SPI Master AC Specifications

Table 28. SPI Master AC Specifications

Symbol

F_SCLK

Description

Conditions

Min

Typ

Max

Units

SCLK clock frequency

VIN 2.4 V

–

6

3

MHz

VIN < 2.4 V

–

DC

SCLK duty cycle

–

50

–

%

t_SETUP

MISO to SCLK setup time

VIN  2.4 V

VIN < 2.4 V

60

100

–

ns

t_HOLD

SCLK to MISO hold time

SCLK to MOSI valid time

MOSI high time

–

40

–

40

–

ns

t_{OUT_VAL}

t_{OUT_HIGH}

40

Figure 13. SPI Master Mode 0 and 2

SPI Master, modes 0 and 2

1/F_SCLK

T_HIGH

T_LOW

SCLK

(mode 0)

SCLK

(mode 2)

T_SETUP

T_HOLD

MISO

(input)

LSB

MSB

T_{OUT_SU}

T_{OUT_H}

MOSI

(output)

Figure 14. SPI Master Mode 1 and 3

SPI Master, modes 1 and 3

1/F_SCLK

T_HIGH

T_LOW

SCLK

(mode 1)

SCLK

(mode 3)

T_SETUP

T_HOLD

MISO

(input)

MSB

LSB

T_{OUT_SU}

T_{OUT_H}

MOSI

(output)

LSB

MSB

Document Number: 001-77748 Rev. *F

Page 32 of 45

CYRF89235

SPI Slave AC Specifications

Table 29. SPI Slave AC Specifications

Symbol

F_SCLK

Description

SCLK clock frequency

SCLK low time

Conditions

Min

Typ

–

Max

4

Units

MHz

ns

–

t_LOW

42

–

t_HIGH

SCLK high time

42

–

ns

t_SETUP

t_HOLD

MOSI to SCLK setup time

SCLK to MOSI hold time

SS high to MISO valid

SCLK to MISO valid

30

–

ns

50

–

ns

t_{SS_MISO}

t_{SCLK_MISO}

t_{SS_HIGH}

t_{SS_CLK}

t_{CLK_SS}

–

153

125

–

ns

–

ns

SS high time

50

–

ns

Time from SS low to first SCLK

Time from last SCLK to SS high

2/SCLK

–

ns

–

ns

Figure 15. SPI Slave Mode 0 and 2

SPI Slave, modes 0 and 2

T_{SS_HIGH}

T_{CLK_SS}

T_{SS_CLK}

/SS

1/F_SCLK

T_HIGH

T_LOW

SCLK

(mode 0)

SCLK

(mode 2)

T_{OUT_H}

T_{SS_MISO}

MISO

(output)

T_SETUP

T_HOLD

MOSI

(input)

LSB

MSB

Document Number: 001-77748 Rev. *F

Page 33 of 45

CYRF89235

Figure 16. SPI Slave Mode 1 and 3

SPI Slave, modes 1 and 3

T_{SS_CLK}

T_{CLK_SS}

/SS

1/F_SCLK

T_HIGH

T_LOW

SCLK

(mode 1)

SCLK

(mode 3)

T_{OUT_H}

T_{SCLK_MISO}

T_{SS_MISO}

MISO

(output)

LSB

MSB

T_SETUP

T_HOLD

MOSI

(input)

MSB

LSB

Document Number: 001-77748 Rev. *F

Page 34 of 45

CYRF89235

Electrical Specifications - RF Section

Symbol

Description

Supply voltage

Min

Typ

Max

Units

Test Condition and Notes

V_IN

DC power supply voltage range

Current consumption

1.9

–

3.6

VDC Input to V_INpins

I_{DD_TX2}

I_{DD_TX12}

I_{DD_RX}

Current consumption – Tx

–

18.5

13.7

18

–

mA

µA

Transmit power PA2.

Transmit power PA12.

Current consumption – Rx

Current consumption – idle

Current consumption – sleep

I_{DD_IDLE1}

I_{DD_SLPx}

1.1

1

Temperature = +25 °C.

Using firmware sleep patch.

Register 27 = 0x1200,

for V_IN≥ 3.00 VDC only

I_{DD_SLPr}

–

8

–

µA

Temperature = +25 °C;

using firmware sleep patch

Register 27 = 0x4200.

I_{DD_SLPh}

38

Temperature = +70 °C

‘C’ grade part;

using firmware sleep patch

Register 27 = 0x4200

V_IH

Logic input high

Logic input low

0.8 VIN

–

1.2 VIN

0.8

V

V_IL

0

–

I_{_LEAK_IN}

Input leakage current

10

µA

V_OH

Logic output high

0.8 VIN

–

8

–

V

I_OH= 100 µA source

I_OL= 100 µA sink

MISO in tristate

7 pF cap. load

V_OL

Logic output low

–

0.4

10

25

I_{_LEAK_OUT}

T_{_RISE_OUT}

T_{_RISE_IN}

T_{r_spi}

Output leakage current

Rise/fall time (SPI MISO)

Rise/fall time (SPI MOSI)

CLK rise, fall time (SPI)

µA

ns

Requirement for error-free

register reading, writing.

F_{_OP}

Operating frequency range

2400

–

2482

MHz Usage on-the-air is subject to

local regulatory agency

restrictions regarding operating

frequency.

V_{SWR_I}

Antenna port mismatch

(Z₀= 50 )

–

<2:1

–

VSWR Receive mode. Measured using

LC matching circuit

VSWR_{_O}

VSWR Transmit mode. Measured using

LC matching circuit

Receive section

Measured using LC matching

circuit for BER  0.1%

Document Number: 001-77748 Rev. *F

Page 35 of 45

CYRF89235

Electrical Specifications - RF Section (continued)

Symbol

RxS_base

Description

Min

Typ

Max

Units

Test Condition and Notes

Receiver sensitivity (FEC off)

–

–87

–

dBm Room temperature only

0-ppm crystal frequency error.

RxS_temp

RxS_ppm

–

–84

–

dBm Over temperature;

0-ppm crystal frequency error.

dBm Room temperature only

80-ppm total frequency error

(± 40-ppm crystal frequency

error, each end of RF link)

RxS_temp+ppm

–

–80

–

dBm Over temperature;

80-ppm total frequency error

(± 40-ppm crystal frequency

error, each end of RF link)

R_xmax-sig

Ts

Maximum usable signal

Data (Symbol) rate

–20

–

0

1

–

dBm Room temperature only

µs

Minimum Carrier/Interference ratio

For BER  0.1%.

Room temperature only.

CI_{_cochannel}

CI_{_1}

Co-channel interference

–

+9

+6

–

dB

–60-dBm desired signal

Adjacent channel interference,

1-MHz offset

CI_{_2}

CI_{_3}

OBB

Adjacent channel interference,

2-MHz offset

–

–12

–24

–

dB

–60-dBm desired signal

–67-dBm desired signal

Adjacent channel interference,

3-MHz offset

Out-of-band blocking

 –27

dBm 30 MHz to 12.75 GHz

Measured with ACX BF2520

ceramic filter on ant. pin.

–67-dBm desired signal,

BER  0.1%.

Room temperature only.

Transmit section

P_AVH

Measured using a LC matching

circuit

RF output power

–

+1

–

dBm PA0

(PA_GN = 0, Reg9 = 0x1820).

Room temperature only

P_AVL

–11.2

dBm PA12

(PA_GN = 12, Reg9 = 0x1E20).

Room temperature only.

TxP_fx2

TxP_fx3

Second harmonic

–

–45

–

dBm Measured using a LC matching

circuit. Room temperature only.

Third and higher harmonics

–45

dBm Measured using a LC matching

circuit. Room temperature only.

Modulation characteristics

Df1_avg

–

263

255

–

kHz Modulation pattern: 11110000...

kHz Modulation pattern: 10101010...

Df2_avg

In-band spurious emission

IBS_2

IBS_3

IBS_4

2-MHz offset

3-MHz offset

 4-MHz offset

–

–20

–30

–

dBm

–30

Document Number: 001-77748 Rev. *F

Page 36 of 45

CYRF89235

Electrical Specifications - RF Section (continued)

Symbol

Description

Min

Typ

Max

Units

Test Condition and Notes

RF VCO and PLL section

F_step

L_100k

L_1M

Channel (Step) size

SSB phase noise

1

–75

–105

–

MHz

dBc/Hz 100-kHz offset

dBc/Hz 1-MHz offset

–

dF_X0

Crystal oscillator frequency error

RF PLL settling time

–40

–

+40

ppm Relative to 12-MHz crystal

reference frequency

T_HOP

100

250

150

350

µs

Settle to within 30 kHz of final

value. AutoCAL off.

T_{HOP_AC}

–

µs

Settle to within 30 kHz of final

value. AutoCAL on.

LDO voltage regulator section

V_DODropout voltage

–

0.17

0.3

V

Measured during receive state

Document Number: 001-77748 Rev. *F

Page 37 of 45

CYRF89235

Initialization Timing Requirements

Table 30. Initialization Timing Requirements

Timing

Min

Max

Unit

Notes

Parameter

T_RSU

–

30 / 150

ms

30 ms Reset setup time necessary to ensure complete Reset for VIN = 6.5 mV/s,

150 ms Reset setup time necessary to ensure complete Reset for VIN = 2 mV/s

T_RPW

T_CMIN

T_VIN

1

3

–

10

–

µs

Reset pulse width necessary to ensure complete reset

ms

Minimum recommended crystal oscillator and APLL settling time

6.5 / 2

mV/s Maximum ramp time for V_IN, measured from 0 to 100% of final voltage.

For example, if V_IN= 3.3 V, the max ramp time is 6.5 × 3.3 = 21.45 ms.

If V_IN= 1.9 V, the max ramp time = 6.5 × 1.9 = 12.35 ms.

Reset setup time necessary to ensure complete Reset for VIN = 6.5mV/s

Figure 17. Initialization Flowchart

Initialize

CYRF89235 at

power-up

MCU generates

negative- going

RST_n pulse

Wait Crystal

Enable Time

Registers,

beginning with

Reg[27]

Initialization

Done

RST_n pulls up

along with Vin

Document Number: 001-77748 Rev. *F

Page 38 of 45

CYRF89235

SPI Timing Requirements

Table 31. SPI Timing Requirements

Timing

Min

Max

Unit

Notes

Parameter

T_SSS

20

200

40

83

30

10

200

–

ns

Setup time from assertion of SPI_SS to CLK edge

Hold time required deassertion of SPI_SS

CLK minimum high time

T_SSH

T_SCKH

T_SCKL

T_SCK

–

CLK minimum low time

–

Maximum CLK clock is 12 MHz

T_SSU

–

MOSI setup time

T_SHD

–

MOSI hold time

T_{SS_SU}

T_{SS_HD}

T_SDO

–

Before SPI_SS enable, CLK hold low time requirement

Minimum SPI inactive time

–

35

5

MISO setup time, ready to read

T_SDO1

T_SDO2

T1 Min_R50

T1 Min

–

If MISO is configured as tristate, MISO assertion time

If MISO is configured as tristate, MISO deassertion time

When reading register 50 (FIFO)

–

250

–

350

83

–

When writing Register 50 (FIFO), or reading/writing any registers other than

register 50.

Figure 18. Power-on and Register Programming Sequence

T_VIN

V_IN

RST_n

BRCLK

Clock stable

Clock unstable

SPI_SS

SPI Activity

T_RPW

Write Reg[27]=

(not drawn to scale)

T_RSU

T_CMIN

0x4200

■ After register initialization, CYRF89235 is ready to transmit or receive.

Document Number: 001-77748 Rev. *F

Page 39 of 45

CYRF89235

Packaging Information

This section illustrates the packaging specifications for the PRoC-USB device, along with the thermal impedances for each package.

Important Note

Emulation tools may require a larger area on the target PCB than the chip’s footprint.

Packaging Dimensions

Figure 19. 40-pin QFN (6 × 6 × 1.0 mm) LT40B 3.5 × 3.5 mm E-Pad (Sawn) Package Outline, 001-13190

001-13190 *H

Document Number: 001-77748 Rev. *F

Page 40 of 45

CYRF89235

Thermal Impedances

Table 32. Thermal Impedances per Package

[13]

Package

Typical _JA

Typical _JC

40-pin QFN ^[14]

27 °C/W

34 °C/W

Capacitance on Crystal Pins

Table 33. Typical Package Capacitance on Crystal Pins

Package

Package Capacitance

40-pin QFN

3.6 pF

Solder Reflow Peak Temperature

Following is the minimum solder reflow peak temperature to achieve good solderability.

Table 34. Solder Reflow Peak Temperature

Package

Minimum Peak Temperature ^[15]

Maximum Peak Temperature

260

265

40-pin QFN

Notes

13. T_J= T_A+ Power x 

JA.

14. To achieve the thermal impedance specified for the package, solder the center thermal pad to the PCB ground plane.

15. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 °C with Sn-Pb or 245 ± 5 °C with Sn-Ag-Cu paste.

Refer to the solder manufacturer specifications.

Document Number: 001-77748 Rev. *F

Page 41 of 45

CYRF89235

Ordering Information

Table 35. Ordering Information

Flash SRAM

Ordering Code

Package Information

40-pin QFN (6 × 6 mm)

No. of GPIOs

(KB)

CYRF89235-40LTXC

32

2

13

Ordering Code Definitions

235

40

LT

C

89

CY

RF

X

Thermal Rating

I

,

C = Commercial , = Industrial E = Extended

X = Lead-Free, X absent = Leaded

Package : LT = QFN

40 pin

235 = PRoC-USB

Family Code 89 = Wireless

:

Marketing code

radio frequency

RF = Wireless

product family

(

)

: CY = Cypress

Company ID

Document Number: 001-77748 Rev. *F

Page 42 of 45

CYRF89235

Acronyms

Document Conventions

Units of Measure

Acronym

Description

API

application programming interface

central processing unit

general purpose I/O

in-circuit emulator

Symbol

C

dB

fF

Unit of Measure

CPU

GPIO

ICE

degree Celsius

decibels

femtofarad

hertz

ILO

internal lowspeed oscillator

internal main oscillator

input/output

Hz

KB

Kbit

kHz

k

MHz

M

A

F

IMO

1024 bytes

1024 bits

I/O

LSb

least significant bit

kilohertz

LVD

low voltage detect

kilohm

megahertz

megaohm

MSb

POR

PPOR

PSoC

SLIMO

SRAM

most significant bit

power-on reset

microampere

microfarad

microhenry

microsecond

microvolt

precision power-on reset

programmable system-on-chip

slow IMO

H

s

static random access memory

V

Vrms

W

mA

ms

mV

nA

ns

microvolts root-mean-square

microwatts

milliampere

millisecond

millivolt

nanoampere

nanosecond

nanovolt

nV

W

ohm

pA

pF

picoampere

picofarad

pp

peak-to-peak

parts per million

picosecond

samples per second

sigma: one standard deviation

volt

ppm

ps

sps



V

Numeric Naming

Hexadecimal numbers are represented with all letters in

uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or

‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’

prefix, the C coding convention. Binary numbers have an

appended lowercase ‘b’ (for example, ‘01010100b’ or

‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or ‘0x’ are

decimal.

Document Number: 001-77748 Rev. *F

Page 43 of 45

CYRF89235

Document History Page

Document Title: CYRF89235, PRoC™ USB

Document Number: 001-77748

Orig. of

Change

Submission

Rev.

ECN No.

Description of Change

Date

**

3554967

3605878

ANTG

04/03/2012 New data sheet.

*A

05/02/2012 Modified title.

Updated status “Company Confidential” of the datasheet.

Changed “PRoC NL Dongle” to “PRoC-USB” everywhere in the datasheet.

*B

*C

3714928

3747532

AKHL

08/16/2012 Major text update. Added Electrical Specifications - RF Section.

09/18/2012 Removed “Company Confidential” tag in the header.

Replaced package diagram spec with 001-13190.

*D

3784571

AKHL

10/26/2012 Updated Functional Overview (Added Transmit Power Control).

Updated Development Tools (Updated PSoC Designer Software Subsystems

(Added Device Programmers)).

Updated Electrical Specifications - RF Section (Replaced CYRF8935 with

CYRF89235 in Figure 17 and also in the last bullet point below Figure 18).

Updated Packaging Information (No update in package diagram, updated

Thermal Impedances (Updated Table 32)).

Updated in new template.

*E

*F

3872679

3982770

AKHL

01/19/2013 Updated PRoC-USB Features (Replaced “Up to 37 general-purpose I/Os

(GPIOs)” with “Up to 13 general-purpose I/Os (GPIOs)”).

Updated Electrical Specifications (Updated DC Chip-Level Specifications

(Changed maximum value of V_INUSBparameter from 3.60 V to 3.45 V in

Table 7)).

05/15/2013 Updated PRoC-USB Features.

Updated PRoC-USB Logical Block Diagram.

Updated Functional Overview:

Updated WirelessUSB-NL Subsystem (Updated Figure 6).

Updated Transmit Power Control (Updated Table 1).

Updated Electrical Specifications:

Updated Absolute Maximum Ratings (Updated Table 5).

Updated Operating Temperature (Updated Table 6).

Updated DC Chip-Level Specifications (Updated Table 7).

Updated DC IDAC Specifications (Updated Table 19).

Updated Electrical Specifications - RF Section:

Updated SPI Timing Requirements (Updated Table 31).

Updated Packaging Information:

No change in Package Diagram revision.

Removed “Package Handling”.

Updated Capacitance on Crystal Pins (Updated Table 33).

Updated Solder Reflow Peak Temperature (Updated Table 34).

Updated Ordering Information:

No change in part numbers.

Added Ordering Code Definitions.

Document Number: 001-77748 Rev. *F

Page 44 of 45

CYRF89235

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

Products

PSoC Solutions

Automotive

cypress.com/go/automotive

cypress.com/go/clocks

cypress.com/go/interface

cypress.com/go/powerpsoc

cypress.com/go/plc

psoc.cypress.com/solutions

PSoC 1 | PSoC 3 | PSoC 5

Clocks & Buffers

Interface

Lighting & Power Control

Memory

cypress.com/go/memory

cypress.com/go/image

cypress.com/go/psoc

Optical & Image Sensing

PSoC

Touch Sensing

USB Controllers

Wireless/RF

cypress.com/go/touch

cypress.com/go/USB

cypress.com/go/wireless

any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for

medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress

integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-77748 Rev. *F

Revised May 15, 2013

Page 45 of 45

PSoC Designer™ is a trademark and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation.

2

Purchase of I C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I C Patent Rights to use these components in an I C system, provided

2

that the system conforms to the I C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors.

All products and company names mentioned in this document may be the trademarks of their respective holders.

厂商	型号	描述	页数
KYOCERA AVX	CYR10	玻璃电容器CYR10 ， 15 （可靠性指标） M23269 / 01 ， 02 （ QPL至MIL-PRF- 23269 ）[ Glass Capacitors CYR10, 15 (Established Reliability) M23269/01, 02 (QPL to MIL-PRF-23269) ]	2 页
FOXCONN	CYR2-AP03MJ04	[ Interconnection Device ]	1 页
KYOCERA AVX	CYR51	玻璃电容器CYR51 ， 52 ， 53 （可靠性指标） M23269 / 10 （ QPL至MIL-PRF- 23269 ）[ Glass Capacitors CYR51, 52, 53 (Established Reliability) M23269/10 (QPL to MIL-PRF-23269) ]	2 页
KYOCERA AVX	CYR52	玻璃电容器CYR51 ， 52 ， 53 （可靠性指标） M23269 / 10 （ QPL至MIL-PRF- 23269 ）[ Glass Capacitors CYR51, 52, 53 (Established Reliability) M23269/10 (QPL to MIL-PRF-23269) ]	2 页
KYOCERA AVX	CYR53	玻璃电容器CYR51 ， 52 ， 53 （可靠性指标） M23269 / 10 （ QPL至MIL-PRF- 23269 ）[ Glass Capacitors CYR51, 52, 53 (Established Reliability) M23269/10 (QPL to MIL-PRF-23269) ]	2 页
CYPRESS	CYRF69103	无线可编程片上低功耗[ Programmable Radio on Chip Low Power ]	73 页
CYPRESS	CYRF69103-40LFXC	无线可编程片上低功耗的16位自由运行定时器[ Programmable Radio on Chip Low Power 16-bit free running timer ]	68 页
CYPRESS	CYRF69103-40LTXC	无线可编程片上低功耗[ Programmable Radio on Chip Low Power ]	72 页
CYPRESS	CYRF69103A-40LFXC	无线可编程片上低功耗[ Programmable Radio on Chip Low Power ]	68 页
CYPRESS	CYRF69103_08	无线可编程片上低功耗[ Programmable Radio on Chip Low Power ]	65 页