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TZA3014U

型号：

TZA3014U

描述：

2.5 Gb / s的postampli连接器与电平检测器[ 2.5 Gbits/s postamplifier with level detector ]

品牌：

NXP[ NXP ]

页数：

28 页

PDF大小：

163 K

下载PDF手册
INTEGRATED CIRCUITS  
DATA SHEET  
TZA3014  
2.5 Gbits/s postamplifier with level  
detector  
Product specification  
2001 Jun 25  
Supersedes data of 2000 Aug 09  
File under Integrated Circuits, IC19  
Philips Semiconductors  
Product specification  
2.5 Gbits/s postamplifier with level detector  
TZA3014  
FEATURES  
APPLICATIONS  
• Postamplifier for SDH/SONET transponder  
• Single 3.3 V power supply  
• Wideband operation from 50 kHz to 2.5 GHz (typical  
value)  
• SDH/SONET wavelength converter  
• PECL driver  
• Fully differential  
• Fibre channel arbitrated loop  
• Signal level detectors  
• On-chip DC-offset compensation without external  
capacitor  
• Swing converter CML 200 mV (p-p) to  
PECL 800 mV (p-p)  
• Interfacing with supplied positive or negative logic  
• Positive Emitter Coupled Logic (PECL) or Current-Mode  
Logic (CML) compatible data outputs adjustable from  
200 to 800 mV (p-p) single-ended  
• 2.5 GHz clock amplification.  
GENERAL DESCRIPTION  
• Power-down capability for unused output or detector  
• Rise and fall times of 80 ps (typical value)  
• Inverted output possible  
The TZA3014 is a low gain postamplifier with a LOS  
detector and a RSSI designed for use in critical signal path  
control applications, such as loop-through or Wavelength  
Division Multiplexing (WDM). The signal path is capable of  
operating from 50 kHz up to 2.5 GHz.  
• Input level detection circuit for Received Signal Strength  
Indicator (RSSI) and Loss Of Signal (LOS),  
programmable from 0.4 to 400 mV (p-p) single-ended,  
with open-drain comparator output for directly  
interfacing positive or negative logic  
The TZA3014 can be delivered in HTQFP32 and HBCC32  
packages and as bare die.  
• Reference voltage for output level and LOS adjustment  
• HTQFP32 and HBCC32 plastic packages with exposed  
pad  
• Mute input.  
ORDERING INFORMATION  
TYPE  
PACKAGE  
NUMBER  
NAME  
DESCRIPTION  
VERSION  
TZA3014HT  
TZA3014VH  
TZA3014U  
HTQFP32 plastic, heatsink thin quad flat package; 32 leads; body 5 × 5 × 1.0 mm  
SOT547-2  
SOT560-1  
−
HBCC32  
plastic, heatsink bottom chip carrier; 32 terminals; body 5 × 5 × 0.65 mm  
bare die; 2.22 × 2.22 × 0.28 mm  
−
2001 Jun 25  
2
Philips Semiconductors  
Product specification  
2.5 Gbits/s postamplifier with level detector  
TZA3014  
BLOCK DIAGRAM  
disable LOS output  
comparator  
32 (40)  
10 (12)  
(31) 25  
GNDB  
GNDA  
LOSTH  
5 kΩ  
RSSI  
(35) 27  
(34) 26  
LOS  
1×  
RSSI  
offset compensation  
offset compensation  
12 (15)  
29 (37)  
level  
LEVEL  
INV  
(30) 24  
1
2
3
V
CCB  
V
CCA  
(29) 23  
(28) 22  
(27) 21  
OUT  
IN  
INQ  
OUTQ  
cross-over  
switch  
buffer amplifier  
4
V
CCB  
V
CCA  
15 (19)  
31 (39)  
(17) 14  
BAND GAP  
REFERENCE  
V
TEST  
TZA3014  
ref  
MUTE  
MGU122  
The numbers in parentheses refer to the pad numbers of the bare die version.  
Fig.1 Block diagram.  
2001 Jun 25  
3
Philips Semiconductors  
Product specification  
2.5 Gbits/s postamplifier with level detector  
TZA3014  
PINNING  
SYMBOL  
PIN  
PAD  
TYPE(1)  
DESCRIPTION  
VCCA  
IN  
1
2
1
2
S
I
supply voltage for input and LOS detector  
differential input; complimentary to pin INQ; DC bias level is set internally  
at approximately VCC − 0.33 V  
INQ  
3
3
I
differential input; complimentary to pin IN; DC bias level is set internally at  
approximately VCC − 0.33 V  
VCCA  
n.c.  
4
−
4
5
S
−
−
−
I
supply voltage for input and LOS detector  
not connected  
n.c.  
−
6
not connected  
n.c.  
5
7
not connected  
n.c.  
6
8
not connected  
n.c.  
7
9
I
not connected  
n.c.  
8
10  
11  
12  
S
S
I
not connected  
n.c.  
9
not connected  
LOSTH  
10  
input for setting threshold level of LOS detector; threshold level is set by  
connecting external resistors between pins VCCA and Vref; when forced to  
GNDA or not connected, the LOS detector is switched off  
n.c.  
11  
−
13  
14  
15  
I
−
I
not connected  
not connected  
n.c.  
LEVEL  
12  
input for setting AC level of the output circuit; output signal level is set by  
connecting external resistors between pins VCCA and Vref; when forced to  
VCCA or not connected, pins OUT and OUTQ will be switched off  
n.c.  
Vref  
13  
14  
16  
17  
I
not connected  
O
reference voltage for programming output level circuit and LOS threshold;  
typical value is VCC − 1.6 V; no external capacitor allowed  
n.c.  
−
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
−
I
not connected  
TEST  
n.c.  
15  
16  
17  
18  
19  
20  
−
for test purposes only; to be left open-circuit in the application  
S
S
O
O
S
−
not connected  
n.c.  
not connected  
n.c.  
not connected  
n.c.  
not connected  
n.c.  
not connected  
n.c.  
not connected  
n.c.  
−
−
not connected  
VCCB  
OUTQ  
OUT  
VCCB  
GNDB  
n.c.  
21  
22  
23  
24  
25  
−
S
O
O
S
S
O
supply voltage for output circuit  
PECL or CML compatible differential output; complimentary to pin OUT  
PECL or CML compatible differential output; complimentary to pin OUTQ  
supply voltage for output circuit  
ground for output circuit  
not connected  
n.c.  
−
O-DRN not connected  
2001 Jun 25  
4
Philips Semiconductors  
Product specification  
2.5 Gbits/s postamplifier with level detector  
TZA3014  
SYMBOL  
PIN  
PAD  
TYPE(1)  
DESCRIPTION  
RSSI  
LOS  
26  
27  
34  
35  
O
RSSI output  
O-DRN output of LOS detector; direct drive to either positive or negative supplied  
logic via internal 5 kΩ resistor  
n.c.  
INV  
28  
29  
36  
37  
TTL  
TTL  
not connected  
input to invert the signal at pins OUT and OUTQ; supports positive or  
negative logic  
n.c.  
30  
31  
38  
39  
TTL  
TTL  
not connected  
MUTE  
input to mute the output signal on pins OUT (‘0’) and OUTQ (‘1’); supports  
positive or negative logic  
GNDA  
GNDp  
32  
40  
S
S
ground for input and LOS detector  
ground pad (exposed die pad)  
pad  
−
Note  
1. Pin type abbreviations: O = output, I = input, S = power supply, TTL = logic input and O-DRN = open-drain output.  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
V
V
V
CCB  
CCA  
IN  
OUT  
exposed pad  
INQ  
OUTQ  
V
CCA  
n.c.  
CCB  
TZA3014HT  
20 n.c.  
n.c.  
n.c.  
n.c.  
n.c.  
n.c.  
n.c.  
19  
18  
17  
GNDp  
MGU123  
Fig.2 Pin configuration HTQFP32 package.  
2001 Jun 25  
5
Philips Semiconductors  
Product specification  
2.5 Gbits/s postamplifier with level detector  
TZA3014  
V
V
1
32 31 30 29 28 27 26  
exposed pad  
25  
CCA  
V
IN  
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
CCB  
INQ  
OUT  
OUTQ  
CCA  
n.c.  
V
TZA3014VH  
CCB  
n.c.  
n.c.  
n.c.  
n.c.  
n.c.  
n.c.  
GNDp  
n.c.  
9
10 11 12 13 14 15 16  
17  
MGU124  
Fig.3 Pin configuration HBCC32 package.  
2001 Jun 25  
6
Philips Semiconductors  
Product specification  
2.5 Gbits/s postamplifier with level detector  
TZA3014  
FUNCTIONAL DESCRIPTION  
The TZA3014 is a postamplifier with a RSSI circuit to  
handbook, halfpage  
V
CCA  
provide output signals for RSSI and LOS (see Fig.1). The  
input signal can be amplified to a programmable level.  
An active level control circuit ensures this level. The  
control voltage on pin INV inverts the outputs, so avoiding  
a required complicated Printed Circuit Board (PCB) layout.  
An offset compensation circuit minimizes the effect of any  
voltage offset present at the input.  
12 pF  
420 Ω  
50 Ω  
50 Ω  
IN  
INQ  
The RSSI and LOS detector are based on a 7-stage  
‘successive detection’ circuit which provides a logarithmic  
output. The LOS detector is followed by a comparator with  
a programmable threshold. The input signal level detection  
is implemented to check if the input signal is above the  
user-programmed level. The user can ensure that data will  
only be transmitted when the input signal-to-noise ratio is  
sufficient for low bit error rate system operation. A second  
offset compensation circuit minimizes the effect of any  
voltage offset present in the logarithmic amplifier.  
GNDA  
MGU125  
Fig.4 RF input circuit.  
RF output level adjustment  
RF input circuit  
The output level can be made compatible with CML or  
PECL by adjusting the voltage on pin LEVEL. The  
DC voltages on pins OUT and OUTQ relate to the  
DC voltage on pin LEVEL. Due to the effect of the 50 Ω  
load resistance at the receiving end, for a given  
peak-to-peak value on pins OUT and OUTQ, a different  
voltage is required on pin LEVEL in case the output is  
AC-coupled and when the output is DC-coupled  
(see Figs 5 and 6).  
The input circuit contains internal 50 Ω resistors  
decoupled to VCCA via an internal common mode 12 pF  
capacitor (see Fig.4).  
The inputs IN and INQ are DC-biased at approximately  
VCCA − 0.33 V by an internal reference generator. The  
TZA3014 can be DC-coupled, but AC coupling is  
preferred. When DC-coupled, the drive source must  
operate within the allowable input range  
(VCCA − 1.0 V to VCCA + 0.3 V). The DC-offset voltage  
should stay below a few millivolts since the internal  
DC-offset compensation circuit has a limited correction  
range. When AC-coupled, do not use capacitors that  
cause a 3 dB cut-off point at 50 kHz (postamplifier cut-off  
point) or at 1 MHz (RSSI cut-off point).  
When pin LEVEL is not connected or connected to VCCA  
the postamplifier is in power-down state (see Fig.5).  
,
DC-offset compensation loop  
A DC-offset compensation loop connected between the  
amplifier output and the buffer input maintains the toggle  
point at the buffer input when there is no input signal  
(see Fig.1). This active control circuit is integrated and  
does not require an external capacitor. The loop  
time constant determines the lower cut-off frequency of  
the amplifier chain, and is internally fixed at approximately  
5 kHz.  
RF output circuit  
Matching the outputs of the postamplifier (see Fig.5) is not  
mandatory. In most applications, the receiving end of the  
transmission line will be properly matched, causing very  
few reflections.  
Matching the transmitting end of the transmission line to  
absorb reflections only, is recommended for very sensitive  
applications.  
In such cases, 100 Ω pull-up resistors should be  
connected to VCCB and pins OUT and OUTQ as close as  
possible to the IC. However, for most applications these  
matching resistors are not required.  
2001 Jun 25  
7
Philips Semiconductors  
Product specification  
2.5 Gbits/s postamplifier with level detector  
TZA3014  
V
V
(27) 21  
100 Ω  
4
CCA  
CCB  
50  
Ω
50  
Ω
100 Ω  
R1  
V
OUT  
(29) 23  
o
OUTQ  
(28) 22  
Transmission  
lines  
V
12 (15)  
14 (17)  
LEVEL  
LEVEL  
R2  
REG  
V
CC  
V
V
V
LEVEL  
ref  
o(se)(p-p)  
V
o
(V)  
MGU126  
VLEVEL = 0.5 × Vo(se)(p-p)  
.
R1  
R1 + R2  
VLEVEL = Vref  
×
----------------------  
VLEVEL = VCC for power-down mode.  
The numbers in parentheses refer to the pad numbers of the bare die version.  
a. DC-coupled.  
V
V
CCA  
(27) 21  
100 Ω  
4
CCB  
50  
Ω
50  
Ω
100 Ω  
R1  
V
OUT  
(29) 23  
o
OUTQ  
(28) 22  
Transmission  
lines  
V
12 (15)  
14 (17)  
LEVEL  
R2  
LEVEL  
V
CC  
REG  
V
ref  
V
V
LEVEL  
o(se)(p-p)  
V
o
(V)  
MGU127  
VLEVEL = 1.5 × Vo(se)(p-p)  
.
R1  
R1 + R2  
VLEVEL = Vref  
×
----------------------  
VLEVEL = VCC for power-down mode.  
The numbers in parentheses refer to the pad numbers of the bare die version.  
b. AC-coupled.  
Fig.5 RF output configurations.  
2001 Jun 25  
8
Philips Semiconductors  
Product specification  
2.5 Gbits/s postamplifier with level detector  
TZA3014  
MGU128  
1000  
V
o(se)(p-p)  
(mV)  
800  
DC-coupled  
AC-coupled  
600  
400  
200  
0
0
20  
40  
60  
80  
100  
V
(% of V  
)
ref  
LEVEL  
Fig.6 Output signal as a function of VLEVEL  
.
TTL logic inputs MUTE and INV  
Table 1 OUT and OUTQ as a function of input MUTE  
It should be noted that switch control voltages in positive  
logic are inverted in case a negative supply voltage is used  
(see Fig.7).  
MUTE  
OUT  
IN  
OUTQ  
INQ  
‘1’  
0
1
‘0’  
Output signal as a function of inputs MUTE and INV  
Table 2 OUT and OUTQ as a function of input INV  
The default logic level for inputs MUTE and INV is 0 in  
case these pins are not connected. See Tables 1 and 2.  
INV  
OUT  
OUTQ  
0
1
IN  
INQ  
IN  
INQ  
2001 Jun 25  
9
Philips Semiconductors  
Product specification  
2.5 Gbits/s postamplifier with level detector  
TZA3014  
logic  
level  
MGS560  
2.0 V  
(1)  
2.0 V  
1
0
TTL  
0.8 V  
0.8 V  
1.4 V  
1.4 V  
V
GND  
CC  
−1  
0
+1  
+2  
+3  
+4  
+5  
+6  
V (V)  
I
a. Positive supply voltage (VCC) and positive input voltage (VCC).  
logic  
level  
MGS559  
2.0 V  
2.0 V  
1
(1)  
TTL  
0.8 V  
0.8 V  
0
1.4 V  
1.4 V  
V
V
EE  
GND  
CC  
−4  
−3  
−2  
−1  
0
+1  
+2  
+3  
V (V)  
I
b. Negative supply voltage (VEE) and positive input voltage (VCC).  
logic  
level  
MGS558  
2.0 V  
(1)  
2.0 V  
1
TTL  
0.8 V  
0.8 V  
0
1.4 V  
1.4 V  
V
GND  
EE  
−4  
−3  
−2  
−1  
0
+1  
+2  
+3  
V (V)  
I
c. Negative supply voltage (VEE) and negative input voltage (VEE).  
(1) Level not defined.  
Fig.7 Logic levels on pins MUTE and INV as a function of the supply voltages.  
10  
2001 Jun 25  
Philips Semiconductors  
Product specification  
2.5 Gbits/s postamplifier with level detector  
TZA3014  
RSSI and LOS detection  
The TZA3014 monitors the level of the input AC signal.  
This function can prevent the output circuit from reacting to  
noise in case there is no valid input signal, and can ensure  
that only data is transmitted when there is sufficient input  
signal for low bit error rate system operation.  
handbook, halfpage3  
MGU129  
10  
V
i(se)(p-p)  
(mV)  
2
10  
The RSSI uses seven limiting amplifiers in a ‘successive  
detection’ topology to closely approximate a logarithmic  
response over a total range of 70 dB. The AC signal is  
full-wave rectified by a detector at each amplifier stage.  
Each detector output has a current driver followed by a  
low-pass filter providing the first stage in the recovery of  
the average value of the demodulated input signal. The  
total current from each detector output is converted to a  
voltage by an internal load resistor and then buffered.  
When the RSSI output is used, input pin LOSTH is not to  
be connected to GND (standby mode). The RSSI output  
follows the internal 3 dB hysteresis of the LOS  
LOS  
LOW-level  
(1)  
(2)  
10  
1
LOS  
HIGH-level  
(3)  
−1  
10  
10  
20  
30  
40  
50  
LOSTH  
60  
(% of V  
70  
comparator. The LOS comparator detects when the input  
signal level rises above a programmable fixed threshold.  
Then pin LOS gets a LOW-level. The threshold level is  
determined by the voltage on pin LOSTH and by the level  
of the input AC signal (see Fig.8). A filter with a nominal  
time constant of 1 µs prevents noise spikes from triggering  
the level detector.  
V
)
ref  
V
−0.16  
V
−0.48  
V
−0.8  
V
−1.12  
CC  
CC  
CC  
CC  
V
(V)  
RSSI  
(1) PRBS pattern input signal with a frequency <1 GHz.  
(2) Linearity error typically 0.5 dB.  
(3) ϕ = 1  
/
12.5 dB/mV.  
The LOS comparator has an internal 3 dB hysteresis and  
drives an open-drain circuit with a 5 kΩ internal resistor  
allowing it to directly interface positive or negative logic  
circuits (see Fig.9).  
Fig.8 Loss of signal assert level.  
Its response is independent of the input signal polarity due  
to the circuit design and to the demodulating action of the  
detector which transforms the alternating input voltage to  
a rectified and filtered quasi DC output signal. The  
logarithmic voltage slope of the TZA3014 is  
ϕ = 1/12.5 dB/mV and mostly is independent of temperature  
and supply voltage due to four feedback loops in the  
reference circuit. The LOS detector output voltage is  
derived from Vref.  
Example: a 200 mV (p-p) single-ended 1.2 GB/s PRBS  
input signal will have a VRSSI voltage of VCC − 1.013 V.  
If the offset voltage of the first stage increases above a  
certain level, the high DC gain of the amplifier circuit will  
cause successive stages to limit prematurely. This is  
prevented by the LOS detector offset control loop which  
extends the lower end of the amplifier’s dynamic range.  
The offset is automatically and continuously compensated  
by a feedback path from the last stage. An offset at the  
output of the logarithmic converter is equivalent to a  
change of amplitude at the input.  
The sensitivity of the LOS detector is affected by the RMS  
value of the input signal which, in its turn, depends on the  
frequency.  
VLOSTH can be calculated using the following formula:  
Using DC-coupling, with signal absence, and VIN not equal  
to VINQ (mute), the LOS detector detects full signal. Only  
very small signals with an average value equal to zero, can  
result into a zero output.  
V
LOSTH = VRSSI  
=
Vi(p-p)  
V
CC + 0.458 – SRSSI × 20 log  
(1)  
-------------------  
26E – 8  
where SRSSI in [mV/dB]; VLOSTH, VRSSI and Vi(p-p) in [V].  
2001 Jun 25  
11  
Philips Semiconductors  
Product specification  
2.5 Gbits/s postamplifier with level detector  
TZA3014  
V
V
handbook, halfpage  
handbook, halfpage  
GND  
CC  
CC  
56 kΩ  
5.6 kΩ  
TZA3014  
TZA3014  
LOS  
LOS  
5 kΩ  
5 kΩ  
GNDA  
GNDA  
I
I
LOS  
GND  
LOS  
V
EE  
MGU132  
MGU131  
a. Positive supply and positive logic.  
b. Negative supply and positive logic.  
GND  
handbook, halfpage  
56 kΩ  
TZA3014  
LOS  
5 kΩ  
GNDA  
I
LOS  
V
EE  
MGU130  
VCC − VEE < 7 V.  
c. Negative supply and negative logic.  
Fig.9 Loss of signal output pin LOS.  
Supply current  
For the supply current ICCB, see Fig.10.  
(1)  
60  
I
CCB  
(mA)  
Using a positive supply voltage  
50  
Although the TZA3014 has been designed to use a single  
+3.3 V supply voltage (see Fig.11), some care should be  
taken with respect to RF transmission lines. The on-chip  
signals refer to the various VCC pins. The external  
transmission lines will most likely be referred to the  
pins GNDA and GNDB, being the system ground.  
40  
30  
20  
17  
The RF signals will change from one reference plane to  
another when interfacing the RF inputs and outputs.  
A positive supply application is very vulnerable to  
interference with respect to this point. For a successful  
+3.3 V application, special care should be taken when  
designing the PCB layout in order to reduce the influence  
of interference and to keep the positive supply voltage as  
clean as possible.  
10  
5
0
0
0.2  
0.5  
V
0.8  
(V)  
1
o(se)(p-p)  
MGU133  
(1) Tamb = 25 °C.  
Fig.10 Supply current as a function of the output  
voltage.  
2001 Jun 25  
12  
Philips Semiconductors  
Product specification  
2.5 Gbits/s postamplifier with level detector  
TZA3014  
LIMITING VALUES  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
SYMBOL  
VCC  
Vn  
PARAMETER  
MIN.  
−0.5  
MAX.  
+5.5  
UNIT  
supply voltage  
DC voltage  
V
pins IN, INQ, LOSTH, LEVEL, Vref, TEST, OUTQ, OUT, GNDp,  
VCCA and VCCB  
−0.5  
−0.5  
VCC + 0.5  
+7  
V
V
pins LOS, INV and MUTE  
DC current  
In  
pins IN and INQ  
−20  
0
+20  
14  
mA  
µA  
mA  
mA  
µA  
W
pins LOSTH and LEVEL  
pins Vref, TEST and LOS  
pins OUT and OUTQ  
pins INV and MUTE  
total power dissipation  
storage temperature  
junction temperature  
ambient temperature  
−1  
−30  
0
+1  
+30  
20  
Ptot  
Tstg  
Tj  
−
0.6  
−65  
−
+150  
150  
+85  
°C  
°C  
Tamb  
−40  
°C  
THERMAL CHARACTERISTICS  
SYMBOL  
PARAMETER  
CONDITIONS  
VALUE  
UNIT  
Rth(j-s)  
thermal resistance from junction to  
solder point (exposed die pad)  
note 1  
15  
K/W  
K/W  
K/W  
Rth(j-a)  
thermal resistance from junction to  
ambient  
1s2p multi-layer test board; notes 1  
and 2  
33  
18  
Rth(s-a)  
thermal resistance from solder point to 1s2p multi-layer test board; notes 1  
ambient (exposed die pad)  
and 2  
Rth(s-a)(req)  
required thermal resistance from  
solder point to ambient  
LOS detector switched on  
Vo = 200 mV (p-p) single-ended  
Vo = 800 mV (p-p) single-ended  
130  
75  
K/W  
K/W  
Notes  
1. JEDEC standard.  
2. HTQFP32 and HBCC32 packages.  
2001 Jun 25  
13  
Philips Semiconductors  
Product specification  
2.5 Gbits/s postamplifier with level detector  
TZA3014  
CHARACTERISTICS  
Typical values at Tamb = 25 °C and VCC = 3.3 V; minimum and maximum values are valid over the entire ambient  
temperature range and supply voltage range; all voltages referenced to ground; note 1; unless otherwise specified.  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
Supply (pins VCCA and VCCB  
)
VCC  
ICCA  
supply voltage  
3.13  
LOS detector power-down 14  
3.3  
24  
40  
6
3.47  
V
supply current A  
34  
56  
10  
24  
mA  
mA  
mA  
mA  
LOS detector switched on  
amplifier power-down  
24  
2
ICCB  
Ptot  
TC  
supply current B  
Vo = 200 mV (p-p)  
single-ended  
11  
17  
Vo = 800 mV (p-p)  
single-ended  
43  
60  
77  
mA  
total power dissipation  
temperature coefficient  
power-down  
60  
100  
190  
240  
270  
mW  
mW  
Vo = 200 mV (p-p)  
single-ended  
120  
250  
Vo = 800 mV (p-p)  
single-ended  
330  
−50  
−30  
450  
−30  
−15  
mW  
LOS detector switched on; −80  
ICCA  
µA/K  
µA/K  
Vo = 800 mV (p-p)  
single-ended; ICCB  
−50  
Tj  
junction temperature  
ambient temperature  
−40  
−40  
−
+125  
+85  
°C  
°C  
Tamb  
+25  
RF inputs in general (PECL or CML input pins IN and INQ)  
VI(bias)  
VI  
DC input bias voltage  
V
CC − 0.4  
CC − 1.0  
V
CC − 0.33 VCC − 0.28 V  
DC and AC input window  
voltage  
note 2  
V
−
VCC + 0.3  
V
Ri  
Ci  
input resistance  
single-ended  
35  
50  
70  
Ω
input capacitance  
single-ended; note 2  
0.6  
0.8  
1.2  
pF  
Cross-over switch and postamplifier  
PECL OR CML INPUT PINS IN AND INQ  
Vi(p-p)  
input voltage swing  
(peak-to-peak value)  
single-ended; notes 2  
and 3  
50  
3.8  
6
−
500  
13.5  
22  
mV  
dB  
αOS(red)  
input offset reduction  
Vo = 200 mV (p-p)  
single-ended; note 4  
9
Vo = 800 mV (p-p)  
single-ended; note 4  
14  
−
dB  
Vio(cor)  
input offset voltage  
correction range  
single-ended  
−10  
+10  
mV  
(peak-to-peak value)  
Vn(i)(eq)(rms) equivalent input noise  
voltage (RMS value)  
Vo = 800 mV (p-p)  
single-ended; note 2  
−
−
75  
5
170  
12  
µV  
Fn  
noise factor  
note 2  
dB  
2001 Jun 25  
14  
Philips Semiconductors  
Product specification  
2.5 Gbits/s postamplifier with level detector  
TZA3014  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
BUFFER AND AMPLIFIER  
Gv  
small signal voltage gain  
Vo = 200 mV (p-p)  
single-ended; note 5  
9
15  
29  
20  
34  
dB  
Vo = 800 mV (p-p)  
21  
dB  
single-ended; note 5  
fD  
signal path data rate  
notes 6 and 7  
note 2  
−
2.5  
5
−
Gbits/s  
kHz  
f−3dB(l)  
low −3 dB cut-off  
frequency DC  
compensation  
2
10  
f−3dB(h)  
high −3 dB cut-off  
−
2.0  
−
GHz  
frequency  
tPD  
propagation delay  
note 2  
150  
200  
0
250  
5
ps  
ps  
∆tPD  
propagation delay  
difference  
at the same signal levels;  
note 2  
−
J
total jitter  
20 bits of the 28.5 kbits  
pattern; notes 2 and 8  
−
−
8
−
−
ps  
αct  
crosstalk  
note 9  
110  
dB  
PECL OR CML OUTPUTS (PINS OUT AND OUTQ)  
Vo(se)(p-p)  
single-ended output  
voltage  
50 Ω load  
200  
−
800  
mV  
(peak-to-peak value)  
TCVo  
temperature coefficient  
output voltage  
−1  
0
+1  
mV/K  
tr  
rise time  
20% to 80%; notes 6 and 8  
80% to 20%; notes 6 and 8  
single-ended  
−
80  
−
ps  
ps  
Ω
tf  
fall time  
−
80  
−
Ro  
Co  
output resistance  
output capacitance  
70  
0.6  
100  
0.8  
130  
1.2  
single-ended; note 2  
pF  
LEVEL CONTROL INPUT (PIN LEVEL)  
Vi  
Ri  
input voltage  
V
CC − Vref  
−
VCC  
600  
V
input resistance  
referenced to VCC  
200  
350  
kΩ  
SWITCH CIRCUIT  
ta  
td  
assert time  
de-assert time  
multiplexer and inverter  
multiplexer and inverter  
−
−
100  
80  
−
−
ns  
ns  
TTL INPUT PINS MUTE AND INV  
VIL  
VIH  
Ri  
LOW-level input voltage  
HIGH-level input voltage  
input resistance  
positive logic; note 10  
positive logic; note 10  
referenced to GNDA  
−0.3  
2
−
+0.8  
V
−
VCC + 0.8  
400  
V
100  
−40  
180  
−
kΩ  
µA  
Ii  
input current  
+40  
2001 Jun 25  
15  
Philips Semiconductors  
Product specification  
2.5 Gbits/s postamplifier with level detector  
TZA3014  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
RSSI and LOS detector  
PECL OR CML INPUT PINS IN AND INQ  
Vi(p-p)  
input voltage swing  
(peak-to-peak value)  
single-ended  
0.4  
−
400  
mV  
αOS(red)  
input offset reduction  
notes 2 and 4  
25  
40  
50  
+5  
dB  
Vio(cor)  
on-chip DC-offset  
compensation correction  
range  
peak-to-peak value;  
single-ended  
−5  
−
mV  
RSSI CIRCUIT  
f−3dB(l)  
low −3 dB cut-off  
0.5  
1.5  
1
2
MHz  
GHz  
frequency  
f−3dB(h)  
high −3 dB cut-off  
note 11  
2
2.5  
frequency  
DR  
dynamic range  
RSSI sensitivity  
57  
10  
60  
63  
dB  
SRSSI  
50 MHz, square; note 11  
12.5  
12  
15  
mV/dB  
mV/dB  
mV/dB  
mV/dB  
620 MHz, square; note 11 10  
14  
1.2 GHz, square; note 11  
100 MB/s PRBS (231 − 1);  
9
9
11  
13.5  
15  
12.5  
note 11  
1.2 GB/s PRBS (231 − 1);  
note 11  
2.4 GB/s PRBS (231 − 1);  
note 11  
10  
10  
−2  
−
12  
12  
0
14.5  
14  
+2  
1
mV/dB  
mV/dB  
µV/dBK  
dB  
TCsens  
LE  
temperature coefficient  
sensitivity  
linearity error  
see Fig.8; note 2  
0.5  
LOS DETECTOR  
hysLOS  
LOS hysteresis  
input signal waveform  
dependent  
2.0  
3.0  
4.0  
dB  
ta  
td  
assert time  
note 2  
note 2  
−
−
−
−
5
5
µs  
µs  
de-assert time  
INPUT PIN LOSTH  
Vi  
Ri  
input voltage  
input resistance  
0
−
VCC  
600  
V
referenced to GNDA  
150  
350  
kΩ  
OUTPUT PIN LOS  
Io(sink)  
Ro  
output sink current  
output resistance  
−
−
1
mA  
internal output series  
resistance  
3.5  
5
6.5  
kΩ  
2001 Jun 25  
16  
Philips Semiconductors  
Product specification  
2.5 Gbits/s postamplifier with level detector  
TZA3014  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
OUTPUT PIN RSSI  
Vo  
Io  
output voltage  
output current  
V
CC − 1.2  
−
−
VCC  
+1  
V
−1  
mA  
Band gap reference circuit  
OUTPUT PIN Vref  
Vref  
reference voltage  
VCC − 1.85 VCC − 1.6  
VCC − 1.45 V  
Cext  
allowed external  
capacitance  
−
−
10  
pF  
Io(sink)  
output sink current  
−
−
500  
µA  
Notes  
1. It is assumed that both CML inputs carry a complementary signal with the specified peak-to-peak value (true  
differential excitation).  
2. Guaranteed by design.  
3. Minimum signal with limiting output.  
GAC  
4. αOS(red)  
=
-----------  
GDC  
V o  
5. GV =  
------  
V i  
6. Based on −3 dB cut-off frequency and rise/fall time.  
7. Low limit can go as low as DC if the input signal overrides the input offset voltage correction range.  
8. Vi = 100 mV (p-p) single-ended, Vo = 800 mV (p-p) single-ended.  
9. Crosstalk of IC only.  
10. When using a negative supply voltage, positive or negative logic can be used. The values will be different, see Fig.7.  
11. Sensitivity depends on the waveform and is therefore a function of −3 dB cut-off frequency;  
see Section “RSSI and LOS detection”, Equation (1).  
2001 Jun 25  
17  
Philips Semiconductors  
Product specification  
2.5 Gbits/s postamplifier with level detector  
TZA3014  
APPLICATION INFORMATION  
To minimize low frequency switching noise in the vicinity of  
the TZA3014, the power supply line should be filtered once  
using a beaded capacitor circuit having a low cut-off  
frequency.  
RF input and output connections  
Striplines, or microstrips, with an odd mode characteristic  
impedance of Zo = 50 Ω have to be used for the differential  
RF connections on the PCB. This applies to both signal  
inputs and signal outputs. Each pair of lines should have  
the same length.  
The exposed die pad GNDp connection on the PCB must  
be a large area of copper to aid the transfer of heat from  
the IC to the PCB (see Figs 11 and 12).  
Grounding and power supply decoupling  
The PCB ground connection has to be a large area of  
copper connected to a common ground plane with an  
inductance as low as possible.  
2001 Jun 25  
18  
Philips Semiconductors  
Product specification  
2.5 Gbits/s postamplifier with level detector  
TZA3014  
2
Boundary of 100 mm area  
0
1
2
3
4
5 mm  
To central  
GND decoupling  
To central  
GND decoupling  
0603  
0603  
V
V
CCA  
CCB  
OUT  
IN  
INQ  
OUTQ  
V
V
CCA  
CCB  
0603  
0603  
0603  
0603  
0603  
0603  
0603  
HTQFP  
cross-section  
MGU134  
In order to enable heat flow out of the package, the following measures have to be taken:  
(1) Solder the 3 × 3 mm2 exposed die pad to a plane with maximum size.  
(2) Add a plane with minimum 100 mm2 in an inner layer, surrounded by ground layers.  
(3) Use maximum amount of vias to connect two planes.  
(4) Use minimum of openings in heat transport area between hot plane and ground planes.  
Fig.11 PCB layout for HTQFP package with positive supply voltage.  
2001 Jun 25  
19  
Philips Semiconductors  
Product specification  
2.5 Gbits/s postamplifier with level detector  
TZA3014  
2
Boundary of 100 mm area  
0
1
2
3
4
5 mm  
To central  
To central  
GND decoupling  
GND decoupling  
0603  
0603  
V
V
CCA  
CCB  
OUT  
IN  
INQ  
V
OUTQ  
V
CCA  
CCB  
0603  
0603  
0603  
0603  
0603  
0603  
0603  
HTQFP  
cross-section  
MGU136  
In order to enable heat flow out of the package, the following measures have to be taken:  
(1) Solder the 3 × 3 mm2 exposed die pad to a plane with maximum size.  
(2) Add a plane with minimum 100 mm2 in an inner layer, surrounded by ground layers.  
(3) Use maximum amount of vias to connect two planes.  
(4) Use minimum of openings in heat transport area between hot plane and ground planes.  
Fig.12 PCB layout for HTQFP package with negative supply voltage.  
2001 Jun 25  
20  
Philips Semiconductors  
Product specification  
2.5 Gbits/s postamplifier with level detector  
TZA3014  
BONDING PAD INFORMATION  
COORDINATES(1)  
SYMBOL  
PAD  
COORDINATES(1)  
x
y
SYMBOL  
VCCA  
PAD  
x
y
n.c.  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
+928  
+928  
+928  
+928  
+928  
+928  
+707  
+550  
+393  
+236  
+79  
−81  
1
2
−928  
−928  
−928  
−928  
−928  
−928  
−928  
−928  
−928  
−928  
−707  
−550  
−393  
−236  
−79  
+710  
+553  
+396  
+239  
+81  
n.c.  
+81  
IN  
VCCB  
OUTQ  
OUT  
VCCB  
GNDB  
n.c.  
+239  
+396  
+553  
+710  
+928  
+928  
+928  
+928  
+928  
+928  
+928  
+928  
+928  
+928  
INQ  
VCCA  
n.c.  
3
4
5
n.c.  
6
−81  
n.c.  
7
−239  
−396  
−553  
−710  
−928  
−928  
−928  
−928  
−928  
−928  
−928  
−928  
−928  
−928  
−710  
−553  
−396  
−239  
n.c.  
8
n.c.  
n.c.  
9
RSSI  
LOS  
n.c.  
n.c.  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
n.c.  
−79  
LOSTH  
n.c.  
INV  
−236  
−393  
−550  
−707  
n.c.  
n.c.  
MUTE  
GNDA  
LEVEL  
n.c.  
+79  
Note  
Vref  
+236  
+393  
+550  
+707  
+928  
+928  
+928  
+928  
1. All x and y coordinates represent the position of the  
centre of the pad in µm with respect to the centre of the  
die (see Fig.13).  
n.c.  
TEST  
n.c.  
n.c.  
n.c.  
n.c.  
n.c.  
2001 Jun 25  
21  
Philips Semiconductors  
Product specification  
2.5 Gbits/s postamplifier with level detector  
TZA3014  
40 39 38 37 36 35 34 33 32 31  
V
V
1
2
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
V
CCB  
CCA  
IN  
OUT  
INQ  
3
OUTQ  
V
4
CCA  
n.c.  
CCB  
5
n.c.  
n.c.  
n.c.  
n.c.  
n.c.  
n.c.  
x
0
6
n.c.  
n.c.  
n.c.  
n.c.  
n.c.  
0
y
7
8
TZA3014U  
9
10  
11 12 13 14 15 16 17 18 19 20  
MGU135  
Fig.13 Bonding pad locations TZA3014U.  
2001 Jun 25  
22  
Philips Semiconductors  
Product specification  
2.5 Gbits/s postamplifier with level detector  
TZA3014  
PACKAGE OUTLINES  
HTQFP32: plastic, heatsink thin quad flat package; 32 leads; body 5 x 5 x 1.0 mm  
SOT547-2  
c
y
heathsink side  
X
D
h
24  
17  
A
Z
25  
E
16  
e
H
E
E
E
(A )  
3
h
A
2
A
A
1
w M  
p
θ
b
L
p
pin 1 index  
L
9
32  
detail X  
1
8
w M  
Z
v
M
A
B
D
b
p
e
D
B
H
v
M
D
0
2.5  
scale  
5 mm  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
D
E
E
e
H
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
h
h
D
E
p
D
max.  
0.15 1.05  
0.05 0.95  
0.27 0.20 5.1  
0.17 0.09 4.9  
3.1  
2.7  
5.1  
4.9  
3.1  
2.7  
7.1  
6.9  
7.1  
6.9  
0.75  
0.45  
0.89 0.89  
0.61 0.61  
7°  
0°  
mm  
1.2  
0.25  
0.5  
1.0  
0.2 0.08 0.08  
Note  
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
EIAJ  
SOT547-2  
99-06-15  
2001 Jun 25  
23  
Philips Semiconductors  
Product specification  
2.5 Gbits/s postamplifier with level detector  
TZA3014  
HBCC32: plastic, heatsink bottom chip carrier; 32 terminals; body 5 x 5 x 0.65 mm  
SOT560-1  
D
x
B
b
w M  
1
w M  
ball A1  
index area  
b
b
3
E
w M  
b
w M  
2
detail X  
x
C
A
B
C
e
1
e
y
v
A
E
e
4
e
2
1
1
32  
A
X
D
1
1
A
2
e
3
A
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
A
A
b
E
e
e
1
w
b
b
b
D
D
E
e
e
3
e
4
v
x
y
UNIT  
1
2
1
1
2
3
1
2
max.  
0.10 0.70 0.35 0.50 0.50 0.50 5.1  
0.05 0.60 0.20 0.30 0.35 0.35 4.9  
3.2 5.1  
3.0 4.9  
3.2  
3.0  
mm 0.80  
0.15 0.15 0.05  
0.5  
4.2  
4.2  
4.15 4.15  
0.2  
REFERENCES  
OUTLINE  
VERSION  
EUROPEAN  
PROJECTION  
ISSUE DATE  
IEC  
JEDEC  
EIAJ  
99-09-10  
00-02-01  
SOT560-1  
MO-217  
2001 Jun 25  
24  
Philips Semiconductors  
Product specification  
2.5 Gbits/s postamplifier with level detector  
TZA3014  
SOLDERING  
If wave soldering is used the following conditions must be  
observed for optimal results:  
Introduction to soldering surface mount packages  
• Use a double-wave soldering method comprising a  
turbulent wave with high upward pressure followed by a  
smooth laminar wave.  
This text gives a very brief insight to a complex technology.  
A more in-depth account of soldering ICs can be found in  
our “Data Handbook IC26; Integrated Circuit Packages”  
(document order number 9398 652 90011).  
• For packages with leads on two sides and a pitch (e):  
– larger than or equal to 1.27 mm, the footprint  
longitudinal axis is preferred to be parallel to the  
transport direction of the printed-circuit board;  
There is no soldering method that is ideal for all surface  
mount IC packages. Wave soldering can still be used for  
certain surface mount ICs, but it is not suitable for fine pitch  
SMDs. In these situations reflow soldering is  
recommended.  
– smaller than 1.27 mm, the footprint longitudinal axis  
must be parallel to the transport direction of the  
printed-circuit board.  
Reflow soldering  
The footprint must incorporate solder thieves at the  
downstream end.  
Reflow soldering requires solder paste (a suspension of  
fine solder particles, flux and binding agent) to be applied  
to the printed-circuit board by screen printing, stencilling or  
pressure-syringe dispensing before package placement.  
• For packages with leads on four sides, the footprint must  
be placed at a 45° angle to the transport direction of the  
printed-circuit board. The footprint must incorporate  
solder thieves downstream and at the side corners.  
Several methods exist for reflowing; for example,  
convection or convection/infrared heating in a conveyor  
type oven. Throughput times (preheating, soldering and  
cooling) vary between 100 and 200 seconds depending  
on heating method.  
During placement and before soldering, the package must  
be fixed with a droplet of adhesive. The adhesive can be  
applied by screen printing, pin transfer or syringe  
dispensing. The package can be soldered after the  
adhesive is cured.  
Typical reflow peak temperatures range from  
215 to 250 °C. The top-surface temperature of the  
packages should preferable be kept below 220 °C for  
thick/large packages, and below 235 °C for small/thin  
packages.  
Typical dwell time is 4 seconds at 250 °C.  
A mildly-activated flux will eliminate the need for removal  
of corrosive residues in most applications.  
Manual soldering  
Wave soldering  
Fix the component by first soldering two  
diagonally-opposite end leads. Use a low voltage (24 V or  
less) soldering iron applied to the flat part of the lead.  
Contact time must be limited to 10 seconds at up to  
300 °C.  
Conventional single wave soldering is not recommended  
for surface mount devices (SMDs) or printed-circuit boards  
with a high component density, as solder bridging and  
non-wetting can present major problems.  
When using a dedicated tool, all other leads can be  
soldered in one operation within 2 to 5 seconds between  
270 and 320 °C.  
To overcome these problems the double-wave soldering  
method was specifically developed.  
2001 Jun 25  
25  
Philips Semiconductors  
Product specification  
2.5 Gbits/s postamplifier with level detector  
TZA3014  
Suitability of surface mount IC packages for wave and reflow soldering methods  
SOLDERING METHOD  
PACKAGE  
WAVE  
not suitable  
REFLOW(1)  
BGA, HBGA, LFBGA, SQFP, TFBGA  
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS  
PLCC(3), SO, SOJ  
suitable  
not suitable(2)  
suitable  
suitable  
suitable  
LQFP, QFP, TQFP  
not recommended(3)(4) suitable  
not recommended(5)  
suitable  
SSOP, TSSOP, VSO  
Notes  
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum  
temperature (with respect to time) and body size of the package, there is a risk that internal or external package  
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the  
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.  
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink  
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).  
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.  
The package footprint must incorporate solder thieves downstream and at the side corners.  
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;  
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.  
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is  
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.  
DATA SHEET STATUS  
PRODUCT  
DATA SHEET STATUS(1)  
DEFINITIONS  
STATUS(2)  
Objective data  
Development This data sheet contains data from the objective specification for product  
development. Philips Semiconductors reserves the right to change the  
specification in any manner without notice.  
Preliminary data  
Product data  
Qualification  
This data sheet contains data from the preliminary specification.  
Supplementary data will be published at a later date. Philips  
Semiconductors reserves the right to change the specification without  
notice, in order to improve the design and supply the best possible  
product.  
Production  
This data sheet contains data from the product specification. Philips  
Semiconductors reserves the right to make changes at any time in order  
to improve the design, manufacturing and supply. Changes will be  
communicated according to the Customer Product/Process Change  
Notification (CPCN) procedure SNW-SQ-650A.  
Notes  
1. Please consult the most recently issued data sheet before initiating or completing a design.  
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was  
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.  
2001 Jun 25  
26  
Philips Semiconductors  
Product specification  
2.5 Gbits/s postamplifier with level detector  
TZA3014  
DEFINITIONS  
Right to make changes  
Philips Semiconductors  
reserves the right to make changes, without notice, in the  
products, including circuits, standard cells, and/or  
software, described or contained herein in order to  
improve design and/or performance. Philips  
Semiconductors assumes no responsibility or liability for  
the use of any of these products, conveys no licence or title  
under any patent, copyright, or mask work right to these  
products, and makes no representations or warranties that  
these products are free from patent, copyright, or mask  
work right infringement, unless otherwise specified.  
Short-form specification  
The data in a short-form  
specification is extracted from a full data sheet with the  
same type number and title. For detailed information see  
the relevant data sheet or data handbook.  
Limiting values definition Limiting values given are in  
accordance with the Absolute Maximum Rating System  
(IEC 60134). Stress above one or more of the limiting  
values may cause permanent damage to the device.  
These are stress ratings only and operation of the device  
at these or at any other conditions above those given in the  
Characteristics sections of the specification is not implied.  
Exposure to limiting values for extended periods may  
affect device reliability.  
Bare die  
All die are tested and are guaranteed to  
comply with all data sheet limits up to the point of wafer  
sawing for a period of ninety (90) days from the date of  
Philips' delivery. If there are data sheet limits not  
guaranteed, these will be separately indicated in the data  
sheet. There are no post packing tests performed on  
individual die or wafer. Philips Semiconductors has no  
control of third party procedures in the sawing, handling,  
packing or assembly of the die. Accordingly, Philips  
Semiconductors assumes no liability for device  
Application information  
Applications that are  
described herein for any of these products are for  
illustrative purposes only. Philips Semiconductors make  
no representation or warranty that such applications will be  
suitable for the specified use without further testing or  
modification.  
functionality or performance of the die or systems after  
third party sawing, handling, packing or assembly of the  
die. It is the responsibility of the customer to test and  
qualify their application in which the die is used.  
DISCLAIMERS  
Life support applications  
These products are not  
designed for use in life support appliances, devices, or  
systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips  
Semiconductors customers using or selling these products  
for use in such applications do so at their own risk and  
agree to fully indemnify Philips Semiconductors for any  
damages resulting from such application.  
2001 Jun 25  
27  
Philips Semiconductors – a worldwide company  
Argentina: see South America  
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,  
Tel. +31 40 27 82785, Fax. +31 40 27 88399  
Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,  
Tel. +61 2 9704 8141, Fax. +61 2 9704 8139  
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,  
Tel. +64 9 849 4160, Fax. +64 9 849 7811  
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,  
Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210  
Norway: Box 1, Manglerud 0612, OSLO,  
Tel. +47 22 74 8000, Fax. +47 22 74 8341  
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,  
220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773  
Pakistan: see Singapore  
Belgium: see The Netherlands  
Brazil: see South America  
Philippines: Philips Semiconductors Philippines Inc.,  
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,  
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474  
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,  
51 James Bourchier Blvd., 1407 SOFIA,  
Tel. +359 2 68 9211, Fax. +359 2 68 9102  
Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,  
Tel. +48 22 5710 000, Fax. +48 22 5710 001  
Portugal: see Spain  
Romania: see Italy  
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,  
Tel. +1 800 234 7381, Fax. +1 800 943 0087  
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,  
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,  
Tel. +852 2319 7888, Fax. +852 2319 7700  
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,  
Tel. +7 095 755 6918, Fax. +7 095 755 6919  
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,  
Colombia: see South America  
Czech Republic: see Austria  
Tel. +65 350 2538, Fax. +65 251 6500  
Slovakia: see Austria  
Slovenia: see Italy  
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,  
Tel. +45 33 29 3333, Fax. +45 33 29 3905  
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,  
2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,  
Tel. +27 11 471 5401, Fax. +27 11 471 5398  
Finland: Sinikalliontie 3, FIN-02630 ESPOO,  
Tel. +358 9 615 800, Fax. +358 9 6158 0920  
France: 7 - 9 Rue du Mont Valérien, BP317, 92156 SURESNES Cedex,  
Tel. +33 1 4728 6600, Fax. +33 1 4728 6638  
South America: Al. Vicente Pinzon, 173, 6th floor,  
04547-130 SÃO PAULO, SP, Brazil,  
Tel. +55 11 821 2333, Fax. +55 11 821 2382  
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,  
Tel. +49 40 2353 60, Fax. +49 40 2353 6300  
Spain: Balmes 22, 08007 BARCELONA,  
Tel. +34 93 301 6312, Fax. +34 93 301 4107  
Hungary: Philips Hungary Ltd., H-1119 Budapest, Fehervari ut 84/A,  
Tel: +36 1 382 1700, Fax: +36 1 382 1800  
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,  
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745  
India: Philips INDIA Ltd, Band Box Building, 2nd floor,  
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,  
Tel. +91 22 493 8541, Fax. +91 22 493 0966  
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,  
Tel. +41 1 488 2741 Fax. +41 1 488 3263  
Indonesia: PT Philips Development Corporation, Semiconductors Division,  
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,  
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080  
Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1,  
TAIPEI, Taiwan Tel. +886 2 2134 2451, Fax. +886 2 2134 2874  
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,  
60/14 MOO 11, Bangna Trad Road KM. 3, Bagna, BANGKOK 10260,  
Tel. +66 2 361 7910, Fax. +66 2 398 3447  
Ireland: Newstead, Clonskeagh, DUBLIN 14,  
Tel. +353 1 7640 000, Fax. +353 1 7640 200  
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,  
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,  
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007  
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813  
Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),  
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,  
Tel. +39 039 203 6838, Fax +39 039 203 6800  
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461  
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,  
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,  
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057  
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421  
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,  
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,  
Tel. +82 2 709 1412, Fax. +82 2 709 1415  
Tel. +1 800 234 7381, Fax. +1 800 943 0087  
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,  
Tel. +60 3 750 5214, Fax. +60 3 757 4880  
Uruguay: see South America  
Vietnam: see Singapore  
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,  
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087  
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,  
Tel. +381 11 3341 299, Fax.+381 11 3342 553  
Middle East: see Italy  
For all other countries apply to: Philips Semiconductors,  
Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN,  
The Netherlands, Fax. +31 40 27 24825  
Internet: http://www.semiconductors.philips.com  
72  
SCA  
© Philips Electronics N.V. 2001  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.  
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed  
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license  
under patent- or other industrial or intellectual property rights.  
Printed in The Netherlands  
403510/200/02/pp28  
Date of release: 2001 Jun 25  
Document order number: 9397 750 08203  
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