TN12, TS12 and TYNx12 Series
Figure 3: Average and D.C. on-state current
versus ambient temperature (device mounted
on FR4 with recommended pad layout) (DPAK)
Figure 4: Relative variation of thermal
impedance junction to case versus pulse
duration
I
(A)
T(AV)
K=[Z
/R
]
th(j-c) th(j-c)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.0
0.5
D.C.
D2PAK
α = 180°
DPAK
0.2
0.1
t (s)
p
T
amb
(°C)
1E-3
1E-2
1E-1
1E+0
0
25
50
75
100
125
Figure 5: Relative variation of thermal
impedance junction to ambient versus pulse
duration (recommended pad layout, FR4 PC
board for DPAK)
Figure 6: Relative variation of gate trigger
current and holding current versus junction
temperature for TS8 series
K=[Z
/R
]
th(j-a) th(j-a)
I
,I ,I [T ] / I ,I ,I [T =25°C]
GT H L j GT H L j
1.00
0.10
0.01
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
IGT
DPAK
D2PAK
TO-220AB / IPAK
IH & IL
RGK = 1kΩ
T (°C)
j
t (s)
p
-40
-20
0
20
40
60
80
100
120
140
1E-2
1E-1
1E+0
1E+1
1E+2
5E+2
Figure 7: Relative variation of gate trigger
current and holding current versus junction
temperature for TN8 & TYN08 series
Figure 8: Relative variation of holding current
versus gate-cathode resistance (typical
values) for TS8 series
I [R ] / I [R =1kΩ]
H
GK
H
GK
I
,I ,I [T ] / I ,I ,I [T =25°C]
GT
H
L
j
GT
H
L
j
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Tj = 25°C
IGT
IH & IL
T (°C)
j
R (kΩ)
GK
-40
-20
0
20
40
60
80
100
120
140
1E-2
1E-1
1E+0
1E+1
4/11
