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EZ801905050MOD

型号：

EZ801905050MOD

描述：

eZ80190模块是一个紧凑的，高性能的以太网模块[ eZ80190 Module is a compact, high-performance Ethernet module ]

品牌：

ZILOG[ ZILOG, INC. ]

页数：

36 页

PDF大小：

429 K

下载PDF手册
eZ801905050MOD  
eZ80190 Module  
Product Specification  
PS019101-1003  
PRELIMINARY  
ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126  
Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com  
This publication is subject to replacement by a later edition. To determine whether  
a later edition exists, or to request copies of publications, contact:  
ZiLOG Worldwide Headquarters  
532 Race Street  
San Jose, CA 95126  
Telephone: 408.558.8500  
Fax: 408.558.8300  
www.ZiLOG.com  
ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other  
products and/or service names mentioned herein may be trademarks of the companies with which  
they are associated.  
Document Disclaimer  
©2003 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices,  
applications, or technology described is intended to suggest possible uses and may be superseded.  
ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF  
ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS  
DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY  
INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR  
TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval  
ZiLOG, use of information, devices, or technology as critical components of life support systems is  
not authorized. No licenses or other rights are conveyed, implicitly or otherwise, by this document  
under any intellectual property rights.  
PS019101-1003  
P R E L I M I N A R Y  
eZ801905050MOD  
eZ80190 Module Product Specification  
iii  
Table of Contents  
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv  
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v  
The eZ80190 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
eZ80190 Processor Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
I/O Connector (JP2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Peripheral Bus Connector (JP1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Onboard Component Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Logic-Level I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Onboard Battery Backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Ethernet Media Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Ethernet LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Ethernet Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
GPIO Pins for Enabling LAN Activity, Sleep, Interrupt . . . . . . . . . . . . . 13  
EMAC Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
EMAC Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Static RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Reset Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Serial Interface Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
ESD/EMI Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Document Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Change Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Customer Feedback Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
PS019101-1003  
P R E L I M I N A R Y  
Table of Contents  
eZ801905050MOD  
eZ80190 Module Product Specification  
iv  
List of Figures  
Figure 1. eZ80190 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Figure 2. eZ80190 Module Peripheral Bus Connector Pin Configuration—JP1 4  
Figure 3. eZ80190 Module I/O Connector Pin Configuration—JP2 . . . . . . . . . 8  
Figure 4. Physical Dimensions of the eZ80190 Module . . . . . . . . . . . . . . . . . 17  
Figure 5. eZ80190 Module—Top Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Figure 6. eZ80190 Module—Bottom Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Figure 7. Power Supply Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Figure 8. eZ80190 Module Schematic Diagram, #1 of 9—CPU . . . . . . . . . . . 23  
Figure 9. eZ80190 Module Schematic Diagram, #2 of 9—36-Pin SRAM  
Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
Figure 10. eZ80190 Module Schematic Diagram, #3 of 9—NOR Flash Device 25  
Figure 11. eZ80190 Module Schematic Diagram, #4 of 9—Ethernet Module . 26  
Figure 12. eZ80190 Module Schematic Diagram, #5 of 9—Ethernet Module  
Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Figure 13. eZ80190 Module Schematic Diagram, #6 of 9—Ethernet Module  
Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
Figure 14. eZ80190 Module Schematic Diagram, #7 of 9—Headers . . . . . . . . 29  
Figure 15. eZ80190 Module Schematic Diagram, #8 of 9—Power Supply . . . 30  
PS019101-1003  
P R E L I M I N A R Y  
List of Figures  
eZ801905050MOD  
eZ80190 Module Product Specification  
v
List of Tables  
Table 1. eZ80190 Module Peripheral Bus Connector Pin Identification. . . . . . . . 5  
Table 2. eZ80190 Module I/O Connector Pin Identification . . . . . . . . . . . . . . . . . 8  
Table 3. Ethernet Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Table 4. Chip Frequency to Wait State Cycle Time Calculation. . . . . . . . . . . . . 14  
Table 5. Real-Time Clock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Table 6. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
PS019101-1003  
P R E L I M I N A R Y  
List of Tables  
eZ801905050MOD  
eZ80190 Module Product Specification  
1
The eZ80190 Module  
The eZ80190 Module is a compact, high-performance Ethernet module specially  
designed for the rapid development and deployment of embedded systems  
requiring control and Internet/Intranet connectivity. It features the low-cost  
eZ80190 microprocessor powered by ZiLOG’s latest power-efficient, high-speed  
®
eZ80 CPU.  
The eZ80190 microprocessor is a high-speed single-cycle instruction-fetch micro-  
processor, which can operate with a clock speed of 50MHz. It can operate in Z80-  
compatible addressing mode (64KB) or full 24-bit addressing mode (16MB).  
The rich peripheral set of the eZ80190 makes it suitable for a variety of applica-  
tions, including industrial control, communication, security, automation, point-of-  
sale terminals, and embedded networking applications.  
Module Features  
•
eZ80190 microprocessor operating at 50MHz  
•
•
•
•
•
•
Ethernet Media Access Controller+ PHY with RJ45 connector  
512KB zero-wait-state onboard SRAM  
1MB onboard NOR Flash ROM (90–100ns)  
Real-Time Clock with 32.768kHz Crystal with battery backup  
I/O connector provides 32 general-purpose 5V-tolerant I/O pinouts  
Onboard peripheral bus connector provides I/O bus for external peripheral con-  
nections (IRQ, CS, 24 address, 8 data)  
•
•
•
Small footprint 78.7mm x 63.5mm; height is 24mm  
Module operates from external 3.3V power supply  
Standard operating temperature range: 0ºC to +70ºC  
eZ80190 Processor Features  
®
•
•
•
•
Single-cycle instruction fetch, high-performance, pipelined eZ80 CPU core  
Low power features including SLEEP mode and HALT mode  
Two UARTs with independent baud rate generators  
Two SPI interfaces with independent clock rate generators  
PS019101-1003  
P R E L I M I N A R Y  
The eZ80190 Module  
eZ801905050MOD  
eZ80190 Module Product Specification  
2
2
•
•
•
•
Two I C interfaces with independent clock rate generators  
Fast multiply accumulate unit (MACC)  
DMA Controller for fast memory-to-memory transfers  
Glueless external memory and I/O interface featuring 4 chip selects with individual  
wait state generators  
•
Fixed-priority vectored interrupts (both internal and external) and interrupt control-  
ler  
•
•
•
•
•
•
•
Six 16-bit Counter/Timers with prescalers and direct input/output drive  
Watch-Dog Timer  
32 bits of general-purpose I/O  
2-wire ZDI debug interface  
100-pin LQFP package  
3.3V 0.3V supply voltage with 5V tolerant inputs  
Standard operating temperature range: 0ºC to +70ºC  
Note:  
All signals with an overline are active Low. For example, B/W, for which  
WORD is active Low, and B/W, for which BYTE is active Low.  
PS019101-1003  
P R E L I M I N A R Y  
eZ80190 Processor Features  
eZ801905050MOD  
eZ80190 Module Product Specification  
3
Block Diagram  
Figure 1 illustrates a block diagram of the eZ80190 microprocessor.  
Power-On  
Reset  
50MHz  
Oscillator  
GPIO  
UART  
SPI  
PD  
eZ80 CPU  
I2C  
6 x 16-Bit  
Timer  
GPIO  
UART  
SPI  
PC  
PB  
ZDI  
ZDI  
I2C  
Watch-Dog  
Timer  
GPIO  
GPIO  
MACC  
DMA  
PA  
I2C  
Bus Controller  
8-Bit Data  
24-Bit Address  
Gold  
Cap  
RTC  
EMAC  
1 MB  
Flash/ROM  
LEDs  
RJ45  
32 kHz XTAL  
512 KB SRAM  
Figure 1. eZ80190 Functional Block Diagram  
PS019101-1003  
P R E L I M I N A R Y  
eZ80190 Processor Features  
eZ801905050MOD  
eZ80190 Module Product Specification  
4
Pin Description  
I/O Connector (JP2)  
Figure 2 illustrates the pin layout of the 60-pin Peripheral Bus Connector (JP1) of  
®
the eZ80190 Module. The eZ80 Development Platform, however, features a 50-  
pin connector. The eZ80190 Module is designed to interface pin 60 of its JP1 con-  
®
nector to pin 50 of the eZ80 Development Platform’s JP1 connector so that pins  
®
1–10 of the eZ80190 Module overlap the edge of the eZ80 Development Plat-  
form. Table 1 identifies the pins and their functions.  
Figure 2. eZ80190 Module  
Peripheral Bus Connector Pin Configuration—JP1  
PS019101-1003  
P R E L I M I N A R Y  
Pin Description  
eZ801905050MOD  
eZ80190 Module Product Specification  
5
Table 1. eZ80190 Module Peripheral Bus Connector Pin Identification*  
Pull  
Pin # Symbol  
Up/Down* Signal Direction Comments  
1
2
3
4
5
Reserved  
Reserved  
Reserved  
Reserved  
TRSTN  
Input  
Input  
Reset for On-Chip Instrumentation (OCI);  
not used with the eZ80190 Module.  
6
7
Reserved  
F91_WE  
PU 10KΩ  
A Low enables a Write to on-chip Flash  
memory. If this pin is unconnected, on-chip  
Flash memory is write-protected; not used  
with the eZ80190 Module.  
8
Reserved  
GND  
9
V
/Ground (0V).  
SS  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
V
3.3V supply input pin.  
CC  
A6  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
A0  
A10  
A3  
GND  
V
/Ground (0V).  
SS  
V
3.3V supply input pin.  
CC  
A8  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
A7  
A13  
A9  
A15  
A14  
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10pF to satisfy  
timing requirements for the CPU.  
All unused inputs should be pulled to either V  
consumption and to reduce noise sensitivity.  
or GND, depending on their inactive levels, to reduce power  
DD  
To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80190 Peripheral Power-Down  
Register.  
All inputs are CMOS level 3.3V (5V tolerant), except where otherwise noted.  
PS019101-1003  
P R E L I M I N A R Y  
I/O Connector (JP2)  
eZ801905050MOD  
eZ80190 Module Product Specification  
6
Table 1. eZ80190 Module Peripheral Bus Connector Pin Identification* (Continued)  
Pull  
Pin # Symbol  
Up/Down* Signal Direction Comments  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
A18  
Bidirectional  
Bidirectional  
Bidirectional  
A16  
A19  
GND  
A2  
V
/Ground (0V).  
SS  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
A1  
A11  
A12  
A4  
A20  
A5  
A17  
Reserved  
DIS_Flash  
PU 10KΩ  
Input  
A Low disables onboard Flash memory.  
Flash is enabled if DIS_Flash is not  
connected; CMOS Input 3.3V (5V tolerant).  
37  
38  
39  
40  
41  
42  
43  
44  
45  
A21  
Bidirectional  
V
3.3V supply input pin.  
CC  
A22  
A23  
CS0  
CS1  
CS2  
D0  
Bidirectional  
Bidirectional  
Output  
Output  
Output  
PU 4k7Ω  
PU 4k7Ω  
Bidirectional  
Bidirectional  
D1  
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10pF to satisfy  
timing requirements for the CPU.  
All unused inputs should be pulled to either V  
consumption and to reduce noise sensitivity.  
or GND, depending on their inactive levels, to reduce power  
DD  
To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80190 Peripheral Power-Down  
Register.  
All inputs are CMOS level 3.3V (5V tolerant), except where otherwise noted.  
PS019101-1003  
P R E L I M I N A R Y  
I/O Connector (JP2)  
eZ801905050MOD  
eZ80190 Module Product Specification  
7
Table 1. eZ80190 Module Peripheral Bus Connector Pin Identification* (Continued)  
Pull  
Pin # Symbol  
Up/Down* Signal Direction Comments  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
D2  
PU 4k7Ω  
PU 4k7Ω  
PU 4k7Ω  
PU 4k7Ω  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
D3  
D4  
D5  
GND  
D7  
V
V
/Ground (0V).  
/Ground (0V).  
SS  
PU 4k7Ω  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
D6  
MREQ  
IORQ  
GND  
RD  
SS  
Bidirectional  
Bidirectional  
Output  
WR  
INSTRD  
BUSACK  
BUSREQ  
Output  
PU 2k2Ω  
Input  
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10pF to satisfy  
timing requirements for the CPU.  
All unused inputs should be pulled to either V  
consumption and to reduce noise sensitivity.  
or GND, depending on their inactive levels, to reduce power  
DD  
To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80190 Peripheral Power-Down  
Register.  
All inputs are CMOS level 3.3V (5V tolerant), except where otherwise noted.  
Peripheral Bus Connector (JP1)  
Figure 3 illustrates the pin layout of the 60-pin I/O Connector (JP2) of the eZ80190  
®
Module. The eZ80 Development Platform, however, features a 50-pin connector.  
The eZ80190 Module is designed to interface pin 60 of its JP2 connector to pin 50  
®
of the eZ80 Development Platform’s JP2 connector so that pins 1–10 of the  
®
eZ80190 Module overlap the edge of the eZ80 Development Platform  
identifies the pins and their functions.  
. Table 2  
PS019101-1003  
P R E L I M I N A R Y  
Peripheral Bus Connector (JP1)  
eZ801905050MOD  
eZ80190 Module Product Specification  
8
Figure 3. eZ80190 Module  
I/O Connector Pin Configuration—JP2  
Table 2. eZ80190 Module I/O Connector Pin Identification*  
Pull  
Signal  
Pin # Symbol  
Up/Down Direction  
Comments  
1
2
3
PA7  
PA6  
PA5  
Bidirectional  
Bidirectional  
Bidirectional  
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10pF to satisfy  
timing requirements for the CPU.  
All unused inputs should be pulled to either V  
consumption and to reduce noise sensitivity.  
or GND, depending on their inactive levels, to reduce power  
DD  
To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80190 Peripheral Power-Down  
Register.  
All inputs are CMOS level 3.3V (5V tolerant), except where otherwise noted.  
PS019101-1003  
P R E L I M I N A R Y  
Peripheral Bus Connector (JP1)  
eZ801905050MOD  
eZ80190 Module Product Specification  
9
Table 2. eZ80190 Module I/O Connector Pin Identification* (Continued)  
Pull Signal  
Pin # Symbol  
Up/Down Direction  
Comments  
4
PA4  
PA3  
PA2  
PA1  
PA0  
Bidirectional  
5
Bidirectional  
6
Bidirectional  
7
Bidirectional  
8
Bidirectional  
9
V
3.3V supply input pin.  
V /Ground (0V).  
CC  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
GND  
PB7  
PB6  
PB5  
PB4  
PB3  
PB2  
PB1  
PB0  
GND  
PC7  
PC6  
PC5  
PC4  
PC3  
PC2  
PC1  
PC0  
SS  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
V
/Ground (0V).  
SS  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10pF to satisfy  
timing requirements for the CPU.  
All unused inputs should be pulled to either V  
consumption and to reduce noise sensitivity.  
or GND, depending on their inactive levels, to reduce power  
DD  
To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80190 Peripheral Power-Down  
Register.  
All inputs are CMOS level 3.3V (5V tolerant), except where otherwise noted.  
PS019101-1003  
P R E L I M I N A R Y  
Peripheral Bus Connector (JP1)  
eZ801905050MOD  
eZ80190 Module Product Specification  
10  
Table 2. eZ80190 Module I/O Connector Pin Identification* (Continued)  
Pull Signal  
Pin # Symbol  
Up/Down Direction  
Comments  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
PD7  
PD6  
GND  
PD5  
PD4  
PD3  
PD2  
PD1  
PD0  
TDO  
Bidirectional  
Bidirectional  
V
/Ground (0V).  
SS  
Bidirectional  
PD 4k7  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Output  
ZDI Data Output pin; not used with the eZ80190  
Module.  
38  
39  
40  
TDI  
Input  
ZDI Data Input pin.  
GND  
V
/Ground (0V).  
SS  
TRIGOUT  
Output  
Active High trigger event indicator; not used with the  
eZ80190 Module.  
41  
42  
TCK  
TMS  
PU 10KΩ Input  
PU 10KΩ Input  
ZDI Clock. High on reset enables ZDI mode; Low on  
reset enables OCI debug.  
JTAG Test Mode Select Input; not used with the  
eZ80190 Module.  
43  
44  
45  
46  
47  
48  
RTC_V  
RTC supply from GoldCap (or external battery).  
Synchronous CPU clock output.  
DD  
EZ80CLK  
Output  
2
2
I CSCL  
PU 4k7  
PU 4k7  
Bidirectional  
I C Bus Clock.  
GND  
V
/Ground (0V).  
SS  
2
2
I CSDA  
Bidirectional  
Power  
I C Data Clock.  
V /Ground (0V).  
SS  
GND  
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10pF to satisfy  
timing requirements for the CPU.  
All unused inputs should be pulled to either V  
consumption and to reduce noise sensitivity.  
or GND, depending on their inactive levels, to reduce power  
DD  
To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80190 Peripheral Power-Down  
Register.  
All inputs are CMOS level 3.3V (5V tolerant), except where otherwise noted.  
PS019101-1003  
P R E L I M I N A R Y  
Peripheral Bus Connector (JP1)  
eZ801905050MOD  
eZ80190 Module Product Specification  
11  
Table 2. eZ80190 Module I/O Connector Pin Identification* (Continued)  
Pull Signal  
Pin # Symbol  
Up/Down Direction  
Comments  
49  
FlashWE  
PU 10KΩ Input  
A Low enables a Write to external Flash memory  
boot block area. If this pin is unconnected, the Flash  
memory boot block area is write-protected.  
50  
51  
52  
GND  
V
/Ground (0V).  
SS  
CS3  
Output  
Connected to the CS8900 EMAC.  
DIS_IRDA  
PU 10KΩ Input  
A Low disables the onboard IRDA transceiver to use  
PC0/PC1 UART pins externally; not used with the  
eZ80190 Module.  
53  
54  
RESET  
WAIT  
PU 2k2  
PU 2k2  
Reset Output from module or push-button reset.  
Bidirectional  
Input  
Driving the WAIT pin Low forces the CPU to provide  
additional clock cycles for an external peripheral or  
external memory to complete its Read or Write oper-  
ation; not used with the eZ80190 Module.  
55  
56  
57  
V
3.3V supply input pin.  
CC  
GND  
V
/Ground (0V).  
SS  
HALT_SLP  
Output, Active A Low on this pin indicates that the CPU enters  
Low  
either HALT or SLEEP mode because of execution  
of either a HALT or SLP instruction.  
58  
NMI  
PU 10KΩ Schmitt Trig- The NMI input is a higher priority input than the  
ger Input,  
Active Low  
maskable interrupts. It is always recognized at the  
end of an instruction, regardless of the state of the  
interrupt enable control bits. This input includes a  
Schmitt trigger to allow RC rise times. This external  
NMI signal is combined with an internal NMI signal  
generated from the WDT block before being con-  
nected to the NMI input of the CPU.  
59  
60  
V
3.3V supply input pin.  
CC  
Reserved  
NC  
Reserved—No Connection.  
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10pF to satisfy  
timing requirements for the CPU.  
All unused inputs should be pulled to either V  
consumption and to reduce noise sensitivity.  
or GND, depending on their inactive levels, to reduce power  
DD  
To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80190 Peripheral Power-Down  
Register.  
All inputs are CMOS level 3.3V (5V tolerant), except where otherwise noted.  
PS019101-1003  
P R E L I M I N A R Y  
Peripheral Bus Connector (JP1)  
eZ801905050MOD  
eZ80190 Module Product Specification  
12  
Onboard Component Description  
Logic-Level I/Os  
The I/O connector features 32 general-purpose 3.3V CMOS I/O pins that can be  
used as outputs or inputs interfacing to external logic. All I/Os are 5V tolerant.  
2
Some of the General-Purpose I/O pins support dual mode functions (SPI, I C,  
UARTs, and bit I/O with edge- or level-triggered interrupt functions on each pin).  
For more information on eZ80190 dual modes, please refer to the eZ80190 Prod-  
uct Specification (PS0066).  
Onboard Battery Backup  
An onboard 0.1F capacitor (GoldCap) is used to bridge power outages of 2–4  
hours if the power supply to the module is disconnected. The capacitor is charged  
to 3.1V during normal operation and is discharged through the on-chip Real Time  
Clock. The VRTC pin is available on the I/O connector of the module to connect  
external components to a power supply or to a larger GoldCap.  
Do not connect a Lithium Battery to the GoldCap capacitor, because  
onboard charging circuitry for the capacitor can destroy the lithium  
battery.  
Caution:  
Ethernet Media Access Controller  
The eZ80190 contains a CS8900A EMAC which is attached to the data/address  
bus of the processor. This chip is connected to the processor’s CS3 Chip Select,  
A0–A3, D0–D7, RD, WR, and PD4 pins for interrupt purposes. Connection of pins  
PD6 and PD7 for LANACT (wake-up from sleep) and SLEEP is optional and resis-  
tor-selectable onboard.  
Ethernet LEDs  
There are two green LEDs, a Link LED and a LAN LED, that are located adjacent  
to each other on the eZ80190 Module. A steady LAN LED (top) indicates received  
link pulses from the Ethernet. A flashing Link LED (bottom) indicates Traffic (RX or  
TX) on the LAN.  
PS019101-1003  
P R E L I M I N A R Y  
Onboard Component Description  
eZ801905050MOD  
eZ80190 Module Product Specification  
13  
An RJ45 loopback connector can be used to verify the correct operation of the  
Receiver and the Transmitter. The green LED should be on if RX+ is connected  
with TX+ and RX– is connected with TX–.  
Ethernet Connector  
The eZ80190 is equipped with an RJ45 connector that features integrated mag-  
netics (transformer, common mode chokes). The remaining pins on the onboard  
RJ45 connector are not connected.  
Node assignments for the RJ45 Ethernet connector are shown in Table 3.  
Table 3. Ethernet Connector Pin Assignments  
Pin  
1
Function  
TX+  
2
TX–  
3
RX+  
6
RX–  
Node assignment, in contrast to hub assignment, means that a straight-through  
cable (equivalent pin numbers on both sides of the cable are connected to each  
other) is used to attach the board to an Ethernet hub or switch. To connect the  
eZ80190 Module directly to another node (e.g., a personal computer), a crossover  
cable must be used.  
The EMAC can be additionally protected by placing a U9 ESD protection array on  
the module. This array can be either of the LCDA15C-6 (Semtech) or ESDA25B1  
(ST Microelectronics) devices.  
GPIO Pins for Enabling LAN Activity, Sleep, Interrupt  
GPIO input bit PD4 serves as an active High interrupt input for the EMAC’s  
INTRQ0 output.  
GPIO output bit PD7 can be used to place the EMAC into SLEEP mode. In  
SLEEP mode, the CS8900 draws less current, because only the receiver is oper-  
ating. A zero-Ohm resistor at position R14 on the eZ80190 is required for this  
function. In this case, the PD6 pin is not available for GPIO on the I/O connector.  
If LAN activity is detected, the LANACT signal is pulled Low. The LANACT is con-  
nected to GPIO input PD6 and can be used in interrupt edge-detection mode to  
wake up and reinitialize the Ethernet chip. A zero-Ohm resistor at position R15 on  
PS019101-1003  
P R E L I M I N A R Y  
Ethernet Media Access Controller  
eZ801905050MOD  
eZ80190 Module Product Specification  
14  
the module is required for this function. In this case, the PD6 pin is not available  
for GPIO on the I/O connector.  
EMAC Ports  
The I/O base address is user-selectable. The EMAC is connected as an 8-bit  
device.  
EMAC Access  
For 50MHz operation, set CS3_CTL (I/O address 0xB3) to 0xF8 (7 wait states for  
I/O). CS3 is used for selecting the Ethernet MAC. By pulling JP1 pin 25 (DIS_Eth)  
Low, access to the Ethernet MAC can be disabled on a per-cycle basis.  
Memory  
The eZ80190 offers SRAM and Flash memories and the wait states that support  
memory operations, as described in this section.  
Wait States  
To ensure that valid data is read from or written to slower memories, a number of  
wait states must be inserted into the memory or I/O access operations by the pro-  
cessor. The number of wait states that are required should be added by program-  
ming the chip select control registers. To calculate the minimum number of wait  
states required, refer to Table 4.  
Table 4. Chip Frequency to Wait State Cycle Time Calculation  
MHz  
20  
Cycle Time  
50.0ns  
24  
41.7ns  
40  
25.0ns  
50  
20.0ns  
Static RAM  
The eZ80190 features 512KB of fast SRAM. Access speed is typically 12ns or  
faster, allowing zero-wait-state operation at 50MHz. With the CPU at 50MHz,  
PS019101-1003  
P R E L I M I N A R Y  
Memory  
eZ801905050MOD  
eZ80190 Module Product Specification  
15  
onboard SRAM can be accessed with zero wait states. The CS1_CTL register can  
be set to 08h (no wait states).  
Flash Memory  
The Flash Boot Loader, application code, and user configuration data are held  
permanently in NOR Flash memory. A typical application requires eight times  
more ROM for code than RAM. As an example, for 128KB onboard SRAM, 1MB  
of ROM is required. The eZ80190 allows NOR Flash memories between  
4megabits (512KB) and 32 megabits (4MB) to be used. The chips are housed in  
wide TSOP40 cases. Typical Flash ROM access time is 100ns.  
For 50MHz CPU operation, set the Chip Select Control register CS0_CTL (I/O  
address 0xAA) to 0xA8. This setting selects 5 wait states. CS0 is used for select-  
ing Flash memory. By pulling JP1 pin 26 (DIS_Flash) Low, access to Flash mem-  
ory can be disabled on a per-cycle basis.  
Real-Time Clock  
An onboard real-time-clock operates continually, even if the system power supply  
is down. An onboard capacitor (GoldCap) or external accumulator/battery serves  
as a standby power supply. The Real-Time-Clock M41T11 contains Binary Coded  
Decimal (BCD) counting registers for Seconds, Minutes, Hours, Day, Month, and  
Year; a Century bit and 56 bytes of backed-up RAM are also included. The fully  
charged 0.1F GoldCap bridges power outages with a maximum of 4 hours. The  
GoldCap, in contrast to a battery or an accumulator, offers the dual advantage of  
no service (replacement) requirements and no effects upon memory.  
2
2
The I C addresses of the RTC are 0xD0 for WRITE and 0xD1 for READ. The I C  
sequence for writing to the RTC is:  
Start → 0xD0 → RegNo → VALUE1 → … → VALUEn → Stop  
and the sequence for reading from the RTC is:  
Start → 0xD1 → RegNo → VALUE1 → … → VALUEn → Stop  
2
where VALUE1…VALUEn… are sent by the RTC. The processor (I C Master)  
requests another value by sending an ACK. The first register to be read is set by a  
preceding WRITE sequence, without sending data values. Clock updates do not  
occur while any of the seven clock registers are being read. See Figure 5.  
PS019101-1003  
P R E L I M I N A R Y  
Real-Time Clock  
eZ801905050MOD  
eZ80190 Module Product Specification  
16  
Table 5. Real-Time Clock Registers  
Data  
Function/Range BCD  
Format  
Address  
D7  
ST  
X
D6  
D5  
D4  
D3  
D2  
D1  
D0  
0
1
2
3
4
5
6
7
10 Seconds  
10 Minutes  
Seconds  
Seconds  
Minutes  
Hours  
Day  
00–59  
00–59  
Minutes  
Hours  
CEB*  
X
CB  
X
10 Hours  
0–1/00–23  
01–07  
X
X
S
X
X
Day  
X
X
10 Date  
Date  
Month  
Years  
Date  
01-31  
X
X
10 M.  
Month  
Year  
01–12  
10 Years  
00–99  
OUT  
FT  
Calibration  
Control  
Notes: *When CEB is set to 1, CB toggles from 0 to 1 or from 1 to 0 every 100 years, depending upon the initial vale  
set. When CEB is set to 0, CB does not toggle.  
Keys: S = Sign bit, FT = Frequency Test bit, ST = Stop bit, OUT = Output level, X = Don’t care, CEB = Century  
Enable bit, CB = Century Bit.  
For further details, please refer to the M41T11 data sheet from SGS-Thomson at  
www.st.com.  
Reset Generator  
The onboard Reset Generator Chip performs reliable Power-On Reset. The chip  
generates a reset pulse with a duration of 200ms if the power supply drops below  
2.93V. This reset pulse ensures that the board always starts in a defined condi-  
tion. The RESET pin on the I/O connector reflects the status of the RESET line. It  
is a bidirectional pin for resetting external peripheral components or for resetting  
the eZ80190 with a low-impedance output (e.g. a 100-Ohm pushbutton).  
Serial Interface Ports  
The processor contains two 16550-style UARTs with programmable baud rate  
®
generators. When the eZ80190 Module is plugged in to the eZ80 Development  
Platform, UART0 is connected to a console connector and UART1 is connected to  
a modem connector. There are no RS232-level shifters on the eZ80190.  
Do not connect an RS-232 interface without level shifters.  
Note:  
PS019101-1003  
P R E L I M I N A R Y  
Reset Generator  
eZ801905050MOD  
eZ80190 Module Product Specification  
17  
Physical Dimensions  
The footprint of the eZ80190 Module PCB is 63.5mmx78.7mm. With an RJ-45  
Ethernet connector, the overall height is 25mm. See Figure 4.  
63.5 mm  
Figure 4. Physical Dimensions of the eZ80190 Module  
PS019101-1003  
P R E L I M I N A R Y  
Serial Interface Ports  
eZ801905050MOD  
eZ80190 Module Product Specification  
18  
Figure 5 illustrates the top layer silkscreen of the eZ80190 Module.  
Figure 5. eZ80190 Module—Top Layer  
PS019101-1003  
P R E L I M I N A R Y  
Serial Interface Ports  
eZ801905050MOD  
eZ80190 Module Product Specification  
19  
Figure 6 illustrates the bottom layer silkscreen of the eZ80190 Module.  
Figure 6. eZ80190 Module—Bottom Layer  
ESD/EMI Protection  
Caution:  
The eZ80190 is a component that is intended to be part of a system  
design for end-user devices. Therefore, the user must exercise caution  
to use ESD protection on the I/O pins.  
The EMAC can be additionally protected by placing an ESD protection array on  
the eZ80190 at position U9. Either use ESDA25B1 from ST Microelectronics or  
LCDA15C-6 from Semtech. A mounting hole on the board can be used for  
grounding the shield of the Ethernet RJ45 jack to prevent surge or ESD currents  
from flowing through the digital circuitry.  
The RJ45 Ethernet Connector on the eZ80190 contains a transformer and com-  
mon mode chokes for EMI suppression.  
CMOS I/Os are ESD-sensitive and must be handled with care.  
Handling of the module should be performed in ESD-safe  
environments (for example with a wrist-wrap attached). When  
Caution:  
PS019101-1003  
P R E L I M I N A R Y  
ESD/EMI Protection  
eZ801905050MOD  
eZ80190 Module Product Specification  
20  
developing applications, the user must provide for proper ESD  
protection on external, user-accessible I/Os (e.g. suppressor arrays for  
the I/Os).  
The components are mounted on a multilayer PCB to provide a stable ground  
plane for onboard components. The module features several GND pins next to  
pins with higher switching frequency for short ground returns. If unused, the clock  
output can be separated from the module header by removing a series resistor on  
the module. Removing the series resistor further reduces electromagnetic emis-  
sions.  
Absolute Maximum Ratings  
Stresses greater than those listed in Table 6 can cause permanent damage to the  
device. These ratings are stress ratings only. Operation of the device at any con-  
dition outside those indicated in the operational sections of these specifications is  
not implied. Exposure to absolute maximum rating conditions for extended peri-  
ods may affect device reliability. For improved reliability, unused inputs should be  
tied to one of the supply voltages (VDD or VSS).  
Table 6. Absolute Maximum Ratings  
Parameter  
Min  
0
Max  
+70  
+85  
90%  
3.3  
Units  
ºC  
Standard operating temperature  
Storage temperature  
–45  
25%  
—
ºC  
Operating Humidity (RH @ 50ºC)  
Operating Voltage ( 5%)  
V
Power Supply  
The eZ80™ Webserver-i E-NET Module requires a regulated external 3.3VDC/  
0.5A power supply. You may use a Low Dropout Regulator (LDO) to get 3.3V from  
5V or use the following switcher circuit to generate 3.3V from unregulated 10-28V  
power supply.  
Power connections follow these conventional descriptions:  
Connection  
Power  
Circuit  
VCC  
Device  
V
V
DD  
SS  
Ground  
GND  
PS019101-1003  
P R E L I M I N A R Y  
Power Supply  
eZ801905050MOD  
eZ80190 Module Product Specification  
21  
Switcher 10–28V → 3.3V  
To Module  
U1  
LM2575S-ADJ  
4
2
L1  
10–28V  
VDD  
3.3V  
FB  
VOUT  
1
V
VIN  
O
IN  
N
330uH/1A  
R1  
5k6  
1%  
/
G
N
D
O
F
F
C2  
C1  
100n  
D1  
1A/30V  
C3  
1000uF  
470uF/6.3V  
Low ESR  
R2  
3k3  
3
5
1%  
GND  
GND  
LDO 5V → 3.3V  
U1  
LM3940  
4-6V  
VDD  
V
VI  
VO  
3.3V  
CC  
G
N
D
C3  
470uF/6.3V  
Low ESR  
C1  
100n  
GND  
GND  
Figure 7. Power Supply Examples  
PS019101-1003  
P R E L I M I N A R Y  
Power Supply  
eZ801905050MOD  
eZ80190 Module Product Specification  
22  
Document Number Description  
The Document Control Number that appears in the footer of each page of this  
document contains unique identifying attributes, as indicated in the following  
table:  
PS  
Product Specification  
Unique Document Number  
Revision Number  
0191  
01  
1003  
Month and Year Published  
Change Log  
Rev  
Date  
Purpose  
Original issue  
By  
01  
October 2003  
M. Staubermann  
PS019101-1003  
P R E L I M I N A R Y  
Document Number Description  
eZ801905050MOD  
eZ80190 Module Product Specification  
Schematic Diagrams  
23  
Figures 8 through 15 present the schematics of the eZ80190 Module.  
X1  
R13  
ETHIRQ  
-SLEEP  
-ACTIVE  
PD4  
PD7  
PD6  
PA[0..7]  
XIN  
3
1
=
ETHIRQ  
-SLEEP  
-ACTIVE  
OUT  
OE  
4k7  
0603  
50.000MHz, 3.3V  
SG-710  
PD[0..7]  
0R  
0603  
R14  
R15  
PA[0..7]  
PA[0..7]  
0R  
0603  
CLK_OUT  
don't  
stuff  
PC[0..7]  
-WR  
-RD  
-MREQ  
-WR  
-RD  
-CS0  
-CS1  
-CS2  
-CS3  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
75  
-WR  
-RD  
MREQ  
WR  
RD  
CS0  
CS1  
CS2  
CS3  
VDD  
VSS  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
VDD  
VSS  
A8  
TEST  
PC7/RI1  
PC6/DCD1  
PC5/DSR1  
PC4/DTR1  
PC7  
PC6  
PC5  
PC4  
PC3  
PC2  
PC1  
PC0  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
PB[0..7]  
PB[0..7]  
-CS[0..3]  
PC[0..7]  
PC[0..7]  
-CS[0..3]  
PC3/SS1/CTS1  
PC2/SCK1/RTS1  
PC1/SDA1/MOSI1/RxD1  
PC0/SCL1/MISO1/TxD1  
PD[0..7]  
PD[0..7]  
-CS0 --> FLASH  
-CS1 --> RAM  
-CS2 --> ext. IO  
-CS3 --> ETH  
U1  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
VSS  
VDD  
PB7  
PB6  
PB5  
PB4  
PB3  
PB2  
PB1  
PB7  
PB6  
PB5  
PB4  
PB3  
PB2  
PB1  
PB0  
ZDA  
ZCL  
-RESET  
-IOREQ  
-INSTRD  
-HALT  
ZDA  
ZDA  
D[0..7]  
ZCL  
ZCL  
eZ80190  
D[0..7]  
A[0..23]  
A[0..23]  
TQFP100  
PB0  
ZDA  
ZCL  
-BUSREQ  
-BUSACK  
-MREQ  
A8  
A9  
A10  
A11  
A12  
A13  
-BUSREQ  
-BUSACK  
-MREQ  
A9  
PB[0..7]  
A10  
A11  
A12  
A13  
RESET  
IORQ  
INSTRD  
HALT  
-RESET  
-RESET  
CLK_OUT  
CLK_OUT  
-IOREQ  
-IOREQ  
-INSTRD  
-INSTRD  
R4  
-NMI  
-HALT  
-HALT  
1k  
0603  
R30  
R31  
-NMI  
-NMI  
don't  
stuff  
0R  
0603  
0R  
0603  
A[0..23]  
D[0..7]  
IICSDA  
IICSCL  
PA7  
IICSDA  
IICSCL  
0R  
0603  
R32  
R33  
place caps close  
to pins 97, 8, 38, 48  
C18  
1nF  
0603  
C19  
1nF  
0603  
C20  
1nF  
0603  
PA6  
0R  
0603  
Figure 8. eZ80190 Module Schematic Diagram, #1 of 9—CPU  
PS019101-1003  
PRELIMINARY  
Schematic Diagrams  
eZ801905050MOD  
eZ80190 Module Product Specification  
24  
U2  
A18  
A0  
A1  
A2  
A3  
-CSRAM  
D0  
D1  
A20  
A16  
A15  
A14  
A13  
-RD  
D7  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
A0  
A1  
A2  
A3  
N.C.  
A18  
A17  
A16  
A15  
OE  
I/O7  
I/O6  
VSS  
VDD  
I/O5  
I/O4  
A14  
A13  
A12  
A11  
A10  
N.C.  
RN1  
10  
D[0..7]  
D[0..7]  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
9
8
7
6
5
4
3
2
A[0..23]  
A21/ A22/ A23  
not used her e  
A[0..23]  
A4  
CE  
I/O0  
I/O1  
VDD  
VSS  
I/O2  
I/O3  
WE  
A5  
A6  
A7  
A8  
A9  
D6  
-CS1  
-CSRAM  
1
=
-CS1  
D2  
D3  
-WR  
A12  
A9  
A6  
A4  
A17  
D5  
D4  
A11  
A8  
A10  
A7  
A5  
9 x 4k7  
SIP10  
-RD  
-RD  
-WR  
-WR  
A19  
512kx8 fast SRAM  
SOJ36.400  
AS7C34096-10JC  
V3.3  
VDD  
VSS  
C1  
100nF  
0603  
GND  
Figure 9. eZ80190 Module Schematic Diagram, #2 of 9—36-Pin SRAM Device  
PS019101-1003  
PRELIMINARY  
Schematic Diagrams  
eZ801905050MOD  
eZ80190 Module Product Specification  
25  
D[0..7]  
A[0..23]  
I nt el - Type  
U3  
U4  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
DFLASH0  
DFLASH1  
DFLASH2  
DFLASH3  
DFLASH4  
DFLASH5  
DFLASH6  
DFLASH7  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
21  
20  
19  
18  
17  
16  
15  
14  
8
7
36  
6
5
4
3
2
1
40  
13  
37  
25  
DQ0  
26  
2
5
6
3
4
7
8
11  
14  
17  
18  
21  
22  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
1B1  
1A1  
1A2  
1A3  
1A4  
1A5  
2A1  
2A2  
2A3  
2A4  
2A5  
DQ1  
27  
1B2  
1B3  
1B4  
1B5  
2B1  
2B2  
2B3  
2B4  
2B5  
DQ2  
28  
9
DQ3  
32  
10  
15  
16  
19  
20  
23  
DQ4  
33  
DQ5  
34  
DQ6  
35  
DQ7  
A8  
A9  
A8  
A9  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
-CSFLASH  
-RD  
-WR  
-RESFLASH  
-WP  
22  
CE  
C2  
100nF  
0603  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
24  
1
13  
OE  
9
1OE  
2OE  
-CSFLASH  
WE  
RP  
WP  
10  
12  
74CBTLV3384  
SO24.300  
R5  
VPP  
11  
VPP  
0R 0603  
A21  
A20  
29  
N.C.  
A20/ A21 used f or  
16/ 32Mbi t - Fl ash  
38  
N.C.  
Pi n37=N. C.  
f or 4Mbi t -  
Fl ashes  
Flash 1Mx8 3.3V  
TSOP40.20MM  
MT28F008B3VG  
D[0..7]  
D[0..7]  
A[0..23]  
A22/ A23  
A[0..23]  
U5A  
1
not used her e  
U6A  
-CS0  
-RD  
-CSFLASH  
3
-RD  
-DIS_FLASH  
-FLASH_EN  
1
2
2
-WR  
-WR  
-CS0  
74LCX32  
TSSOP14  
R6  
74LCX04  
TSSOP14  
V3.3  
-CS0  
10k  
0603  
-DIS_FLASH  
-DIS_FLASH  
VDD  
VSS  
R7  
-RESET  
-RESFLASH  
=
10k  
0603  
-RESET  
U6B  
GND  
-FLASHWE  
-FLASHWE  
-WP  
3
4
-FLASHWE  
Note: Must be pulled Low  
externally for programming.  
74LCX04  
TSSOP14  
Figure 10. eZ80190 Module Schematic Diagram, #3 of 9—NOR Flash Device  
PS019101-1003  
PRELIMINARY  
Schematic Diagrams  
eZ801905050MOD  
eZ80190 Module Product Specification  
26  
R8  
10k  
0603  
Dual-LED assembly,  
right angle, grn/grn  
R9  
100  
0603  
R10  
100  
0603  
LD1  
green  
-LANLED  
-LINKLED  
-LANLED  
-LINKLED  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
100  
99  
98  
97  
96  
95  
94  
93  
92  
91  
90  
89  
88  
87  
86  
85  
84  
83  
82  
81  
80  
79  
78  
77  
76  
SD9  
SD8  
LANLED  
LINKLED/HC0  
XTAL2  
XTAL1  
AVSS  
upper LED  
green  
R11  
4k7  
0603  
MEMW  
MEMR  
INTRQ2  
INTRQ1  
INTRQ0  
IOCS16  
MEMCS16  
INTRQ3  
SHBE  
SA0  
SA1  
SA2  
SA3  
SA4  
SA5  
SA6  
SA7  
SA8  
Y1  
20.000 MHz  
HC49  
lower LED  
5682F5;5  
LED5682F  
AVDD  
AVSS  
RES  
ETHIRQ  
R12  
4k99/1%  
U7  
RXD-  
RXD+  
RXD-  
0603  
RXD+  
AVDD  
AVSS  
TXD-  
TXD+  
AVSS  
AVDD  
DO-  
DO+  
CI-  
ESD protection array  
U8  
CS8900A-CQ3  
TQFP100  
SA0  
SA1  
SA2  
SA3  
TXD-  
TXD+  
RD+  
RD-  
TD+  
TD-  
1
2
3
4
8
7
6
5
SA[0..3]  
CI+  
DI-  
DI+  
SA9  
SA10  
SA11  
REFRESH  
SA12  
BSTATUS/HC1  
SLEEP  
TEST  
-DIS_ETH  
-SLEEP  
i nt . Pul l - Up  
LCDA15C-6  
SO8.150  
GND  
GND  
TXD-  
TD-  
CASE  
8R2  
0603  
C3  
560pF  
0603  
R1  
J1  
device addresses:  
00300h bis 0030Fh  
1
2
3
4
5
6
TXD+  
TD+  
CTD  
C4  
100nF  
0603  
8R2  
0603  
R2  
-ETHRD  
-ETHWR  
-DIS_ETH  
CRD  
-ETHRD  
-ETHWR  
-ETHRD  
-ETHWR  
RXD-  
RD-  
8
R3  
-DIS_ETH  
100  
0603  
shi el d  
HFJ11-1041(E)  
HALOFASTJACK  
RXD+  
JP4  
RD+  
C5  
100nF  
0603  
C6  
SD[0..7]  
SA[0..3]  
ETHIRQ  
SD[0..7]  
TX+ <- > 1  
TX- <- > 2  
RX+ <- > 3  
RX- <- > 6  
100nF  
0603  
SD[0..7]  
SA[0..3]  
ETHIRQ  
through-hole  
solder pad  
place near  
FAST JACK  
HEADER 1  
SIP1  
V3.3  
plane or  
big trace  
CASE  
do not  
stuff  
VDD  
VSS  
L1  
-SLEEP  
CASE  
-SLEEP  
ferrite  
1210  
-ACTIVE  
-LANLED  
=
-ACTIVE  
GND  
do not stuff  
Figure 11. eZ80190 Module Schematic Diagram, #4 of 9—Ethernet Module  
PS019101-1003  
PRELIMINARY  
Schematic Diagrams  
eZ801905050MOD  
eZ80190 Module Product Specification  
27  
U9  
D[0..7]  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
SD0  
SD1  
SD2  
SD3  
SD4  
SD5  
SD6  
SD7  
SD[0..7]  
SD[0..7]  
3
4
5
6
7
8
9
10  
22  
21  
20  
19  
18  
17  
16  
15  
D[0..7]  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
B0  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
A[0..23]  
SA[0..3]  
SA[0..3]  
A[0..23]  
-RD  
-RD  
-ETHWR  
-WR  
-CSETH  
13  
14  
11  
OEAB  
LEAB  
CEAB  
-WR  
D[0..7]  
SD[0..7]  
-WR  
-RD  
2
1
23  
OEBA  
LEBA  
CEBA  
-CS3  
-CSETH  
=
-CS3  
-CSETH  
74LCX543  
TSSOP24  
-ETHRD  
-ETHRD  
CLK_OUT  
CLK_OUT  
-ETHWR  
-ETHWR  
U10  
A0  
A1  
A2  
A3  
SA0  
SA1  
SA2  
SA3  
2
3
4
5
6
7
8
9
19  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
Q1  
Q2  
18  
17  
16  
15  
14  
13  
12  
Q3  
Q4  
Q5  
Q6  
Q7  
Q8  
A[0..23]  
SA[0..3]  
CSETH_P  
11  
1
LE  
OE  
74LCX573  
TSSOP20  
U5B  
-RD  
4
5
-ETHRD  
-ETHWR  
6
8
-CSETH1D  
U6C  
74LCX32  
TSSOP14  
CSETH_P  
5
6
don't  
stuff  
R16  
0R  
0603  
U5C  
74LCX04  
TSSOP14  
-WR  
9
U11A  
U11B  
Q
-CSETH  
-CSETH1D  
CLK_OUT  
-CSETH2D  
2
3
5
6
12  
D
9
8
10  
D
Q
R17  
0R  
0603  
CLK_OUT  
74LCX32  
TSSOP14  
11  
CLK  
CLK  
Q
Q
V3.3  
74LCX74  
TSSOP14  
74LCX74  
TSSOP14  
VDD  
VSS  
V3.3  
V3.3  
GND  
Figure 12. eZ80190 Module Schematic Diagram, #5 of 9—Ethernet Module Logic  
PS019101-1003  
PRELIMINARY  
Schematic Diagrams  
eZ801905050MOD  
eZ80190 Module Product Specification  
28  
power supervisor  
V3.3  
C7  
100nF  
0603  
R18  
2k2  
0603  
U12  
-RESET  
-RESET  
2
-RESET  
RESET  
open-drain  
C8  
10nF  
0603  
MAX6328UR29  
SOT-23-L3  
alternative:  
Maxim MAX6802UR29D3  
real-time clock  
Gold Cap  
C9  
0,1F  
R19  
V3.3  
100  
0603  
GOLDCAP_SD_V  
D1  
RTC_VDD  
C10  
100nF  
0603  
RTC_VDD  
TMM BAT41  
MINIMELF_AK  
R20  
VBAT  
5
RTC_VDD  
0R  
0603  
U13  
1
IICSDA  
ICISCL  
SDA  
SCL  
R21  
R22  
6
OSCI  
2
4k7  
0603  
4k7  
0603  
OSCO  
Y2  
7
FT/OUT  
V3.3  
4k7  
0603  
R23  
IICSDA  
ICISCL  
M41T11M6  
SO8.150  
32.768kHz  
XTAL3  
IICSDA  
VDD  
ICISCL  
VSS  
I2C bus address:  
{D0}H/{D1}H  
C11  
unplace  
0603  
GND  
Figure 13. eZ80190 Module Schematic Diagram, #6 of 9—Ethernet Module Peripherals  
PS019101-1003  
PRELIMINARY  
Schematic Diagrams  
eZ801905050MOD  
eZ80190 Module Product Specification  
29  
A[0..23]  
D[0..7]  
A[0..23]  
D[0..7]  
connector 1  
connector 2  
JP1  
JP2  
PA7  
PA5  
PA3  
PA1  
V3.3_EXT  
PB7  
PB5  
PB3  
PB1  
GND_EXT  
PC6  
PC4  
PC2  
PC0  
PD6  
PD5  
PD3  
PD1  
PA6  
PA4  
PA2  
1
3
5
7
2
4
6
1
3
5
7
2
4
6
-CS[0..3]  
-CS[0..3]  
PA0  
8
8
GND_EXT  
A6  
A10  
GND_EXT  
A8  
A13  
A15  
A18  
A19  
A2  
A11  
A4  
A5  
-DIS_ETH  
A21  
V3.3_EXT  
A0  
A3  
V3.3_EXT  
A7  
A9  
A14  
A16  
GND_EXT  
A1  
A12  
GND_EXT  
9
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
38  
40  
42  
44  
46  
48  
50  
52  
54  
56  
58  
60  
9
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
38  
40  
42  
44  
46  
48  
50  
52  
54  
56  
58  
60  
IICSDA  
IICSCL  
PB6  
PB4  
PB2  
PB0  
PC7  
PC5  
PC3  
PC1  
PD7  
IICSDA  
IICSCL  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
35  
37  
39  
41  
43  
45  
47  
49  
51  
53  
55  
57  
59  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
35  
37  
39  
41  
43  
45  
47  
49  
51  
53  
55  
57  
59  
R24  
CLK_OUT  
EZ80CLK  
CLK_OUT  
33 0603  
-DIS_FLASH  
-DIS_FLASH  
place near eZ80  
output (PHI)  
-FLASHWE  
RTC_VDD  
PB[0..7]  
GND_EXT  
PD4  
-FLASHWE  
RTC_VDD  
PB[0..7]  
A20  
A17  
PD2  
PD0  
ZDA  
-DIS_FLASH  
V3.3_EXT  
A23  
-CS1  
D0  
D2  
D4  
GND_EXT  
D6  
-IOREQ  
-RD  
A22  
GND_EXT  
ZCL  
RTC_VDD  
IICSCL  
IICSDA  
-FLASHWE  
-CS3  
-RESET  
V3.3_EXT  
-HALT  
PC[0..7]  
-CS0  
-CS2  
D1  
D3  
D5  
PC[0..7]  
EZ80CLK  
GND_EXT  
GND_EXT  
GND_EXT  
PD[0..7]  
R25  
PD[0..7]  
10k  
0603  
PA[0..7]  
PA[0..7]  
D7  
-DIS_ETH  
-MREQ  
GND_EXT  
-WR  
-BUSACK  
NOTUSED1  
GND_EXT  
-NMI  
-DIS_ETH  
-INSTRD  
-BUSREQ  
-RESET  
V3.3_EXT  
-RESET  
NC  
-RD  
-WR  
Header 30x2  
Header 30x2  
-RD  
-WR  
Pin 50 open,  
to be keyed  
peripheral bus  
connector  
I/O connector  
-IOREQ  
-MREQ  
-INSTRD  
-IOREQ  
-MREQ  
-INSTRD  
R26  
2k2  
0603  
-HALT  
-HALT  
-BUSREQ  
-BUSACK  
-BUSREQ  
-BUSACK  
R27  
R28  
R29  
10k  
0603  
10k  
0603  
10k  
0603  
-NMI  
-NMI  
ZDA  
ZCL  
NOTUSED1  
( * WAI T * )  
ZDA  
ZCL  
V3.3  
V3.3_EXT  
GND_EXT  
GND  
Figure 14. eZ80190 Module Schematic Diagram, #7 of 9—Headers  
PS019101-1003  
PRELIMINARY  
Schematic Diagrams  
eZ801905050MOD  
eZ80190 Module Product Specification  
30  
common power plane  
V3.3  
GND  
VDD  
no power supply on board  
C12  
C13  
C14  
1nF  
C15  
100nF  
0603  
C16  
1nF  
0603  
C17  
22uF  
22uF  
100nF  
0603  
SMT7343  
SMT7343  
0603  
VSS  
Input: VDD ( = V3.3) = 3.3V 5%  
Power: Pmax = tbd  
Ptyp = tbd  
common ground plane  
Current: lmax = tbd  
ltyp = tbd  
PCB1  
eZ80190 ethernet module board  
98Cxxxx-xxx  
U6D  
U5D  
12  
11  
13  
9
11  
13  
8
74LCX32  
TSSOP14  
74LCX04  
TSSOP14  
unused gates  
U6E  
10  
74LCX04  
TSSOP14  
U6F  
12  
74LCX04  
TSSOP14  
Figure 15. eZ80190 Module Schematic Diagram, #8 of 9—Power Supply  
PS019101-1003  
PRELIMINARY  
Schematic Diagrams  
eZ801905050MOD  
eZ80190 Module Product Specification  
31  
Customer Feedback Form  
The eZ80190 Module Product Specification  
If you experience any problems while operating this product, or if you note any inaccuracies  
while reading this Product Specification, please copy and complete this form, then mail or fax it to  
ZiLOG (see Return Information, below). We also welcome your suggestions!  
Customer Information  
Name  
Country  
Phone  
Fax  
Company  
Address  
City/State/Zip  
Email  
Product Information  
Serial # or Board Fab #/Rev. #  
Software Version  
Document Number  
Host Computer Description/Type  
Return Information  
ZiLOG  
System Test/Customer Support  
532 Race Street  
San Jose, CA 95126  
Phone: (408) 558-8500  
Fax: (408) 558-8536  
ZiLOG Customer Support  
Problem Description or Suggestion  
Provide a complete description of the problem or your suggestion. If you are reporting a specific  
problem, include all steps leading up to the occurrence of the problem. Attach additional pages  
as necessary.  
_____________________________________________________________________________________________  
_____________________________________________________________________________________________  
_____________________________________________________________________________________________  
_____________________________________________________________________________________________  
_____________________________________________________________________________________________  
PS019101-1003  
P R E L I M I N A R Y  
Customer Feedback Form  
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