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CYM1846V33P8-35C

型号：

CYM1846V33P8-35C

描述：

512K ×32的3.3V静态RAM模块[ 512K x 32 3.3V Static RAM Module ]

品牌：

CYPRESS[ CYPRESS ]

页数：

8 页

PDF大小：

314 K

下载PDF手册
46V33  
PRELIMINARY  
CYM1846V33  
512K x 32 3.3V Static RAM Module  
module is constructed from four 512K x 8 SRAMs in SOJ pack-  
ages mounted on an epoxy laminate substrate. Four chip se-  
lects are used to independently enable the four bytes. Reading  
or writing can be executed on individual bytes or any combina-  
tion of multiple bytes through proper use of selects.  
Features  
• High-density 3.3V 16-megabit SRAM module  
• 32-bit Standard Footprint supports densities from  
16K x 32 through 2M x 32  
• High-speed SRAMs  
— Access time of 12 ns  
• Low active power  
The CYM1846V33 is designed for use with standard 72-pin  
SIMM sockets. The pinout is downward compatible with the  
64-pin JEDEC ZIP/SIMM module family (CYM1821,  
CYM1831, CYM1836, and CYM1841). Thus, a single mother-  
board design can be used to accommodate memory depth  
ranging from 16K words (CYM1821) to 1,024K words  
(CYM1851). The CYM1846V33 is offered in vertical SIMM  
configuration and is available with either tin-lead or 10  
micro-inches of gold flash on the edge contacts.  
— 1.650W (max.) at 12 ns  
• 72 pins  
• Available in ZIP, SIMM format  
Functional Description  
Presence detect pins (PD0−PD3) are used to identify module  
memory density in applications where modules with alternate  
word depths can be interchanged.  
The CYM1846V33 is a high-performance 3.3V 16-megabit  
static RAM module organized as 512K words by 32 bits. This  
Pin Configuration  
Logic Block Diagram  
ZIP/SIMM  
Top View  
PD - OPEN  
0
PD - OPEN  
PD - GND  
2
NC  
PD  
1
3
5
1
NC  
3
PD  
0
2
4
A0–A18  
2
PD  
19  
GND  
PD - OPEN  
3
OE  
6
8
7
9
PD  
1
8
I/O  
0
WE  
I/O  
I/O  
1
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
I/O  
I/O  
I/O  
9
10  
11  
I/O  
2
I/O –I/O  
0
7
I/O  
3
512K x 8  
SRAM  
8
8
8
8
V
CC  
7
8
A
0
A
A
1
2
A
CS  
1
A
A
9
I/O  
I/O  
I/O  
I/O  
12  
13  
14  
15  
I/O  
I/O  
I/O  
I/O  
4
5
6
7
I/O –I/O  
7
15  
512K x 8  
SRAM  
GND  
WE  
CS  
CS  
CS  
2
3
4
33  
35  
A
15  
A
14  
34  
36  
CS  
CS  
2
CS  
1
I/O –I/O  
16  
23  
512K x 8  
SRAM  
37  
39  
41  
43  
45  
47  
49  
51  
53  
55  
57  
59  
61  
63  
65  
67  
69  
71  
4
CS  
3
38  
40  
42  
44  
46  
48  
50  
52  
54  
56  
58  
60  
62  
64  
66  
68  
70  
72  
A
17  
A
16  
OE  
GND  
I/O  
I/O  
I/O  
I/O  
24  
25  
26  
27  
I/O  
16  
I/O  
17  
I/O –I/O  
24  
31  
512K x 8  
SRAM  
I/O  
18  
I/O  
19  
A
3
A
10  
A
4
5
A
11  
12  
13  
20  
21  
22  
23  
A
A
V
CC  
A
A
6
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
28  
29  
30  
31  
GND  
A
18  
NC  
NC  
NC  
Cypress Semiconductor Corporation  
Document #: 38-05275 Rev. **  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Revised March 15, 2002  
PRELIMINARY  
CYM1846V33  
Selection Guide  
1846V33-12 1846V33-15 1846V33-20  
1846V33-25  
1846V33-35  
Maximum Access Time (ns)  
12  
15  
20  
25  
35  
Maximum Operating Current (mA)  
820  
120  
800  
120  
780  
120  
780  
120  
780  
120  
Maximum Standby Current (mA)  
Shaded area contains advance information.  
Maximum Ratings [1]  
DC Input Voltage ............................................–0.5V to +4.6V  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Operating Range  
Ambient  
Storage Temperature .................................–55°C to +125°C  
Range  
Temperature  
VCC  
Ambient Temperature with  
Power Applied...............................................–10°C to +85°C  
Commercial  
0°C to +70°C  
3.3V + 10%  
/ –5%  
Supply Voltage to Ground Potential............... –0.5V to +4.6V  
DC Voltage Applied to Outputs  
in High Z State................................................ –0.5V to +VCC  
Electrical Characteristics Over the Operating Range  
Parameter  
VOH  
VOL  
Description  
Output HIGH Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
Input Load Current  
Output Leakage Current  
Test Conditions  
Min.  
Max.  
Unit  
V
VCC = Min., IOH = −4.0 mA  
2.4  
VCC = Min., IOL = 4.0 mA  
0.4  
VCC + 0.3  
0.8  
V
VIH  
2.0  
–0.3  
–10  
–10  
V
VIL  
V
IIX  
GND < VI < VCC  
+10  
µA  
µA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
IOZ  
GND < VO < VCC, Output Disabled  
VCC = Max., IOUT = 0 mA, −12  
+10  
ICC  
VCC Operating Supply  
Current  
820  
CSN < VIL, F = FMAX  
−15  
800  
−20,−25,−35  
–12  
780  
ISB1  
Automatic CS Power-Down  
Current[2]  
Max. VCC, CS > VIH,  
Min. Duty Cycle = 100%  
180  
−15  
160  
−20,−25,−35  
140  
ISB2  
Automatic CS Power-Down  
Current[2]  
Max. VCC, CS > VCC − 0.2V, VIN > VCC − 0.2V,  
120  
or VIN < 0.2V  
Shaded area contains advance information.  
Capacitance[3]  
Parameter  
CINA  
Description  
Test Conditions  
Max.  
32  
8
Unit  
pF  
Input Capacitance (WE, OE, A0–18  
)
TA = 25°C, f = 1 MHz,  
VCC = 5.0V  
CINB  
Input Capacitance (CS)  
pF  
COUT  
Output Capacitance  
8
pF  
Notes:  
1. If device is operated at these settings, long term reliability will be affected.  
2. A pull-up resistor to VCC on the CS input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given.  
3. Tested on a sample basis.  
Document #: 38-05275 Rev. **  
Page 2 of 8  
PRELIMINARY  
CYM1846V33  
AC Test Loads and Waveforms  
R1 315 Ω  
R1 315 Ω  
ALL INPUT PULSES  
90%  
10%  
5V  
5V  
OUTPUT  
3.0V  
90%  
10%  
OUTPUT  
R2  
351Ω  
R2  
351Ω  
GND  
≤ 5 ns  
30 pF  
5 pF  
≤
5ns  
INCLUDING  
JIG AND  
SCOPE  
INCLUDING  
JIG AND  
SCOPE  
(a)  
(b)  
(c)  
Equivalent to:  
THÉVENIN EQUIVALENT  
167Ω  
1.73V  
OUTPUT  
Switching Characteristics Over the Operating Range[4]  
1846V33-12  
1846V33-15  
Parameter  
Description  
Min.  
12  
3
Max.  
Min.  
Max.  
Unit  
READ CYCLE  
tRC  
Read Cycle Time  
15  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
Address to Data Valid  
12  
15  
tOHA  
tACS  
Data Hold from Address Change  
CS LOW to Data Valid  
OE LOW to Data Valid  
OE LOW to Low Z  
3
12  
7
15  
8
tDOE  
tLZOE  
tHZOE  
tLZCS  
tHZCS  
tPD  
0
3
0
3
OE HIGH to High Z  
CS LOW to Low Z[5]  
7
8
CS HIGH to High Z[5, 6]  
7
8
CS HIGH to Power-Down  
12  
15  
WRITE CYCLE[7]  
tWC  
Write Cycle Time  
12  
9
15  
10  
10  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tSCS  
CS LOW to Write End  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
tAW  
9
tHA  
0
tSA  
1
1
tPWE  
tSD  
10  
7
12  
8
Data Set-Up to Write End  
Data Hold from Write End  
WE HIGH to Low Z  
tHD  
1
1
tLZWE  
tHZWE  
3
3
WE LOW to High Z[6]  
0
7
0
8
Shaded area contains advance information.  
Notes:  
4. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified  
IOL/IOH and 30-pF load capacitance.  
5. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device. These parameters are guaranteed and not 100% tested.  
6.  
tHZCS and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage.  
7. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can  
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.  
Document #: 38-05275 Rev. **  
Page 3 of 8  
PRELIMINARY  
CYM1846V33  
Switching Characteristics Over the Operating Range[4] (continued)  
1846V33-20  
1846V33-25  
1846V33-35  
Parameter  
Description  
Min.  
20  
3
Max.  
Min.  
25  
3
Max.  
Min.  
35  
3
Max.  
Unit  
READ CYCLE  
tRC  
Read Cycle Time  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
Address to Data Valid  
Data Hold from Address Change  
CS LOW to Data Valid  
OE LOW to Data Valid  
OE LOW to Low Z  
20  
25  
35  
tOHA  
tACS  
tDOE  
tLZOE  
tHZOE  
tLZCS  
tHZCS  
tPD  
20  
12  
25  
15  
35  
18  
0
3
0
3
0
3
OE HIGH to High Z  
CS LOW to Low Z[5]  
CS HIGH to High Z[5, 6]  
10  
12  
15  
10  
20  
12  
25  
15  
35  
CS HIGH to Power-Down  
WRITE CYCLE[7]  
tWC Write Cycle Time  
tSCS  
tAW  
20  
17  
17  
3
25  
20  
20  
3
35  
30  
30  
3
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CS LOW to Write End  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
tHA  
tSA  
2
2
2
tPWE  
tSD  
15  
12  
2
20  
15  
2
30  
20  
2
Data Set-Up to Write End  
Data Hold from Write End  
WE HIGH to Low Z  
tHD  
tLZWE  
tHZWE  
3
3
3
WE LOW to High Z[6]  
0
12  
0
12  
0
15  
Switching Waveforms  
[8, 9]  
Read Cycle No. 1  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
Notes:  
8. WE is HIGH for read cycle.  
9. Device is continuously selected, CS = VIL, and OE= VIL  
.
Document #: 38-05275 Rev. **  
Page 4 of 8  
PRELIMINARY  
CYM1846V33  
Switching Waveforms (continued)  
[8,10]  
Read Cycle No. 2  
t
RC  
CS  
t
ACS  
OE  
t
HZOE  
t
DOE  
t
HZCS  
t
LZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA VALID  
DATA OUT  
t
LZCS  
t
PD  
t
PU  
ICC  
ISB  
VCC  
SUPPLY  
CURRENT  
50%  
50%  
Write Cycle No. 1 (WE Controlled) [7]  
t
WC  
ADDRESS  
CS  
t
SCS  
t
t
HA  
AW  
t
t
SA  
PWE  
WE  
t
t
HD  
SD  
DATA IN  
DATA VALID  
t
t
LZWE  
HZWE  
HIGH IMPEDANCE  
DATA OUT  
DATA UNDEFINED  
Note:  
10. Address valid prior to or coincident with CS transition LOW.  
Document #: 38-05275 Rev. **  
Page 5 of 8  
PRELIMINARY  
CYM1846V33  
Switching Waveforms (continued)  
Write Cycle No. 2 (CS Controlled)[7,11]  
t
WC  
ADDRESS  
t
SA  
t
SCS  
CS  
t
t
HA  
AW  
t
PWE  
WE  
t
t
HD  
SD  
DATA IN  
DATA VALID  
t
HZWE  
HIGH IMPEDANCE  
DATA OUT  
DATA UNDEFINED  
Truth Table  
CS  
H
L
WE  
X
OE  
X
Inputs/Output  
Mode  
High Z  
Deselect/Power-Down  
H
L
Data Out  
Data In  
High Z  
Read  
L
L
X
Write  
L
H
H
Deselect  
Ordering Information  
Package  
Type  
Operating  
Range  
Speed (ns)  
Ordering Code  
CYM1846V33PM-12C  
CYM1846V33P8-12C  
CYM1846V33PZ-12C  
CYM1846V33PM-15C  
CYM1846V33P8-15C  
CYM1846V33PZ-15C  
CYM1846V33PM-20C  
CYM1846V33P8-20C  
CYM1846V33PZ-20C  
CYM1846V33PM-25C  
CYM1846V33P8-25C  
CYM1846V33PZ-25C  
Package Type  
12  
PM21  
PM21  
PZ11  
PM21  
PM11  
PZ11  
PM21  
PM21  
PZ11  
PM21  
PM21  
PZ11  
72-Pin Plastic SIMM Module  
Commercial  
72-Pin Plastic SIMM Module (gold contacts)  
72-Pin Plastic ZIP Module  
15  
20  
25  
72-Pin Plastic SIMM Module  
72-Pin Plastic SIMM Module (gold contacts)  
72-Pin Plastic ZIP Module  
72-Pin Plastic SIMM Module  
72-Pin Plastic SIMM Module (gold contacts)  
72-Pin Plastic ZIP Module  
72-Pin Plastic SIMM Module  
72-Pin Plastic SIMM Module (gold contacts)  
72-Pin Plastic ZIP Module  
Shaded area contains advance information.  
Note:  
11. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.  
Document #: 38-05275 Rev. **  
Page 6 of 8  
PRELIMINARY  
CYM1846V33  
Ordering Information (continued)  
Package  
Operating  
Range  
Speed (ns)  
Ordering Code  
CYM1846V33PM-35C  
CYM1846V33P8-35C  
CYM1846V33PZ-35C  
Type  
PM21  
PM21  
PZ11  
Package Type  
72-Pin Plastic SIMM Module  
35  
Commercial  
72-Pin Plastic SIMM Module (gold contacts)  
72-Pin Plastic ZIP Module  
Package Diagrams  
72-Pin Plastic SIMM Module PM21  
72-Pin Plastic ZIP Module PZ11  
Document #: 38-05275 Rev. **  
Page 7 of 8  
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
PRELIMINARY  
CYM1846V33  
Document Title: CYM1846V33 512K x 32 3.3V Static RAM Module  
Document Number: 38-05275  
Issue  
Date  
Orig. of  
Change  
REV.  
ECN NO.  
Description of Change  
**  
114176  
3/19/02  
DSG  
Change from Spec number: 38-M-00089 to 38-05275  
Document #: 38-05275 Rev. **  
Page 8 of 8  
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