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MicroClock Programmable Clock

Generator

5X1503

Datasheet

Description

The 5X1503 is a series of small form factor programmable clock

generators intended for low-power, consumer, battery powered

applications, wearable and smart devices.

Features

▪ Proactive Power Saving (PPS) features save power during the

end device power-down mode

▪ Dynamic Frequency Control (DFC) feature allows programming

up to 4 difference frequencies that switch dynamically

The device is a 1 PLL + DCO architecture design with one

embedded crystal. The device is OTP programmable, allowing for

up to 3 unique frequency outputs. The 5X1503 has built-in unique

features such as Proactive Power Saving (PPS) and a low power

DCO to support system date/time keeping clock at 32.768kHz.

Dynamic Frequency Control (DFC) supports dynamically changing

between four different PLL frequencies via external requests with

controlled frequency changes, reducing frequency overshoot and

undershoot (ORT). The 5X1503S device can also support a

spread clock for EMI reduction. For a description of terms and

their functions, see Glossary of Features.

▪ Programmable output clock amplitude (1V, 1.1V, 1.2V and

1.8V) to support low swing clock requirement

▪ Dedicated 32kHz output with 6 clock amplitude options

(5X1503L)

▪ Integrated crystal; no external input source requirement

▪ Configurable through I2C or OTP programming

▪ Spread spectrum clock support (5X1503S)

▪ 1.8V operating supply voltage

▪ 2 × 2 mm 10-VFQFPN package

An internal OTP memory allows the user to store up to four

independent configurations that can be loaded on power-up

without programming. It can then be reprogrammed again through

the I²C interface.

Output Features

▪ 3 LVCMOS outputs, 1MHz–100MHz or 32.768kHz

▪ Low-power 32.768kHz clock supported

The 5X1503 supports three LVCMOS type outputs. Two outputs

have programmable amplitude. A low-power 32.768kHz clock is

supported with only less than 1.5μA current consumption for

system RTC reference clock needs.

Key Specifications

▪ Output cycle-cycle jitter: 50ps (typ)

▪ Low power-on fully active mode: 2mA (typ)

▪ Low-power 32.768kHz < 1.0μA (5X1503L)

5X1503 Base

Number

VCO Range

(MHz)

Description

5X1503

5X1503L

5X1503S

Standard, Integrated Crystal

Ultra Low-power, Integrated Crystal

Spread Clock, Integrated Crystal

50 – 130

500 –1100

Typical Applications

▪ SmartDevice

▪ Handheld

▪ Wearable applications

▪ Portable Consumer applications

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June 19, 2019

5X1503 Datasheet

Contents

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Output Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Key Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Device Feature and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

DFC – Dynamic Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

DFC Function Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

PPS – Proactive Power Saving Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

PPS Function Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Output Divider Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Device Output Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

5X1503 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

5X1503L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

5X1503S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Input Pin Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Digital Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Crystal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

I2C Bus DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Spread Spectrum Generation Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

General I2C Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

How to Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

How to Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Glossary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Package Outline Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Marking Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

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June 19, 2019

5X1503 Datasheet

Block Diagram

Power

Monitor

VDD

VSS

OE1

POR

OSC

OUT1

VDDO

VSS

PLL

Mux

&

Divider

OUT2

OE2

Calibration

32.768K

DCO

OUT3

OE3

SCL/DFC1

I²C Engine

Dynamic Frequency Control Logic (DFC)

SEL_DFC/SDA/DFC0

OTP memory (1 configuration)

Proactive Power Saving Logic (PPS)

Pin Assignments

Figure 1. Pin Assignments for 2.0 × 2.0 mm 10-VFQFPN Package

OUT2

1

2

3

4

5

10

9

SCL/DFC1

SEL_DFC/SDA/DFC0

OE2

8

OE1

OUT1

VDD

5X1503

VDDO

7

6

OUT3

VSS

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June 19, 2019

5X1503 Datasheet

Pin Descriptions

Table 1. Pin Descriptions

Number

Name

Type

Description

I2C clock pin/dynamic frequency input pin.

1

SCL/DFC1

Input

Functional selection pin/I2C data pin/dynamic frequency input pin.

0 = HW mode; 0 = I2C mode.

2

SEL_DFC /SDA/DFC0

I/O

3

4

OE1

OUT1

VDD

Input

OUT1 output enable pin. The pin can be configured to other functions (DFC and PPS).

Output Programmable LVCMOS clock output (32.768kHz only on 5X1503L).

Power 1.8V power supply for core, PLL, and 32kHz DCO.

5

6

VSS

GND

Connect to ground.

7

OUT3

VDDO

OE2

Output Programmable LVCMOS clock output.

Power 1.8V power supply for I/O.

8

9

Input

OUT2 output enable pin. The pin can be configured to other functions (DFC and PPS).

10

OUT2

Output Programmable LVCMOS clock output.

Device Feature and Function

DFC – Dynamic Frequency Control

▪ OTP programmable–4 different feedback fractional dividers (4 VCO frequencies) that apply to PLL.

▪ ORT (overshoot reduction) function will be applied automatically during the VCO frequency change.

▪ Smooth frequency incremental or decremental from current VCO to targeted VCO based on DFC hardware pins selection.

Figure 2. DFC Function Block Diagram

M divider

PLL

OUT DIV

Selector

N divider

00

01

10

11

DFC[1:0]

OTP/I2C

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June 19, 2019

5X1503 Datasheet

Table 2. DFC Function Priority

DFC_EN

B17[0] Read/Write

I2C

SDA_DFC0 SCL_HW_Mode_sel OE1_fun_sel OE2_fun_sel

Mode

DFC1

Notes

Latch

B18[5]

B16[6:5]

B16[3:2]

x

0

1

Yes

No

x

1

0

x

0

1

x

00–10

11

x

00 or 10

00–10

11

x

DFC disable

Select via I2C

SW

HW

B0[1]

SCL

OE2

—

B0[0]

OE1

SDA

OE1

Select via pins

Select via single pin

No

00–10

11

No

11

01

DFC Function Programming

▪ Register B0b1:0 – select DFC00–DFC11 configuration.

▪ Byte5–8 are the registers for PLL VCO setting. Based on B0b1:0 configuration selection, the data write to B5–8 will be stored in

selected configuration OTP memory.

▪ Refer to DFC Function Priority table. Select proper control pin(s) to activate DFC function.

▪ Note the DFC function can also be controlled by I2C access.

PPS – Proactive Power Saving Function

PPS (Proactive Power Saving) is an IDT patented unique design for the clock generator that proactively detects end device power down

state and then switches output clocks between normal operation clock frequency and low power mode 32kHz clock that only consumes <

1.5μA current. The system could save power when the device goes into power down or sleep mode. The PPS function diagram is shown

as below.

Figure 3. PPS Function Block Diagram

PPS

Control

Logic

Power

Down

Control

I²C

&

Logic

Low

Power

DCO

OEn

SEn

XOUT

XIN

Xtal

Oscillator

Logic

Xtal

Oscillator

PLL

MHz / kHz

Switching

Target Device

5X1503

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June 19, 2019

5X1503 Datasheet

Figure 4. PPS Assertion/Deassertion Timing Chart

MHz clock

32K clocks

PPS assertion

OUTn

OEn_PPS input

Lose an edge

PPS deassertion

OUTn

32K clocks

MHz clock

OEn_PPS input

Receive an edge

PPS Function Programming

▪ Refer to the OE Pin Function table to have proper PPS function selected for OE pin(s). Note that the register default is set to Output

Enable (OE) function for OE pins.

▪ Have proper setup to Byte 16 for OE1–OE2 function selection. For PPS function, select 10 to control register bits.

Output Divider Selection

Table 3. Output Divider Selection

Output Divider bits<2:0>

Output Divider bits<4:3>

000

001

010

011

100

101

00

01

10

11

1

2

4

8

3

6

5

7

9

11

22

44

88

10

20

40

14

28

56

18

36

72

12

24

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June 19, 2019

5X1503 Datasheet

Device Output Support

5X1503

Outputs

Frequency

Amplitude

VCO Range

Spread Spectrum

OUT1

OUT2

OUT3

1.8V

32kHz or up to 100MHz LVCMOS

50MHz – 130MHz

N/A

1V, 1.1V, 1.2V, 1.8V

5X1503L

Outputs

Frequency

Amplitude

VCO Range

Spread Spectrum

OUT1

OUT2

OUT3

32kHz

0.8V, 0.9V, 1V, 1.1V, 1.2V, 1.8V

50MHz – 130MHz

N/A

32kHz or up to 100MHz LVCMOS

1V, 1.1V,1.2V,1.8V

5X1503S

Outputs

Frequency

Amplitude

VCO Range

Spread Spectrum

OUT1

OUT2

OUT3

1.8V

32kHz or up to 100MHz LVCMOS

500MHz – 1100MHz

Available

1V, 1.1V, 1.2V, 1.8V

Input Pin Function

OE pins in the 5X1503 have multiple functions. The OE pins can be configured as output enable control (OE) or chip power-down control

(PD#) or Proactive Power Saving function (PPS). Furthermore, the OE1 pin can be configured as single or Dynamic Frequency Control

(DFC).

Table 4. OE Pin Function

OE1

OE2

Function

B16<6:5>

Function

B16<3:2>

Function

Output Enable/Disable

Global Power Down (PD#)

Proactive Power Saving Input

DFC Control

00

01

10

11

OUT1 (Default)

PD#

00

01

10

11

OUT2 (Default)

Config_SEL

OUT2_PPS

DFC1

OUT1_PPS

DFC0

Note: Config_SEL and DFC Control require the device to be in H/W mode with no I2C access

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June 19, 2019

5X1503 Datasheet

Table 5. OE Pin Function Summary

Function

OE1: OUT1

OE2: OUT2

OE1 only control OUT1 enable/disable, other outputs are not affected by this pin status.

OE2 only control OUT2 enable/disable, other outputs are not affected by this pin status.

OE1 control chip global power down (PD#) except 32.768kHz on OE1 (when 32K is enabled), When the PD# pin is active

low, the chip goes to lowest power down mode and all outputs are disabled except 32kHz output and only keep 32k/Xtal

calibration.

OE1: PD#

OE1: OUT1_PPS Config OE1 as OUT1_PPS (Proactive Power Saving) function pin.

OE2: OUT2_PPS Config OE2 as OUT2_PPS (Proactive Power Saving) function pin.

OE1:DFC0

OE2:DFC1

Config OE1 as DFC0 control pin 0.

Config OE2 as DFC1 control pin 1.

Table 6. PD# Priority

OUT1/2/3,

OUTx_PPS

PD#

I2C_OE_EN_bit

Output

Notes

0

1

X

0

1

X

0

1

stop

32KHz free run

stop

running

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June 19, 2019

5X1503 Datasheet

Spread Spectrum

The 5X1503 supports spread spectrum clocks from PLL with digital spread spectrum.

Digital Spread Spectrum

Figure 5. Digital Spread Spectrum

Step_deepth: step

Fvco

N 

How many steps: Period

2 * Fout

Fpfd

2 * Fss

period



N * SSamount

period

step 

Down spread or spread off

N = Fvco/Fpfd

N: include integer and fraction

Fvco: VCOs frequency

Fpfd: PLLs pfd frequency

Fss: spread modulation rate

SSamount: spread percentage

N will decrease to make the center frequency lower than spread off.

Example: 0.5% down spread at 32kHz modulation rate.

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June 19, 2019

5X1503 Datasheet

Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the 5X1503. These ratings, which are standard values for IDT

commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those

indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended

periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.

Table 7. Absolute Maximum Ratings

Item

Rating

Supply Voltage: V_DD, V_DDO

Inputs; DFC, OE1, OE2, SCL

Outputs: LVCMOS

-0.5V to 2.2V

-0.5V to V_DD/V_DDO

-0.5V to V_DD/V_DDO+ 0.5V

10mA

Outputs: SDA

Storage Temperature, T_STG

ESD Human Body Model

Junction Temperature

-65°C to 150°C

2000V

125°C

Thermal Characteristics

Table 8. Thermal Characteristics

Symbol

Parameter

Value

Units

θ

Theta J_B. Junction to board

Theta J_C. Junction to case

28.4

183.3

MSL1

°C/W

—

Jb

JC

Moisture Sensitivity Rating (per J-STD-020)

Recommended Operating Conditions

Table 9. Recommended Operating Conditions

Symbol

Parameter

Minimum

Typical

Maximum

Units

V_DDOUT1

V_DDOUT2

V_{DD1_8}

T_A

Power Supply Voltage for Supporting OUT1

Power Supply Voltage for Supporting OUT2/OUT3

Power Supply Voltage for Core Logic Functions

Ambient Operating Temperature

1.71

-40

1.8

—

1.89

85

V

°C

pF

C_{LOAD_OUT}

t_PU

Maximum Load Capacitance (1.8V LVCMOS only)

—

5

—

Power-up Time for all V_DDs to reach Minimum Specified Voltage

(power ramps must be monotonic)

0.05

—

3

ms

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June 19, 2019

5X1503 Datasheet

Crystal Characteristics

Table 10. Embedded Crystal Characteristics

Parameter

Test Conditions

Minimum

Typical

Maximum Units

Mode of Oscillation

—

Fundamental

Frequency

—

6

52

—

2

—

±20

80

MHz

ppm

Ω

Frequency Tolerance ¹

Equivalent Series Resistance (ESR)

Shunt Capacitance

After trimming

—

7

pF

Load Capacitance (C_L)

Maximum Crystal Drive Level

8

10

pF

—

100

μW

¹Frequency tolerance includes initial frequency, over temperature range and aging data.

DC Electrical Characteristics

Table 11. DC Electrical Characteristics – Current

V_DD= V_DDO= 1.8V ±5%, V_SS= 0V, T_A= -40°C to +85°C.

Symbol

Parameter

Conditions

Minimum Typical Maximum Units

Core Supply Current

(5X1503/5X1503L)

V_DD= V_DDO= 1.8V, Xtal = 52MHz, DCO = OFF,

no output; PLL default.

—

2.0

9.5

1.0

9.0

mA

Idd

Core Supply Current

(5X1503S)

V_DD= V_DDO= 1.8V, Xtal = 52MHz, DCO = OFF,

no output; PLL default.

PLL Supply Current

(5X1503/5X1503L)

V_DD= V_DDO= 1.8V, Xtal = 52MHz, no output;

PLL= default

Idd_PLL

Iddox

PLL Supply Current

(5X1503S)

V_DD= V_DDO= 1.8V, Xtal = 52MHz, no output;

PLL= default

LVCMOS, OUT1 = 8MHz, V_DD= V_DDO= 1.8V.

LVCMOS, OUT1 = 100MHz, V_DD= V_DDO= 1.8V.

LVCMOS, OUT1 = 8MHz, V_DD= V_DDO= 1.8V.

LVCMOS, OUT1 = 100MHz, V_DD= V_DDO= 1.8V.

—

0.5

2

mA

Output Buffer Supply

Current (5X1503/5X1503L)

0.5

2

Output Buffer Supply

Current (5X1503S)

Power Down Current

(5X1503/5X1503L)

PD asserted with V_DDand V_DDOON, I2C enable,

32.768kHz clock running.

—

310

320

7

μA

Iddpd

Power Down Current

(5X1503S)

PD asserted with V_DDand V_DDOON, I2C enable,

32.768kHz clock running.

Ultra Power Down Current PD asserted with V_DDand V_DDOON, I2C disable,

(5X1503/5X1503L) 32.768kHz clock running.

Iddupd

Ultra Power Down Current PD asserted with V_DDand V_DDOON, I2C disable,

(5X1503S) 32.768kHz clock running.

9.5

11

June 19, 2019

5X1503 Datasheet

Table 11. DC Electrical Characteristics – Current (Cont.)

V_DD= V_DDO= 1.8V ±5%, V_SS= 0V, T_A= -40°C to +85°C.

Symbol

Parameter

Conditions

Minimum Typical Maximum Units

V_DDD= 1.8V, V_DDO= GND, OUT1 = 32.768kHz

running in DCO mode, no output loads, I2C and OE

pins open.

Power Suspend Current

(5X1503)

—

1.4

1

μA

V_DDD= 1.8V, V_DDO= GND, OUT1 = 32.768kHz

running in DCO mode, no output loads, I2C and OE

pins open.

Power Suspend Current

(5X1503L)

Iddsuspend

V_DDD= 1.8V, V_DDO= GND, OUT1 = 32.768kHz

running in DCO mode, no output loads, I2C and OE

pins open.

Power Suspend Current

(5X1503S)

1.4

Table 12. DC Electrical Characteristics – Input and Output Voltage

Symbol

Parameter

Conditions

Minimum

Typical

Maximum

Units

V_OH

V_OL

I_OZDD

V_IH

Output High Voltage

Output Low Voltage

I_OH= -8mA.

I_OL= 8mA.

0.7 × V_DDO

—

V_DDO

0.25 × V_DDO

80

V

Output Leakage Current Tri-state outputs, V_DDO= 1.89V.

—

μA

V

Input High Voltage

Input Low Voltage

Single-ended inputs – DFC, OE, SDA, SCL.

0.65 × V_DDO

GND - 0.3

V_DDO+ 0.3

0.35 × V_DDO

V_IL

V

AC Electrical Characteristics

Table 13. AC Timing Electrical Characteristics

V_DDSE= 1.8V ±5%, T_A= -40°C to +85°C. Spread spectrum = OFF.

Symbol

Parameter

Conditions

Minimum Typical Maximum Units

f_IN

Integrated Xtal Frequency

Output Frequency

Input frequency limit (XIN)¹.

—

1

52

—

100

130

1100

MHz

f_OUT

Single-ended clock output limit (LVCMOS).

VCO operating frequency range (5X1503).

VCO operating frequency range (5X1503L).

VCO operating frequency range (5X1503S).

f_VCO1

f_VCO2

f_VCO3

VCO Frequency Range of PLL

50

500

PFD operating frequency range (5X1503 and

5X1503L).

f_PFD1

PFD Frequency Range of PLL1

0

—

0.125

MHz

f_PFD1

f_BW1

PFD Frequency Range of PLL1

Loop Bandwidth for PLL1

PFD operating frequency range (5X1503S).

0.8

0.001

—

100

1

MHz

ppm

Input frequency = 52MHz.

F_{32K_ACC1}32K Stability

F_{32K_ACC2}32K Stability

F_{32K_ACC3}32K Stability

Average accuracy after 24 hours².

Average accuracy after 3 days².

Average accuracy after 7 days².

42

36

32

—

12

June 19, 2019

5X1503 Datasheet

Table 13. AC Timing Electrical Characteristics (Cont.)

V_DDSE= 1.8V ±5%, T_A= -40°C to +85°C. Spread spectrum = OFF.

Symbol

Parameter

Conditions

Minimum Typical Maximum Units

Minimum Input Amplitude

Input Duty Cycle

For a 40/60% SE input duty cycle.

Duty cycle.

800

30

—

V_DD

70

mV

%

t2

t3

Measured at V_DD/2, all outputs with a crystal

or a 50% input duty cycle clock.

Output Duty Cycle

Rise/Fall Slew Rate

45

—

55

—

%

1.8V LVCMOS clock rise and fall time, 20%

to 80% of V_DDO/V_DD(output load = 2 pF).

t4³

2.0

V/ns

1.2V LVCMOS clock rise and fall time, 20%

to 80% of V_DDO/V_DD(output load = 2 pF).

Byte19<3:2> = 11 Byte19<1:0> = 11.

Rise/Fall Slew Rate

—

1.1

—

V/ns

1.1V LVCMOS clock rise and fall time, 20%

to 80% of V_DDO/V_DD(output load = 2 pF).

t4³

Rise/Fall Slew Rate

—

1.0

—

V/ns

1.0V LVCMOS clock rise and fall time, 20%

to 80% of V_DDO/V_DD(output load = 2 pF).

OUT1 1.8V 32kHz LVCMOS clock rise and

t4³

Rise/Fall Slew

fall time, 20% to 80% of V_DDO/V_DD

Byte20<2:0>=000 (5X1503L).

,

—

27.4

2.3

3.9

5.4

6.7

8.5

—

V/μs

OUT1 0.8V 32kHz LVCMOS clock rise and

fall time, 20% to 80% of V_DDO/V_DD

Byte20<2:0> = 001 (5X1503L).

,

OUT1 0.9V 32kHz LVCMOS clock rise and

fall time, 20% to 80% of V_DDO/V_DD

Byte20<2:0> = 010 (5X1503L).

,

OUT1 1.0V 32kHz LVCMOS clock rise and

fall time, 20% to 80% of V_DDO/V_DD

Byte20<2:0> = 011 (5X1503L).

,

OUT1 1.1V 32kHz LVCMOS clock rise and

fall time, 20% to 80% of V_DDO/V_DD

Byte20<2:0> = 100 (5X1503L).

,

OUT1 1.2V 32kHz LVCMOS clock rise and

fall time, 20% to 80% of V_DDO/V_DD

Byte20<2:0> = 101 (5X1503L).

,

Cycle-to-cycle jitter, 1.8V LVCMOS output

clock.

t6⁴

Clock Jitter

—

50

—

ps

OUT1 = 32.768KHz (1.8V LVCMOS)

OUT2 = 72MHz

OUT3 = 26MHz

Cycle-to-cycle jitter, 1.2V LVCMOS output

clock.

t6⁴

OUT1 = 32.768KHz (1.8V LVCMOS)

OUT2 = 72MHz

OUT3 = 26MHz

13

June 19, 2019

5X1503 Datasheet

Table 13. AC Timing Electrical Characteristics (Cont.)

V_DDSE= 1.8V ±5%, T_A= -40°C to +85°C. Spread spectrum = OFF.

Symbol

Parameter

Conditions

Minimum Typical Maximum Units

Cycle-to-cycle jitter, 1.1V LVCMOS output

clock

t6⁴

Clock Jitter

—

50

—

ps

OUT1 = 32.768kHz (1.8V LVCMOS)

OUT2 = 72MHz

OUT3 = 26MHz

Cycle-to-cycle jitter, 1.0V LVCMOS output

clock.

t6⁴

t7

—

ps

OUT1 = 32.768kHz (1.8V LVCMOS)

OUT2 = 72MHz

OUT3 = 26MHz

Skew between the same frequencies, with

outputs using the same driver format.

Output Skew

300

t8⁵

t9

Lock Time

PLL lock time from power-up.

—

5

ms

32.768kHz clock low power power-up time.

10

20

¹High Drive only when crystal frequency is higher than 30MHz.

²The data is measured on constant temperature.

³The slew rate is set by Byte19<3:2> and Byte19<1:0>.

⁴Jitter performance depend on output configuration.

⁵Includes loading the configuration bits from EPROM to PLL registers. It does not include EPROM programming/write time.

⁶Actual PLL lock time depends on the loop configuration.

2

I C Bus DC Characteristics

Table 14. I²C Bus DC Characteristics

Symbol

Parameter

Input High Level

Conditions

Minimum

Typical

Maximum

Units

V_IH

V_IL

—

0.7 × V_DDO

—

1

—

V

Input Low Level

—

0.3 × V_DDO

V_HYS

I_IN

Hysteresis of Inputs

Input Leakage Current

Output Low Voltage

—

0.05 × V_DDO

—

10

V

—

μA

V

V_OL

I_OL= 3mA.

—

0.4

Note: I2C bus is 3.3V tolerant.

14

June 19, 2019

5X1503 Datasheet

Table 15. I²C Bus AC Characteristics

Symbol

Parameter

Minimum

Typical

Maximum

Units

F_SCLK

t_BUF

Serial Clock Frequency (SCL)

Bus Free Time between STOP and START

Setup Time, START

—

100

—

400

—

kHz

μs

ns

μs

pF

ns

μs

1.3

t_SU:START

t_HD:START

t_SU:DATA

t_HD:DATA

t_OVD

0.6

—

Hold Time, START

0.6

—

Setup Time, Data Input (SDA)

Hold Time, Data Input (SDA) ¹

Output Data Valid from Clock

Capacitive Load for Each Bus Line

Rise Time, Data and Clock (SDA, SCL)

Fall Time, Data and Clock (SDA, SCL)

High Time, Clock (SCL)

100

—

0

—

0.9

400

300

—

C_B

—

20 + 0.1 × C_B

0.6

t_R

t_F

t_HIGH

t_LOW

Low Time, Clock (SCL)

1.3

—

t_SU:STOP

Setup Time, STOP

0.6

—

¹A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V_IH(MIN)of the SCL signal) to bridge the undefined

region of the falling edge of SCL.

Spread Spectrum Generation Specifications

Table 16. Spread Spectrum Generation Specifications (5X1503S only)

Symbol

Parameter

Description

Minimum

Typical

Maximum

Units

f_OUT

f_MOD

Output Frequency

Mod Frequency

Spread Value

Output frequency range.

Modulation frequency.

1

—

100

MHz

kHz

30 – 63

Amount of spread value

(programmable)–down spread.

f_SPREAD

0.15% – 2.0%

% f_OUT

15

June 19, 2019

5X1503 Datasheet

General I2C Interface Information

How to Write

How to Read

▪ Controller (host) sends a start bit

▪ Controller (host) will send a start bit

▪ Controller (host) sends the write address

▪ IDT clock will acknowledge

▪ Controller (host) sends the write address

▪ IDT clock will acknowledge

▪ Controller (host) sends the beginning byte location = N

▪ IDT clock will acknowledge

▪ Controller (host) sends the beginning byte location = N

▪ IDT clock will acknowledge

▪ Controller (host) sends the byte count = X

▪ IDT clock will acknowledge

▪ Controller (host) will send a separate start bit

▪ Controller (host) sends the read address

▪ IDT clock will acknowledge

▪ Controller (host) starts sending Byte N through Byte N+X-1

▪ IDT clock will acknowledge each byte one at a time

▪ Controller (host) sends a stop bit

▪ IDT clock will send the data byte count = X

▪ IDT clock sends Byte N+X-1

▪ IDT clock sends Byte 0 through Byte X (if X_(H)was written to

Index Block Write Operation

Byte 8)

Controller (Host)

starT bit

Slave Address

WR WRite

IDT (Slave/Receiver)

▪ Controller (host) will need to acknowledge each byte

▪ Controller (host) will send a not acknowledge bit

▪ Controller (host) will send a stop bit

T

ACK

Index Block Read Operation

Beginning Byte = N

Data Byte Count = X

Beginning Byte N

Controller (Host)

starT bit

IDT (Slave/Receiver)

T

Slave Address

WRite

WR

ACK

Beginning Byte = N

O

RT

RD

Repeat starT

Slave Address

ReaD

Byte N + X - 1

ACK

P

stoP bit

Data Byte Count=X

Beginning Byte N

ACK

O

Byte N + X - 1

N

P

Not acknowledge

stoP bit

16

June 19, 2019

5X1503 Datasheet

Byte 0: General Control

Byte 00h

Name

Control Function

Type

0

1

PWD

OTP memory

non-programmed

OTP memory

programmed

Bit 7

OTP_Burned

OTP TRIM

OTP memory programming indication

R/W

0

OTP TRIM bits

non-programmed

OTP TRIM bits

programmed

Bit 6

OTP memory programming indication

R/W

0

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

I2C_addr[1]

I2C_addr[0]

I2C address select bit 1

I2C address select bit 0

R/W

0

00: D0 / 01: D2

10: D4 / 11: D6

OTP TRIM Protect

OTP Configure Select 2

OTP Configure Select <1>

OTP TRIM bits memory protection

OTP Config Select Bit

read/write

Config 0

write locked

Config 1

DFC Config Select Bit 1

00: DFC Config 0

01: DFC Config 1

10: DFC Config 2

11: DFC Config 3

Bit 0

OTP Configure Select <0>

DFC Config Select Bit 0

R/W

0

Byte 1: Dash Code ID (optional)

Byte 01h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

XTAL_DIV2

XTAL Divider

Dash code ID

R/W

Div /2

—

Bypass

0

DashCode ID[6]

DashCode ID[5]

DashCode ID[4]

DashCode ID[3]

DashCode ID[2]

DashCode ID[1]

DashCode ID[0]

—

Byte 2: Crystal Cap Setting

Byte 02h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Xtal_Cap[3]

Xtal_Cap[2]

Xtal_Cap[1]

Xtal_Cap[0]

PPS Hyst Prog

Xtal cap load trimming bits

PPS Hysteresis Prog Bit1

R/W

0

1

0

x1 x2

x4 x8

total 15pF

00: 20mV

01: 40mV

10: 60mV

11: 80mV

Bit 2

PPS Hyst Prog

PPS Hysteresis Prog Bit0

R/W

0

Bit 1

Bit 0

PPS Vbias Prog

PPS Vbias Prog Bit 1

PPS Vbias Prog Bit 0

R/W

—

0

17

June 19, 2019

5X1503 Datasheet

Byte 3: OTP Protect

Byte 03h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

OTP Configure 3 Protect

OTP Configure 2 Protect

OTP Configure 1 Protect

OTP Configure 0 Protect

PPS2 Amp Prog

—

R/W

read/write

write locked

0

—

PPS OE2 Amplitude Prog Bit 1

00: 400mV

01: 500mV

10: 600mV

11: 700mV

Bit 2

Bit 1

Bit 0

PPS2 Amp Prog

PPS1 Amp Prog

PPS OE2 Amplitude Prog Bit 0

PPS OE1 Amplitude Prog Bit 1

PPS OE1 Amplitude Prog Bit 0

R/W

0

00: 400mV

01: 500mV

10: 600mV

11: 700mV

Byte 4: (Apply to 5X1503S)

Byte 04h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

UltraPowerDown

EN DIFF CLKIN

PLL HRS EN

Ultra Power Down

R/W

disabled

normal

disabled

—

enabled

0

Enable Differential Clkin on X1/X2

-

enable (shift 4 bits)

PLL EN 3rd

-

enabled

Reserved

—

PLL_FB_INT[10]

PLL_FB_INT[9]

PLL_FB_INT[8]

PLL feedback integer divider 10

PLL feedback integer divider 9

PLL feedback integer divider 8

—

Byte 4: (Apply to 5X1503/5X1503L)

Byte 04h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

UltraPowerDown

EN DIFF CLKIN

PLL HRS EN

Ultra Power Down

Enable Differential Clkin on X1/X2

—

R/W

disabled

normal

disabled

—

enabled

0

enabled

enable (shift 4 bits)

PLL EN 3rd

—

enabled

—

SEL_PREDIV

PLL_FB_INT[10]

PLL_FB_INT[9]

PLL_FB_INT[8]

Divide by 4

PLL feedback integer divider 10

PLL feedback integer divider 9

PLL feedback integer divider 8

—

18

June 19, 2019

5X1503 Datasheet

Byte 5: PLL Integer Feedback Divider (Apply to 5X1503S)

Byte 05h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL_FB_INT_DIV[7]

PLL_FB_INT_DIV[6]

PLL_FB_INT_DIV[5]

PLL_FB_INT_DIV[4]

PLL_FB_INT_DIV[3]

PLL_FB_INT_DIV[2]

PLL_FB_INT_DIV[1]

PLL_FB_INT_DIV[0]

PLL feedback integer divider 7

PLL feedback integer divider 6

PLL feedback integer divider 5

PLL feedback integer divider 4

PLL feedback integer divider 3

PLL feedback integer divider 2

PLL feedback integer divider 1

PLL feedback integer divider 0

R/W

—

0

1

0

1

0

Byte 5: PLL Integer Feedback Divider (Apply to 5X1503/5X1503L)

Byte 05h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL_FB_INT_DIV[7]

PLL_FB_INT_DIV[6]

PLL_FB_INT_DIV[5]

PLL_FB_INT_DIV[4]

PLL_FB_INT_DIV[3]

PLL_FB_INT_DIV[2]

PLL_FB_INT_DIV[1]

PLL_FB_INT_DIV[0]

PLL feedback integer divider 7

PLL feedback integer divider 6

PLL feedback integer divider 5

PLL feedback integer divider 4

PLL feedback integer divider 3

PLL feedback integer divider 2

PLL feedback integer divider 1

PLL feedback integer divider 0

R/W

—

0

1

0

Byte 6: PLL Fractional Feedback Divider

Byte 06h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL_FB_FRC_DIV[15]

PLL_FB_FRC_DIV[14]

PLL_FB_FRC_DIV[13]

PLL_FB_FRC_DIV[12]

PLL_FB_FRC_DIV[11]

PLL_FB_FRC_DIV[10]

PLL_FB_FRC_DIV[9]

PLL_FB_FRC_DIV[8]

PLL feedback fractional divider 15

PLL feedback fractional divider 14

PLL feedback fractional divider 13

PLL feedback fractional divider 12

PLL feedback fractional divider 11

PLL feedback fractional divider 10

PLL feedback fractional divider 9

PLL feedback fractional divider 8

R/W

—

0

19

June 19, 2019

5X1503 Datasheet

Byte 7: Fractional Feedback Divider

Byte 07h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL_FB_FRC_DIV[7]

PLL_FB_FRC_DIV[6]

PLL_FB_FRC_DIV[5]

PLL_FB_FRC_DIV[4]

PLL_FB_FRC_DIV[3]

PLL_FB_FRC_DIV[2]

PLL_FB_FRC_DIV[1]

PLL_FB_FRC_DIV[0]

PLL feedback fractional divider 7

PLL feedback fractional divider 6

PLL feedback fractional divider 5

PLL feedback fractional divider 4

PLL feedback fractional divider 3

PLL feedback fractional divider 2

PLL feedback fractional divider 1

PLL feedback fractional divider 0

R/W

—

0

Byte 8: PLL Spread Spectrum Control

Byte 08h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL_STEP[15]

PLL_STEP[14]

PLL_STEP[13]

PLL_STEP[12]

PLL_STEP[11]

PLL_STEP[10]

PLL_STEP[9]

PLL_STEP[8]

PLL spread step size control bit 15

PLL spread step size control bit 14

PLL spread step size control bit 13

PLL spread step size control bit 12

PLL spread step size control bit 11

PLL spread step size control bit 10

PLL spread step size control bit 9

PLL spread step size control bit 8

R/W

—

0

Byte 9: PLL Spread Spectrum Control

Byte 09h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL_STEP[7]

PLL_STEP[6]

PLL_STEP[5]

PLL_STEP[4]

PLL_STEP[3]

PLL_STEP[2]

PLL_STEP[1]

PLL_STEP[0]

PLL spread step size control bit 7

PLL spread step size control bit 6

PLL spread step size control bit 5

PLL spread step size control bit 4

PLL spread step size control bit 3

PLL spread step size control bit 2

PLL spread step size control bit 1

PLL spread step size control bit 0

R/W

—

0

20

June 19, 2019

5X1503 Datasheet

Byte 10: PLL Period Control

Byte 0Ah

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL_PERIOD[7]

PLL_PERIOD[6]

PLL_PERIOD[5]

PLL_PERIOD[4]

PLL_PERIOD[3]

PLL_PERIOD[2]

PLL_PERIOD[1]

PLL_PERIOD[0]

PLL period control bit 7

PLL period control bit 6

PLL period control bit 5

PLL period control bit 4

PLL period control bit 3

PLL period control bit 2

PLL period control bit 1

PLL period control bit 0

R/W

—

0

Byte 11: PLL M Divider Setting (Apply to 5X1503S)

Byte 0Bh

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL_MDIV1

PLL_MDIV2

PLL_MDIV[5]

PLL_MDIV[4]

PLL_MDIV[3]

PLL_MDIV[2]

PLL_MDIV[1]

PLL_MDIV[0]

PLL reference divider 1

R/W

disable M DIV1

disable M DIV2

bypadd divider (/1)

bypadd divider (/2)

1

0

1

0

1

0

PLL reference divider 2

PLL reference divider control bit 5

PLL reference divider control bit 4

PLL reference divider control bit 3

PLL reference divider control bit 2

PLL reference divider control bit 1

PLL reference divider control bit 0

3–63, default is 26

Byte 11: PLL M Divider Setting (Apply to 5X1503/5X1503L)

Byte 0Bh

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL_MDIV1

PLL_MDIV2

PLL_MDIV[5]

PLL_MDIV[4]

PLL_MDIV[3]

PLL_MDIV[2]

PLL_MDIV[1]

PLL_MDIV[0]

PLL reference divider 1

R/W

disable M DIV1

disable M DIV2

bypadd divider (/1)

bypadd divider (/2)

0

1

0

1

0

PLL reference divider 2

PLL reference divider control bit 5

PLL reference divider control bit 4

PLL reference divider control bit 3

PLL reference divider control bit 2

PLL reference divider control bit 1

PLL reference divider control bit 0

3–63, default is 26

21

June 19, 2019

5X1503 Datasheet

Byte 12: PLL Loop R Setting (Apply to 5X1503S)

Byte 0Ch

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

PLL_MDIV_Doubler

PLL IREF

PLL reference divider - doubler

PLL CP reference current

R/W

disable

1X

enable

2X

0

1

0

PLL_SSEN

PLL spread spectrum enable

PLL Loop filter resister 100kOhm

PLL Loop filter resister 50kOhm

PLL Loop filter resister 25kOhm

PLL Loop filter resister 12.5kOhm

disable

bypass

enable

PLL_R100K

PLL_R50K

plus 100Kohm

plus 50Kohm

plus 25Kohm

plus 12.5Kohm

PLL_R25K

PLL_R12.5K

only 1Kohm

applied

Bit 0

PLL_R1K

PLL Loop filter resister 1kOhm

R/W

bypass

1

Byte 12: PLL Loop R Setting (Apply to 5X1503/5X1503L)

Byte 0Ch

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL_MDIV_Doubler

PLL IREF

PLL reference divider - doubler

PLL CP reference current

R/W

disable

1X

enable

2X

0

1

PLL_SSEN

PLL_R100K

PLL_R75K

PLL spread spectrum enable

PLL Loop filter resister 100kOhm

PLL Loop filter resister 75kOhm

PLL Loop filter resister 50kOhm

PLL Loop filter resister 25kOhm

PLL Loop filter resister 12.5kOhm

disable

bypass

enable

plus 100kOhm

plus 75kOhm

plus 50kOhm

plus 25kOhm

plus 12.5kOhm

PLL_R50K

PLL_R25K

PLL_R12.5K

Byte 13: PLL Charge Pump Control (Apply to 5X1503S)

Byte 0Dh

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL_CP_31X

PLL_CP_16X

PLL_CP_8X

PLL_CP_4X

PLL_CP_2X

PLL_CP_1X

PLL_CP_/24

PLL_CP_/3

PLL charge pump control

R/W

—

x31

x16

x8

1

0

1

0

1

x4

x2

x1

/24

/3

22

June 19, 2019

5X1503 Datasheet

Byte 13: PLL Charge Pump Control (Apply to 5X1503/5X1503L)

Byte 0Dh

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL_CP_31X

PLL_CP_16X

PLL_CP_8X

PLL_CP_4X

PLL_CP_2X

PLL_CP_1X

PLL_CP_/24

PLL_CP_/3

PLL charge pump control

R/W

—

x31

x16

x8

0

1

0

1

0

x4

x2

x1

/24

/3

Byte 14: Output Divider1 Control (Apply to 5X1503S)

Byte 0Eh

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

OUTDIV1[4]

OUTDIV1[3]

Output divider1 control bit 4

Output divider1 control bit 3

Output divider1 control bit 2

Output divider1 control bit 1

Output divider1 control bit 0

OUTDIV2 Source Select

OUTDIV1 Source Select

R/W

0

1

0

1

0

1

DIV1[3:2] = 1,3,5,7,9,11;

DIV1[1:0] = 1,2,4,8;

D e f a u l t D i v i d e r = 0 0 0 0 1 = 3

OUTDIV1[2]

OUTDIV1[1]

OUTDIV1[0]

OUTDIV2 Source Select

OUTDIV1 Source Select

From REF

OUTDIV2_Source

From PLL

enable seed to

OUTDIV2

Bit 0

OUTDIV1 Seed

R/W

disabled

0

Byte 14: Output Divider1 Control (Apply to 5X1503/5X1503L)

Byte 0Eh

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

OUTDIV1[4]

OUTDIV1[3]

Output divider1 control bit 4

Output divider1 control bit 3

Output divider1 control bit 2

Output divider1 control bit 1

Output divider1 control bit 0

OUTDIV2 Source Select

OUTDIV1 Source Select

R/W

0

1

0

1

DIV1[3:2] = 1,3,5,7,9,11;

DIV1[1:0] = 1,2,4,8;

D e f a u l t D i v i d e r = 0 0 0 0 1 = 3

OUTDIV1[2]

OUTDIV1[1]

OUTDIV1[0]

OUTDIV2 Source Select

OUTDIV1 Source Select

From REF

OUTDIV2_Source

From PLL

enable seed to

OUTDIV2

Bit 0

OUTDIV1 Seed

R/W

disabled

0

23

June 19, 2019

5X1503 Datasheet

Byte 15: Output Divider 2 Control

Byte 0Fh

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

OUTDIV2[4]

OUTDIV2[3]

Output divider2 control bit 4

Output divider2 control bit 3

Output divider2 control bit 2

Output divider2 control bit 1

Output divider2 control bit 0

OUT3 State Select

R/W

0

1

DIV1[3:2] = 1, 3, 5, 7, 9, 11;

DIV1[1:0] = 1, 2, 4, 8;

D e f a u l t D i v i d e r = 0 0 0 0 1 = 3

OUTDIV2[2]

OUTDIV2[1]

OUTDIV2[0]

OUT3_OUT_TRI

OUT2_OUT_TRI

OUT1_OUT_TRI

normal

Tristate

0

OUT2 State Select

Tristate

OUT1 State Select

Byte 16: PLL Operation Control Register

Byte 10h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

OUT1_EN

OUT1 output enable control

OE1 pin function selection bit 1

OE1 pin function selection bit 0

OUT2 output enable control

OE2 pin function selection bit 1

OE2 pin function selection bit 0

OUT2 Freerun enable control

OUT1 Freerun enable control

R/W

disable

enable

1

0

1

0

1

0

OE1_fun_sel[1]

OE1_fun_sel[0]

OUT2_EN

11: DFC0 10: OUT1_PPS

01: PD# 00: OUT1 OE

disable

enable

OE2_fun_sel[1]

OE2_fun_sel[0]

OUT2 Freerun

OUT1 Freerun

11: DFC1 10: OUT2_PPS

01: Config_SEL 00: OUT2 OE

Freerun

normal

Byte 17: OE and DFC Control

Byte 11h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

OUT1 CLKSEL 1

OUT1 CLKSEL 0

OUT2 CLKSEL 1

OUT2 CLKSEL 0

OUT3 CLKSEL 1

OUT3 CLKSEL 0

OUT3_EN

OUT1 output clock selection

OUT2 output clock selection

OUT3 output clock selection

OUT3 output enable control

DFC function control

R/W

0

1

0

1

0

00: CLK32K, 01: OUTDIV2

10: NA, 11: OUTDIV1

00: CLK32K, 01: OUTDIV2

10: NA, 11: OUTDIV1

00: CLK32K, 01: OUTDIV2

10: REF, 11: OUTDIV1

disable

enable

DFC_EN

24

June 19, 2019

5X1503 Datasheet

Byte 18: Control Register

Byte 12h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL PDB

PLL Powerdown enable control

PLL Lock Bypass enable control

R/W

Powerdown

Bypass

N/A

Not powerdown

Not Bypass

DFC1

1

0

PLL LOCKBYPASS

SCL HW Mode Sel

PPS PDB EN

SCL in hardware mode function select R/W

PPS PDB enable control

PPS2 Timer select bit 1

PPS2 Timer select bit 0

PPS1 Timer select bit 1

PPS1 Timer select bit 0

R/W

disable

enable

PPS2 Timer_sel<1>

PPS2 Timer_sel<0>

PPS1 Timer_sel<1>

PPS1 Timer_sel<0>

00: 100μs 01: 200μs

10: 400μs 11: 800μs

00: 100μs 01: 200μs

10: 400μs 11: 800μs

Byte 19: Control Register

Byte 13h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

OUT1 CLK Invert

OUT2 CLK Invert

OUT3 CLK Invert

OUT3 Freerun

OUT1 CLK Invert control

OUT2 CLK Invert control

R/W

Non-Invert

Freerun

Invert

normal

0

1

0

OUT3 CLK Invert control

OUT3 Freerun enable control

OUT2 Amplitude Select control

OUT3 Amplitude Select control

OUT2 Amp OUT 1

OUT2 Amp OUT 0

OUT3 Amp OUT 1

OUT3 Amp OUT 0

00: 1.8V 01: 1.0V

10: 1.1V 11: 1.0V

00: 1.8V 01: 1.0V

10: 1.1V 11: 1.0V

Byte 20: OUT1 and DIV4 Control (Apply to 5X1503/5X1503S)

Byte 14h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

I2C_PDB

Ref_free_run

chip power down control bit

Reference clock output (OUT2/OUT3)

OUT clocks free run control

PDB polarity control bit

Bypass AC cap in X1 (5X1503 only)

Reserved

R/W

power down

normal

1

0

1

stop

freerun

free_run_output_config

PDB Invert

OUT2 free run

OUT2/3 free run

Non-Invert

Invert

Bypass

—

BYP_AC

normal

—

Reserved

—

Reserved

—

25

June 19, 2019

5X1503 Datasheet

Byte 20: OUT1 and DIV4 Control (Apply to 5X1503L)

Byte 14h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

I2C_PDB

Ref_free_run

chip power down control bit

Reference clock output (OUT2/OUT3)

OUT clocks free run control

PDB polarity control bit

R/W

power down

stop

normal

freerun

1

0

1

free_run_output_config

PDB Invert

OUT2 free run

Non-Invert

normal

OUT2/3 free run

Invert

BYP_AC

Bypass AC cap in X1

Bypass

CLK32K Low Drive Amp

Select<2:0>

CLK32K Low Drive Amplitude

Select<2:0>

000: 1.8V 001: 0.8V 010: 0.9V

011: 1.0V 100: 1.1V 101:1.2V

Glossary of Features

Table 17. Glossary of Features

Term

Function Description

Apply to

Dynamic Frequency Control from selected PLL (TBD) to support two VCO frequencies–two different output

frequencies by assigning H/W pin state changes (H-L or L-H). Needs to have frequency change Glitch-free

function in order to not crash application system.

DFC

ORT

OE

All

Overshoot Reduction Technology–when the PLL performs VCO frequency changes by DFC, or manually

programming, the VCO changes frequencies smoothly to target frequency without overshoot or undershoot.

All

Output Enable function. High active. Each output can be controlled by assigned OE pin and the dedicated

OE pin can be OTP programmable as Global Power Down function (PD#) or Output enable (OE) or proactive

power saving function (PPS).

Programmable Calibration Time, for 32K DCO, the programmable calibration time will help power saving or

output accuracy adjustments.

PCT

The output clock should not have short pulses that will kill the application system, the output frequency

switch (based on DFC) should has glitch free function.

Glitch-free

SS

All

5X1503S

All

Spread Spectrum Clock

Proactive Power Saving. Utilizes OE pin as monitor pin for end device X2 clock status. See PPS – Proactive

Power Saving Function description for details.

PPS

26

June 19, 2019

5X1503 Datasheet

Package Outline Drawings

The package outline drawings are appended at the end of this document and are accessible from the link below. The package information

is the most current data available.

www.idt.com/document/psc/10-vfqfpn-package-outline-drawing-20-x-20-x-10-mm-body-epad-16-x-08-mm-04mm-pitch-nlg10p1

Ordering Information

Orderable Part Number

Package

Shipping Packaging

Temperature

5X1503-xxxNLGI

5X1503-xxxNLGI8

5X1503L-xxxNLGI

5X1503L-xxxNLGI8

5X1503S-xxxNLGI

5X1503S-xxxNLGI8

2.0 × 2.0 × 1.0 mm 10-VFQFPN

Tray

Reel

Tray

Reel

Tray

Reel

-40° to +85°C

Marking Diagrams

5X1503

▪ Line 1 is the truncated part number and indicates the following:

• “D” denotes 5X1503; “xxx” denotes dash code.

• “E” denotes 5X1503L; “xxx” denotes dash code.

• “F” denotes 5X1503S; “xxx” denotes dash code.

▪ Line 2 indicates the following:

Dxxx

YW**

• “YW” is the last digit of the year and work week the part was assembled.

• “**” denotes sequential lot number.

5X1503L

Exxx

YW**

5X1503S

Fxxx

YW**

27

June 19, 2019

5X1503 Datasheet

Revision History

Revision Date

Description of Change

June 19, 2019

Initial release.

Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 USA

www.IDT.com

Sales

Tech Support

www.IDT.com/go/support

1-800-345-7015 or 408-284-8200

Fax: 408-284-2775

www.IDT.com/go/sales

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time,

without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same

way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability

of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not

convey any license under intellectual property rights of IDT or any third parties.

IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be rea-

sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property

28

June 19, 2019

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IDT	5X1503-XXXNLGI8	[ PROC SPECIFIC CLOCK GENERATOR ]	28 页
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IDT	5X1503L-XXXNLGI8	[ PROC SPECIFIC CLOCK GENERATOR ]	28 页
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